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This register is incremented at rate of 16384Hz (~16779Hz on SGB). Writing any value to this register resets it to $00. Additionally, this register is reset when executing the stop instruction, and only begins ticking again once stop mode is exited. This also occurs during a speed switch. (TODO: how is it affected by the wait after a speed switch?)
The text was updated successfully, but these errors were encountered:
FF04 - DIV - Divider Register (R/W)
This register is incremented at rate of 16384Hz (~16779Hz on SGB). Writing any value to this register resets it to $00. Additionally, this register is reset when executing the stop instruction, and only begins ticking again once stop mode is exited. This also occurs during a speed switch. (TODO: how is it affected by the wait after a speed switch?)
The text was updated successfully, but these errors were encountered: