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mips.h
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mips.h
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/* Definitions of target machine for GNU compiler. MIPS version.
Copyright (C) 1989-2018 Free Software Foundation, Inc.
Contributed by A. Lichnewsky (lich@inria.inria.fr).
Changed by Michael Meissner (meissner@osf.org).
64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
Brendan Eich (brendan@microunity.com).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#include "config/vxworks-dummy.h"
#ifdef GENERATOR_FILE
/* This is used in some insn conditions, so needs to be declared, but
does not need to be defined. */
extern int target_flags_explicit;
#endif
/* MIPS external variables defined in mips.c. */
/* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
to work on a 64-bit machine. */
#define ABI_32 0
#define ABI_N32 1
#define ABI_64 2
#define ABI_EABI 3
#define ABI_O64 4
/* Masks that affect tuning.
PTF_AVOID_BRANCHLIKELY_SPEED
Set if it is usually not profitable to use branch-likely instructions
for this target when optimizing code for speed, typically because
the branches are always predicted taken and so incur a large overhead
when not taken.
PTF_AVOID_BRANCHLIKELY_SIZE
As above but when optimizing for size.
PTF_AVOID_BRANCHLIKELY_ALWAYS
As above but regardless of whether we optimize for speed or size.
PTF_AVOID_IMADD
Set if it is usually not profitable to use the integer MADD or MSUB
instructions because of the overhead of getting the result out of
the HI/LO registers. */
#define PTF_AVOID_BRANCHLIKELY_SPEED 0x1
#define PTF_AVOID_BRANCHLIKELY_SIZE 0x2
#define PTF_AVOID_BRANCHLIKELY_ALWAYS (PTF_AVOID_BRANCHLIKELY_SPEED | \
PTF_AVOID_BRANCHLIKELY_SIZE)
#define PTF_AVOID_IMADD 0x4
/* Information about one recognized processor. Defined here for the
benefit of TARGET_CPU_CPP_BUILTINS. */
struct mips_cpu_info {
/* The 'canonical' name of the processor as far as GCC is concerned.
It's typically a manufacturer's prefix followed by a numerical
designation. It should be lowercase. */
const char *name;
/* The internal processor number that most closely matches this
entry. Several processors can have the same value, if there's no
difference between them from GCC's point of view. */
enum processor cpu;
/* The ISA level that the processor implements. */
int isa;
/* A mask of PTF_* values. */
unsigned int tune_flags;
};
#include "config/mips/mips-opts.h"
/* Macros to silence warnings about numbers being signed in traditional
C and unsigned in ISO C when compiled on 32-bit hosts. */
#define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
#define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
#define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
/* Run-time compilation parameters selecting different hardware subsets. */
/* True if we are generating position-independent VxWorks RTP code. */
#define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
/* Compact branches must not be used if the user either selects the
'never' policy or the 'optimal' policy on a core that lacks
compact branch instructions. */
#define TARGET_CB_NEVER (mips_cb == MIPS_CB_NEVER \
|| (mips_cb == MIPS_CB_OPTIMAL \
&& !ISA_HAS_COMPACT_BRANCHES))
/* Compact branches may be used if the user either selects the
'always' policy or the 'optimal' policy on a core that supports
compact branch instructions. */
#define TARGET_CB_MAYBE (TARGET_CB_ALWAYS \
|| (mips_cb == MIPS_CB_OPTIMAL \
&& ISA_HAS_COMPACT_BRANCHES))
/* Compact branches must always be generated if the user selects
the 'always' policy or the 'optimal' policy om a core that
lacks delay slot branch instructions. */
#define TARGET_CB_ALWAYS (mips_cb == MIPS_CB_ALWAYS \
|| (mips_cb == MIPS_CB_OPTIMAL \
&& !ISA_HAS_DELAY_SLOTS))
/* Special handling for JRC that exists in microMIPSR3 as well as R6
ISAs with full compact branch support. */
#define ISA_HAS_JRC ((ISA_HAS_COMPACT_BRANCHES \
|| TARGET_MICROMIPS) \
&& mips_cb != MIPS_CB_NEVER)
/* True if the output file is marked as ".abicalls; .option pic0"
(-call_nonpic). */
#define TARGET_ABICALLS_PIC0 \
(TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
/* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
#define TARGET_ABICALLS_PIC2 \
(TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
/* True if the call patterns should be split into a jalr followed by
an instruction to restore $gp. It is only safe to split the load
from the call when every use of $gp is explicit.
See mips_must_initialize_gp_p for details about how we manage the
global pointer. */
#define TARGET_SPLIT_CALLS \
(TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
/* True if we're generating a form of -mabicalls in which we can use
operators like %hi and %lo to refer to locally-binding symbols.
We can only do this for -mno-shared, and only then if we can use
relocation operations instead of assembly macros. It isn't really
worth using absolute sequences for 64-bit symbols because GOT
accesses are so much shorter. */
#define TARGET_ABSOLUTE_ABICALLS \
(TARGET_ABICALLS \
&& !TARGET_SHARED \
&& TARGET_EXPLICIT_RELOCS \
&& !ABI_HAS_64BIT_SYMBOLS)
/* True if we can optimize sibling calls. For simplicity, we only
handle cases in which call_insn_operand will reject invalid
sibcall addresses. There are two cases in which this isn't true:
- TARGET_MIPS16. call_insn_operand accepts constant addresses
but there is no direct jump instruction. It isn't worth
using sibling calls in this case anyway; they would usually
be longer than normal calls.
- TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
accepts global constants, but all sibcalls must be indirect. */
#define TARGET_SIBCALLS \
(!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
/* True if we need to use a global offset table to access some symbols. */
#define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
/* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
#define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
/* True if TARGET_USE_GOT and if $gp is a call-saved register. */
#define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
/* True if we should use .cprestore to store to the cprestore slot.
We continue to use .cprestore for explicit-reloc code so that JALs
inside inline asms will work correctly. */
#define TARGET_CPRESTORE_DIRECTIVE \
(TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
/* True if we can use the J and JAL instructions. */
#define TARGET_ABSOLUTE_JUMPS \
(!flag_pic || TARGET_ABSOLUTE_ABICALLS)
/* True if indirect calls must use register class PIC_FN_ADDR_REG.
This is true for both the PIC and non-PIC VxWorks RTP modes. */
#define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
/* True if .gpword or .gpdword should be used for switch tables. */
#define TARGET_GPWORD \
(TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
/* True if the output must have a writable .eh_frame.
See ASM_PREFERRED_EH_DATA_FORMAT for details. */
#ifdef HAVE_LD_PERSONALITY_RELAXATION
#define TARGET_WRITABLE_EH_FRAME 0
#else
#define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
#endif
/* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
#ifdef HAVE_AS_DSPR1_MULT
#define ISA_HAS_DSP_MULT ISA_HAS_DSP
#else
#define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
#endif
/* ISA has LSA available. */
#define ISA_HAS_LSA (mips_isa_rev >= 6 || ISA_HAS_MSA)
/* ISA has DLSA available. */
#define ISA_HAS_DLSA (TARGET_64BIT \
&& (mips_isa_rev >= 6 \
|| ISA_HAS_MSA))
/* The ISA compression flags that are currently in effect. */
#define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
/* Generate mips16 code */
#define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
/* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
#define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
/* Generate mips16e register save/restore sequences. */
#define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
/* True if we're generating a form of MIPS16 code in which general
text loads are allowed. */
#define TARGET_MIPS16_TEXT_LOADS \
(TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
/* True if we're generating a form of MIPS16 code in which PC-relative
loads are allowed. */
#define TARGET_MIPS16_PCREL_LOADS \
(TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
/* Generic ISA defines. */
#define ISA_MIPS1 (mips_isa == 1)
#define ISA_MIPS2 (mips_isa == 2)
#define ISA_MIPS3 (mips_isa == 3)
#define ISA_MIPS4 (mips_isa == 4)
#define ISA_MIPS32 (mips_isa == 32)
#define ISA_MIPS32R2 (mips_isa == 33)
#define ISA_MIPS32R3 (mips_isa == 34)
#define ISA_MIPS32R5 (mips_isa == 36)
#define ISA_MIPS32R6 (mips_isa == 37)
#define ISA_MIPS64 (mips_isa == 64)
#define ISA_MIPS64R2 (mips_isa == 65)
#define ISA_MIPS64R3 (mips_isa == 66)
#define ISA_MIPS64R5 (mips_isa == 68)
#define ISA_MIPS64R6 (mips_isa == 69)
/* Architecture target defines. */
#define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
#define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
#define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
#define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
#define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
#define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
#define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
#define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
#define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
#define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
#define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
#define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
#define TARGET_MIPS8000 (mips_arch == PROCESSOR_R8000)
#define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
#define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
|| mips_arch == PROCESSOR_OCTEON2 \
|| mips_arch == PROCESSOR_OCTEON3)
#define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2 \
|| mips_arch == PROCESSOR_OCTEON3)
#define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
|| mips_arch == PROCESSOR_SB1A)
#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
#define TARGET_XLP (mips_arch == PROCESSOR_XLP)
/* Scheduling target defines. */
#define TUNE_20KC (mips_tune == PROCESSOR_20KC)
#define TUNE_24K (mips_tune == PROCESSOR_24KC \
|| mips_tune == PROCESSOR_24KF2_1 \
|| mips_tune == PROCESSOR_24KF1_1)
#define TUNE_74K (mips_tune == PROCESSOR_74KC \
|| mips_tune == PROCESSOR_74KF2_1 \
|| mips_tune == PROCESSOR_74KF1_1 \
|| mips_tune == PROCESSOR_74KF3_2)
#define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
|| mips_tune == PROCESSOR_LOONGSON_2F)
#define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
#define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
#define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
#define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
#define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
#define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
#define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
#define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
#define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
#define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
#define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
#define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
#define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
|| mips_tune == PROCESSOR_OCTEON2 \
|| mips_tune == PROCESSOR_OCTEON3)
#define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
|| mips_tune == PROCESSOR_SB1A)
#define TUNE_P5600 (mips_tune == PROCESSOR_P5600)
#define TUNE_I6400 (mips_tune == PROCESSOR_I6400)
#define TUNE_P6600 (mips_tune == PROCESSOR_P6600)
/* Whether vector modes and intrinsics for ST Microelectronics
Loongson-2E/2F processors should be enabled. In o32 pairs of
floating-point registers provide 64-bit values. */
#define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
&& (TARGET_LOONGSON_2EF \
|| TARGET_LOONGSON_3A))
/* True if the pre-reload scheduler should try to create chains of
multiply-add or multiply-subtract instructions. For example,
suppose we have:
t1 = a * b
t2 = t1 + c * d
t3 = e * f
t4 = t3 - g * h
t1 will have a higher priority than t2 and t3 will have a higher
priority than t4. However, before reload, there is no dependence
between t1 and t3, and they can often have similar priorities.
The scheduler will then tend to prefer:
t1 = a * b
t3 = e * f
t2 = t1 + c * d
t4 = t3 - g * h
which stops us from making full use of macc/madd-style instructions.
This sort of situation occurs frequently in Fourier transforms and
in unrolled loops.
To counter this, the TUNE_MACC_CHAINS code will reorder the ready
queue so that chained multiply-add and multiply-subtract instructions
appear ahead of any other instruction that is likely to clobber lo.
In the example above, if t2 and t3 become ready at the same time,
the code ensures that t2 is scheduled first.
Multiply-accumulate instructions are a bigger win for some targets
than others, so this macro is defined on an opt-in basis. */
#define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
|| TUNE_MIPS4120 \
|| TUNE_MIPS4130 \
|| TUNE_24K \
|| TUNE_P5600)
#define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
#define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
/* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
directly accessible, while the command-line options select
TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
in use. */
#define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
#define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
/* TARGET_FLOAT64 represents -mfp64 and TARGET_FLOATXX represents
-mfpxx, derive TARGET_FLOAT32 to represent -mfp32. */
#define TARGET_FLOAT32 (!TARGET_FLOAT64 && !TARGET_FLOATXX)
/* TARGET_O32_FP64A_ABI represents all the conditions that form the
o32 FP64A ABI extension (-mabi=32 -mfp64 -mno-odd-spreg). */
#define TARGET_O32_FP64A_ABI (mips_abi == ABI_32 && TARGET_FLOAT64 \
&& !TARGET_ODD_SPREG)
/* False if SC acts as a memory barrier with respect to itself,
otherwise a SYNC will be emitted after SC for atomic operations
that require ordering between the SC and following loads and
stores. It does not tell anything about ordering of loads and
stores prior to and following the SC, only about the SC itself and
those loads and stores follow it. */
#define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
/* Define preprocessor macros for the -march and -mtune options.
PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
processor. If INFO's canonical name is "foo", define PREFIX to
be "foo", and define an additional macro PREFIX_FOO. */
#define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
do \
{ \
char *macro, *p; \
\
macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
for (p = macro; *p != 0; p++) \
if (*p == '+') \
*p = 'P'; \
else \
*p = TOUPPER (*p); \
\
builtin_define (macro); \
builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
free (macro); \
} \
while (0)
/* Target CPU builtins. */
#define TARGET_CPU_CPP_BUILTINS() \
do \
{ \
builtin_assert ("machine=mips"); \
builtin_assert ("cpu=mips"); \
builtin_define ("__mips__"); \
builtin_define ("_mips"); \
\
/* We do this here because __mips is defined below and so we \
can't use builtin_define_std. We don't ever want to define \
"mips" for VxWorks because some of the VxWorks headers \
construct include filenames from a root directory macro, \
an architecture macro and a filename, where the architecture \
macro expands to 'mips'. If we define 'mips' to 1, the \
architecture macro expands to 1 as well. */ \
if (!flag_iso && !TARGET_VXWORKS) \
builtin_define ("mips"); \
\
if (TARGET_64BIT) \
builtin_define ("__mips64"); \
\
/* Treat _R3000 and _R4000 like register-size \
defines, which is how they've historically \
been used. */ \
if (TARGET_64BIT) \
{ \
builtin_define_std ("R4000"); \
builtin_define ("_R4000"); \
} \
else \
{ \
builtin_define_std ("R3000"); \
builtin_define ("_R3000"); \
} \
\
if (TARGET_FLOAT64) \
builtin_define ("__mips_fpr=64"); \
else if (TARGET_FLOATXX) \
builtin_define ("__mips_fpr=0"); \
else \
builtin_define ("__mips_fpr=32"); \
\
if (mips_base_compression_flags & MASK_MIPS16) \
builtin_define ("__mips16"); \
\
if (TARGET_MIPS3D) \
builtin_define ("__mips3d"); \
\
if (TARGET_SMARTMIPS) \
builtin_define ("__mips_smartmips"); \
\
if (mips_base_compression_flags & MASK_MICROMIPS) \
builtin_define ("__mips_micromips"); \
\
if (TARGET_MCU) \
builtin_define ("__mips_mcu"); \
\
if (TARGET_EVA) \
builtin_define ("__mips_eva"); \
\
if (TARGET_DSP) \
{ \
builtin_define ("__mips_dsp"); \
if (TARGET_DSPR2) \
{ \
builtin_define ("__mips_dspr2"); \
builtin_define ("__mips_dsp_rev=2"); \
} \
else \
builtin_define ("__mips_dsp_rev=1"); \
} \
\
if (ISA_HAS_MSA) \
{ \
builtin_define ("__mips_msa"); \
builtin_define ("__mips_msa_width=128"); \
} \
\
MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
\
if (ISA_MIPS1) \
{ \
builtin_define ("__mips=1"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
} \
else if (ISA_MIPS2) \
{ \
builtin_define ("__mips=2"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
} \
else if (ISA_MIPS3) \
{ \
builtin_define ("__mips=3"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
} \
else if (ISA_MIPS4) \
{ \
builtin_define ("__mips=4"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
} \
else if (mips_isa >= 32 && mips_isa < 64) \
{ \
builtin_define ("__mips=32"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
} \
else if (mips_isa >= 64) \
{ \
builtin_define ("__mips=64"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
} \
if (mips_isa_rev > 0) \
builtin_define_with_int_value ("__mips_isa_rev", \
mips_isa_rev); \
\
switch (mips_abi) \
{ \
case ABI_32: \
builtin_define ("_ABIO32=1"); \
builtin_define ("_MIPS_SIM=_ABIO32"); \
break; \
\
case ABI_N32: \
builtin_define ("_ABIN32=2"); \
builtin_define ("_MIPS_SIM=_ABIN32"); \
break; \
\
case ABI_64: \
builtin_define ("_ABI64=3"); \
builtin_define ("_MIPS_SIM=_ABI64"); \
break; \
\
case ABI_O64: \
builtin_define ("_ABIO64=4"); \
builtin_define ("_MIPS_SIM=_ABIO64"); \
break; \
} \
\
builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
builtin_define_with_int_value ("_MIPS_FPSET", \
32 / MAX_FPRS_PER_FMT); \
builtin_define_with_int_value ("_MIPS_SPFPSET", \
TARGET_ODD_SPREG ? 32 : 16); \
\
/* These defines reflect the ABI in use, not whether the \
FPU is directly accessible. */ \
if (TARGET_NO_FLOAT) \
builtin_define ("__mips_no_float"); \
else if (TARGET_HARD_FLOAT_ABI) \
builtin_define ("__mips_hard_float"); \
else \
builtin_define ("__mips_soft_float"); \
\
if (TARGET_SINGLE_FLOAT) \
builtin_define ("__mips_single_float"); \
\
if (TARGET_PAIRED_SINGLE_FLOAT) \
builtin_define ("__mips_paired_single_float"); \
\
if (mips_abs == MIPS_IEEE_754_2008) \
builtin_define ("__mips_abs2008"); \
\
if (mips_nan == MIPS_IEEE_754_2008) \
builtin_define ("__mips_nan2008"); \
\
if (TARGET_BIG_ENDIAN) \
{ \
builtin_define_std ("MIPSEB"); \
builtin_define ("_MIPSEB"); \
} \
else \
{ \
builtin_define_std ("MIPSEL"); \
builtin_define ("_MIPSEL"); \
} \
\
/* Whether calls should go through $25. The separate __PIC__ \
macro indicates whether abicalls code might use a GOT. */ \
if (TARGET_ABICALLS) \
builtin_define ("__mips_abicalls"); \
\
/* Whether Loongson vector modes are enabled. */ \
if (TARGET_LOONGSON_VECTORS) \
builtin_define ("__mips_loongson_vector_rev"); \
\
/* Historical Octeon macro. */ \
if (TARGET_OCTEON) \
builtin_define ("__OCTEON__"); \
\
if (TARGET_SYNCI) \
builtin_define ("__mips_synci"); \
\
/* Macros dependent on the C dialect. */ \
if (preprocessing_asm_p ()) \
{ \
builtin_define_std ("LANGUAGE_ASSEMBLY"); \
builtin_define ("_LANGUAGE_ASSEMBLY"); \
} \
else if (c_dialect_cxx ()) \
{ \
builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
} \
else \
{ \
builtin_define_std ("LANGUAGE_C"); \
builtin_define ("_LANGUAGE_C"); \
} \
if (c_dialect_objc ()) \
{ \
builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
/* Bizarre, but retained for backwards compatibility. */ \
builtin_define_std ("LANGUAGE_C"); \
builtin_define ("_LANGUAGE_C"); \
} \
\
if (mips_abi == ABI_EABI) \
builtin_define ("__mips_eabi"); \
\
if (TARGET_CACHE_BUILTIN) \
builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
if (!ISA_HAS_LXC1_SXC1) \
builtin_define ("__mips_no_lxc1_sxc1"); \
if (!ISA_HAS_UNFUSED_MADD4 && !ISA_HAS_FUSED_MADD4) \
builtin_define ("__mips_no_madd4"); \
} \
while (0)
/* Default target_flags if no switches are specified */
#ifndef TARGET_DEFAULT
#define TARGET_DEFAULT 0
#endif
#ifndef TARGET_CPU_DEFAULT
#define TARGET_CPU_DEFAULT 0
#endif
#ifndef TARGET_ENDIAN_DEFAULT
#define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
#endif
#ifdef IN_LIBGCC2
#undef TARGET_64BIT
/* Make this compile time constant for libgcc2 */
#ifdef __mips64
#define TARGET_64BIT 1
#else
#define TARGET_64BIT 0
#endif
#endif /* IN_LIBGCC2 */
/* Force the call stack unwinders in unwind.inc not to be MIPS16 code
when compiled with hardware floating point. This is because MIPS16
code cannot save and restore the floating-point registers, which is
important if in a mixed MIPS16/non-MIPS16 environment. */
#ifdef IN_LIBGCC2
#if __mips_hard_float
#define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
#endif
#endif /* IN_LIBGCC2 */
#define TARGET_LIBGCC_SDATA_SECTION ".sdata"
#ifndef MULTILIB_ENDIAN_DEFAULT
#if TARGET_ENDIAN_DEFAULT == 0
#define MULTILIB_ENDIAN_DEFAULT "EL"
#else
#define MULTILIB_ENDIAN_DEFAULT "EB"
#endif
#endif
#ifndef MULTILIB_ISA_DEFAULT
#if MIPS_ISA_DEFAULT == 1
#define MULTILIB_ISA_DEFAULT "mips1"
#elif MIPS_ISA_DEFAULT == 2
#define MULTILIB_ISA_DEFAULT "mips2"
#elif MIPS_ISA_DEFAULT == 3
#define MULTILIB_ISA_DEFAULT "mips3"
#elif MIPS_ISA_DEFAULT == 4
#define MULTILIB_ISA_DEFAULT "mips4"
#elif MIPS_ISA_DEFAULT == 32
#define MULTILIB_ISA_DEFAULT "mips32"
#elif MIPS_ISA_DEFAULT == 33
#define MULTILIB_ISA_DEFAULT "mips32r2"
#elif MIPS_ISA_DEFAULT == 37
#define MULTILIB_ISA_DEFAULT "mips32r6"
#elif MIPS_ISA_DEFAULT == 64
#define MULTILIB_ISA_DEFAULT "mips64"
#elif MIPS_ISA_DEFAULT == 65
#define MULTILIB_ISA_DEFAULT "mips64r2"
#elif MIPS_ISA_DEFAULT == 69
#define MULTILIB_ISA_DEFAULT "mips64r6"
#else
#define MULTILIB_ISA_DEFAULT "mips1"
#endif
#endif
#ifndef MIPS_ABI_DEFAULT
#define MIPS_ABI_DEFAULT ABI_32
#endif
/* Use the most portable ABI flag for the ASM specs. */
#if MIPS_ABI_DEFAULT == ABI_32
#define MULTILIB_ABI_DEFAULT "mabi=32"
#elif MIPS_ABI_DEFAULT == ABI_O64
#define MULTILIB_ABI_DEFAULT "mabi=o64"
#elif MIPS_ABI_DEFAULT == ABI_N32
#define MULTILIB_ABI_DEFAULT "mabi=n32"
#elif MIPS_ABI_DEFAULT == ABI_64
#define MULTILIB_ABI_DEFAULT "mabi=64"
#elif MIPS_ABI_DEFAULT == ABI_EABI
#define MULTILIB_ABI_DEFAULT "mabi=eabi"
#endif
#ifndef MULTILIB_DEFAULTS
#define MULTILIB_DEFAULTS \
{ MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
#endif
/* We must pass -EL to the linker by default for little endian embedded
targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
linker will default to using big-endian output files. The OUTPUT_FORMAT
line must be in the linker script, otherwise -EB/-EL will not work. */
#ifndef ENDIAN_SPEC
#if TARGET_ENDIAN_DEFAULT == 0
#define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
#else
#define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
#endif
#endif
/* A spec condition that matches all non-mips16 -mips arguments. */
#define MIPS_ISA_LEVEL_OPTION_SPEC \
"mips1|mips2|mips3|mips4|mips32*|mips64*"
/* A spec condition that matches all non-mips16 architecture arguments. */
#define MIPS_ARCH_OPTION_SPEC \
MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
/* A spec that infers a -mips argument from an -march argument. */
#define MIPS_ISA_LEVEL_SPEC \
"%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
%{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
%{march=mips2|march=r6000:-mips2} \
%{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
%{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
|march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
%{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
%{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
|march=34k*|march=74k*|march=m14k*|march=1004k* \
|march=interaptiv: -mips32r2} \
%{march=mips32r3: -mips32r3} \
%{march=mips32r5|march=p5600|march=m5100|march=m5101: -mips32r5} \
%{march=mips32r6: -mips32r6} \
%{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
|march=xlr: -mips64} \
%{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \
%{march=mips64r3: -mips64r3} \
%{march=mips64r5: -mips64r5} \
%{march=mips64r6|march=i6400|march=i6500|march=p6600: -mips64r6}}"
/* A spec that injects the default multilib ISA if no architecture is
specified. */
#define MIPS_DEFAULT_ISA_LEVEL_SPEC \
"%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
%{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
/* A spec that infers a -mhard-float or -msoft-float setting from an
-march argument. Note that soft-float and hard-float code are not
link-compatible. */
#define MIPS_ARCH_FLOAT_SPEC \
"%{mhard-float|msoft-float|mno-float|march=mips*:; \
march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
|march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
|march=m14k*|march=m5101|march=octeon|march=xlr: -msoft-float; \
march=*: -mhard-float}"
/* A spec condition that matches 32-bit options. It only works if
MIPS_ISA_LEVEL_SPEC has been applied. */
#define MIPS_32BIT_OPTION_SPEC \
"mips1|mips2|mips32*|mgp32"
/* A spec condition that matches architectures should be targeted with
o32 FPXX for compatibility reasons. */
#define MIPS_FPXX_OPTION_SPEC \
"mips2|mips3|mips4|mips5|mips32|mips32r2|mips32r3|mips32r5| \
mips64|mips64r2|mips64r3|mips64r5"
/* Infer a -msynci setting from a -mips argument, on the assumption that
-msynci is desired where possible. */
#define MIPS_ISA_SYNCI_SPEC \
"%{msynci|mno-synci:;:%{mips32r2|mips32r3|mips32r5|mips32r6|mips64r2 \
|mips64r3|mips64r5|mips64r6:-msynci;:-mno-synci}}"
/* Infer a -mnan=2008 setting from a -mips argument. */
#define MIPS_ISA_NAN2008_SPEC \
"%{mnan*:;mips32r6|mips64r6:-mnan=2008;march=m51*: \
%{!msoft-float:-mnan=2008}}"
#if (MIPS_ABI_DEFAULT == ABI_O64 \
|| MIPS_ABI_DEFAULT == ABI_N32 \
|| MIPS_ABI_DEFAULT == ABI_64)
#define OPT_ARCH64 "mabi=32|mgp32:;"
#define OPT_ARCH32 "mabi=32|mgp32"
#else
#define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
#define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
#endif
/* Support for a compile-time default CPU, et cetera. The rules are:
--with-arch is ignored if -march is specified or a -mips is specified
(other than -mips16); likewise --with-arch-32 and --with-arch-64.
--with-tune is ignored if -mtune is specified; likewise
--with-tune-32 and --with-tune-64.
--with-abi is ignored if -mabi is specified.
--with-float is ignored if -mhard-float or -msoft-float are
specified.
--with-fpu is ignored if -msoft-float, -msingle-float or -mdouble-float are
specified.
--with-nan is ignored if -mnan is specified.
--with-fp-32 is ignored if -msoft-float, -msingle-float, -mmsa or -mfp are
specified.
--with-odd-spreg-32 is ignored if -msoft-float, -msingle-float, -modd-spreg
or -mno-odd-spreg are specified.
--with-divide is ignored if -mdivide-traps or -mdivide-breaks are
specified. */
#define OPTION_DEFAULT_SPECS \
{"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
{"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
{"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
{"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
{"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
{"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
{"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
{"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
{"fpu", "%{!msoft-float:%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}}" }, \
{"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \
{"fp_32", "%{" OPT_ARCH32 \
":%{!msoft-float:%{!msingle-float:%{!mfp*:%{!mmsa:-mfp%(VALUE)}}}}}" }, \
{"odd_spreg_32", "%{" OPT_ARCH32 ":%{!msoft-float:%{!msingle-float:" \
"%{!modd-spreg:%{!mno-odd-spreg:-m%(VALUE)}}}}}" }, \
{"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
{"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
{"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
{"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }, \
{"lxc1-sxc1", "%{!mlxc1-sxc1:%{!mno-lxc1-sxc1:-m%(VALUE)}}" }, \
{"madd4", "%{!mmadd4:%{!mno-madd4:-m%(VALUE)}}" } \
/* A spec that infers the:
-mnan=2008 setting from a -mips argument,
-mdsp setting from a -march argument. */
#define BASE_DRIVER_SELF_SPECS \
MIPS_ISA_NAN2008_SPEC, \
"%{!mno-dsp: \
%{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k* \
|march=interaptiv: -mdsp} \
%{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}"
#define DRIVER_SELF_SPECS \
MIPS_ISA_LEVEL_SPEC, \
BASE_DRIVER_SELF_SPECS
#define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
&& ISA_HAS_COND_TRAP)
#define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
/* True if the ABI can only work with 64-bit integer registers. We
generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
otherwise floating-point registers must also be 64-bit. */
#define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
/* Likewise for 32-bit regs. */
#define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
/* True if the file format uses 64-bit symbols. At present, this is
only true for n64, which uses 64-bit ELF. */
#define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
/* True if symbols are 64 bits wide. This is usually determined by
the ABI's file format, but it can be overridden by -msym32. Note that
overriding the size with -msym32 changes the ABI of relocatable objects,
although it doesn't change the ABI of a fully-linked object. */
#define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
&& Pmode == DImode \
&& !TARGET_SYM32)
/* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
#define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
|| ISA_MIPS4 \
|| ISA_MIPS64 \
|| ISA_MIPS64R2 \
|| ISA_MIPS64R3 \
|| ISA_MIPS64R5 \
|| ISA_MIPS64R6)
#define ISA_HAS_JR (mips_isa_rev <= 5)
#define ISA_HAS_DELAY_SLOTS 1
#define ISA_HAS_COMPACT_BRANCHES (mips_isa_rev >= 6)
/* ISA has branch likely instructions (e.g. mips2). */
/* Disable branchlikely for tx39 until compare rewrite. They haven't
been generated up to this point. */
#define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 && mips_isa_rev <= 5)
/* ISA has 32 single-precision registers. */
#define ISA_HAS_ODD_SPREG ((mips_isa_rev >= 1 \
&& !TARGET_LOONGSON_3A) \
|| TARGET_FLOAT64 \
|| TARGET_MIPS5900)
/* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
#define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
|| TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_MIPS5900 \
|| TARGET_MIPS7000 \
|| TARGET_MIPS9000 \
|| TARGET_MAD \
|| (mips_isa_rev >= 1 \
&& mips_isa_rev <= 5)) \
&& !TARGET_MIPS16)
/* ISA has a three-operand multiplication instruction. */
#define ISA_HAS_DMUL3 (TARGET_64BIT \
&& TARGET_OCTEON \
&& !TARGET_MIPS16)
/* ISA has HI and LO registers. */
#define ISA_HAS_HILO (mips_isa_rev <= 5)
/* ISA supports instructions DMULT and DMULTU. */
#define ISA_HAS_DMULT (TARGET_64BIT \
&& !TARGET_MIPS5900 \
&& mips_isa_rev <= 5)
/* ISA supports instructions MULT and MULTU. */
#define ISA_HAS_MULT (mips_isa_rev <= 5)
/* ISA supports instructions MUL, MULU, MUH, MUHU. */
#define ISA_HAS_R6MUL (mips_isa_rev >= 6)
/* ISA supports instructions DMUL, DMULU, DMUH, DMUHU. */
#define ISA_HAS_R6DMUL (TARGET_64BIT && mips_isa_rev >= 6)
/* For Loongson, it is preferable to use the Loongson-specific division and
modulo instructions instead of the regular (D)DIV(U) instruction,
because the former are faster and can also have the effect of reducing
code size. */
#define ISA_AVOID_DIV_HILO ((TARGET_LOONGSON_2EF \
|| TARGET_LOONGSON_3A) \
&& !TARGET_MIPS16)
/* ISA supports instructions DDIV and DDIVU. */
#define ISA_HAS_DDIV (TARGET_64BIT \
&& !TARGET_MIPS5900 \
&& !ISA_AVOID_DIV_HILO \
&& mips_isa_rev <= 5)
/* ISA supports instructions DIV and DIVU.
This is always true, but the macro is needed for ISA_HAS_<D>DIV
in mips.md. */
#define ISA_HAS_DIV (!ISA_AVOID_DIV_HILO \
&& mips_isa_rev <= 5)
/* ISA supports instructions DIV, DIVU, MOD and MODU. */
#define ISA_HAS_R6DIV (mips_isa_rev >= 6)
/* ISA supports instructions DDIV, DDIVU, DMOD and DMODU. */