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i386.md
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i386.md
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;; GCC machine description for IA-32 and x86-64.
;; Copyright (C) 1988-2018 Free Software Foundation, Inc.
;; Mostly by William Schelter.
;; x86_64 support added by Jan Hubicka
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>. */
;;
;; The original PO technology requires these to be ordered by speed,
;; so that assigner will pick the fastest.
;;
;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
;;
;; The special asm out single letter directives following a '%' are:
;; L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
;; C -- print opcode suffix for set/cmov insn.
;; c -- like C, but print reversed condition
;; F,f -- likewise, but for floating-point.
;; O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
;; otherwise nothing
;; R -- print the prefix for register names.
;; z -- print the opcode suffix for the size of the current operand.
;; Z -- likewise, with special suffixes for x87 instructions.
;; * -- print a star (in certain assembler syntax)
;; A -- print an absolute memory reference.
;; E -- print address with DImode register names if TARGET_64BIT.
;; w -- print the operand as if it's a "word" (HImode) even if it isn't.
;; s -- print a shift double count, followed by the assemblers argument
;; delimiter.
;; b -- print the QImode name of the register for the indicated operand.
;; %b0 would print %al if operands[0] is reg 0.
;; w -- likewise, print the HImode name of the register.
;; k -- likewise, print the SImode name of the register.
;; q -- likewise, print the DImode name of the register.
;; x -- likewise, print the V4SFmode name of the register.
;; t -- likewise, print the V8SFmode name of the register.
;; h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
;; y -- print "st(0)" instead of "st" as a register.
;; d -- print duplicated register operand for AVX instruction.
;; D -- print condition for SSE cmp instruction.
;; P -- if PIC, print an @PLT suffix.
;; p -- print raw symbol name.
;; X -- don't print any sort of PIC '@' suffix for a symbol.
;; & -- print some in-use local-dynamic symbol name.
;; H -- print a memory address offset by 8; used for sse high-parts
;; K -- print HLE lock prefix
;; Y -- print condition for XOP pcom* instruction.
;; + -- print a branch hint as 'cs' or 'ds' prefix
;; ; -- print a semicolon (after prefixes due to bug in older gas).
;; ~ -- print "i" if TARGET_AVX2, "f" otherwise.
;; ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
;; ! -- print MPX or NOTRACK prefix for jxx/call/ret instructions if required.
(define_c_enum "unspec" [
;; Relocation specifiers
UNSPEC_GOT
UNSPEC_GOTOFF
UNSPEC_GOTPCREL
UNSPEC_GOTTPOFF
UNSPEC_TPOFF
UNSPEC_NTPOFF
UNSPEC_DTPOFF
UNSPEC_GOTNTPOFF
UNSPEC_INDNTPOFF
UNSPEC_PLTOFF
UNSPEC_MACHOPIC_OFFSET
UNSPEC_PCREL
UNSPEC_SIZEOF
;; Prologue support
UNSPEC_STACK_ALLOC
UNSPEC_SET_GOT
UNSPEC_SET_RIP
UNSPEC_SET_GOT_OFFSET
UNSPEC_MEMORY_BLOCKAGE
UNSPEC_PROBE_STACK
;; TLS support
UNSPEC_TP
UNSPEC_TLS_GD
UNSPEC_TLS_LD_BASE
UNSPEC_TLSDESC
UNSPEC_TLS_IE_SUN
;; Other random patterns
UNSPEC_SCAS
UNSPEC_FNSTSW
UNSPEC_SAHF
UNSPEC_NOTRAP
UNSPEC_PARITY
UNSPEC_FSTCW
UNSPEC_FLDCW
UNSPEC_REP
UNSPEC_LD_MPIC ; load_macho_picbase
UNSPEC_TRUNC_NOOP
UNSPEC_DIV_ALREADY_SPLIT
UNSPEC_PAUSE
UNSPEC_LEA_ADDR
UNSPEC_XBEGIN_ABORT
UNSPEC_STOS
UNSPEC_PEEPSIB
UNSPEC_INSN_FALSE_DEP
UNSPEC_SBB
;; For SSE/MMX support:
UNSPEC_FIX_NOTRUNC
UNSPEC_MASKMOV
UNSPEC_MOVMSK
UNSPEC_RCP
UNSPEC_RSQRT
UNSPEC_PSADBW
;; Generic math support
UNSPEC_COPYSIGN
UNSPEC_IEEE_MIN ; not commutative
UNSPEC_IEEE_MAX ; not commutative
;; x87 Floating point
UNSPEC_SIN
UNSPEC_COS
UNSPEC_FPATAN
UNSPEC_FYL2X
UNSPEC_FYL2XP1
UNSPEC_FRNDINT
UNSPEC_FIST
UNSPEC_F2XM1
UNSPEC_TAN
UNSPEC_FXAM
;; x87 Rounding
UNSPEC_FRNDINT_FLOOR
UNSPEC_FRNDINT_CEIL
UNSPEC_FRNDINT_TRUNC
UNSPEC_FRNDINT_MASK_PM
UNSPEC_FIST_FLOOR
UNSPEC_FIST_CEIL
;; x87 Double output FP
UNSPEC_SINCOS_COS
UNSPEC_SINCOS_SIN
UNSPEC_XTRACT_FRACT
UNSPEC_XTRACT_EXP
UNSPEC_FSCALE_FRACT
UNSPEC_FSCALE_EXP
UNSPEC_FPREM_F
UNSPEC_FPREM_U
UNSPEC_FPREM1_F
UNSPEC_FPREM1_U
UNSPEC_C2_FLAG
UNSPEC_FXAM_MEM
;; SSP patterns
UNSPEC_SP_SET
UNSPEC_SP_TEST
;; For ROUND support
UNSPEC_ROUND
;; For CRC32 support
UNSPEC_CRC32
;; For LZCNT suppoprt
UNSPEC_LZCNT
;; For BMI support
UNSPEC_TZCNT
UNSPEC_BEXTR
;; For BMI2 support
UNSPEC_PDEP
UNSPEC_PEXT
UNSPEC_BNDMK
UNSPEC_BNDMK_ADDR
UNSPEC_BNDSTX
UNSPEC_BNDLDX
UNSPEC_BNDLDX_ADDR
UNSPEC_BNDCL
UNSPEC_BNDCU
UNSPEC_BNDCN
UNSPEC_MPX_FENCE
;; IRET support
UNSPEC_INTERRUPT_RETURN
])
(define_c_enum "unspecv" [
UNSPECV_UD2
UNSPECV_BLOCKAGE
UNSPECV_STACK_PROBE
UNSPECV_PROBE_STACK_RANGE
UNSPECV_ALIGN
UNSPECV_PROLOGUE_USE
UNSPECV_SPLIT_STACK_RETURN
UNSPECV_CLD
UNSPECV_NOPS
UNSPECV_RDTSC
UNSPECV_RDTSCP
UNSPECV_RDPMC
UNSPECV_LLWP_INTRINSIC
UNSPECV_SLWP_INTRINSIC
UNSPECV_LWPVAL_INTRINSIC
UNSPECV_LWPINS_INTRINSIC
UNSPECV_RDFSBASE
UNSPECV_RDGSBASE
UNSPECV_WRFSBASE
UNSPECV_WRGSBASE
UNSPECV_FXSAVE
UNSPECV_FXRSTOR
UNSPECV_FXSAVE64
UNSPECV_FXRSTOR64
UNSPECV_XSAVE
UNSPECV_XRSTOR
UNSPECV_XSAVE64
UNSPECV_XRSTOR64
UNSPECV_XSAVEOPT
UNSPECV_XSAVEOPT64
UNSPECV_XSAVES
UNSPECV_XRSTORS
UNSPECV_XSAVES64
UNSPECV_XRSTORS64
UNSPECV_XSAVEC
UNSPECV_XSAVEC64
UNSPECV_XGETBV
UNSPECV_XSETBV
;; For atomic compound assignments.
UNSPECV_FNSTENV
UNSPECV_FLDENV
UNSPECV_FNSTSW
UNSPECV_FNCLEX
;; For RDRAND support
UNSPECV_RDRAND
;; For RDSEED support
UNSPECV_RDSEED
;; For RTM support
UNSPECV_XBEGIN
UNSPECV_XEND
UNSPECV_XABORT
UNSPECV_XTEST
UNSPECV_NLGR
;; For CLWB support
UNSPECV_CLWB
;; For CLFLUSHOPT support
UNSPECV_CLFLUSHOPT
;; For MONITORX and MWAITX support
UNSPECV_MONITORX
UNSPECV_MWAITX
;; For CLZERO support
UNSPECV_CLZERO
;; For RDPKRU and WRPKRU support
UNSPECV_PKU
;; For RDPID support
UNSPECV_RDPID
;; For CET support
UNSPECV_NOP_ENDBR
UNSPECV_NOP_RDSSP
UNSPECV_INCSSP
UNSPECV_SAVEPREVSSP
UNSPECV_RSTORSSP
UNSPECV_WRSS
UNSPECV_WRUSS
UNSPECV_SETSSBSY
UNSPECV_CLRSSBSY
])
;; Constants to represent rounding modes in the ROUND instruction
(define_constants
[(ROUND_FLOOR 0x1)
(ROUND_CEIL 0x2)
(ROUND_TRUNC 0x3)
(ROUND_MXCSR 0x4)
(ROUND_NO_EXC 0x8)
])
;; Constants to represent AVX512F embeded rounding
(define_constants
[(ROUND_NEAREST_INT 0)
(ROUND_NEG_INF 1)
(ROUND_POS_INF 2)
(ROUND_ZERO 3)
(NO_ROUND 4)
(ROUND_SAE 8)
])
;; Constants to represent pcomtrue/pcomfalse variants
(define_constants
[(PCOM_FALSE 0)
(PCOM_TRUE 1)
(COM_FALSE_S 2)
(COM_FALSE_P 3)
(COM_TRUE_S 4)
(COM_TRUE_P 5)
])
;; Constants used in the XOP pperm instruction
(define_constants
[(PPERM_SRC 0x00) /* copy source */
(PPERM_INVERT 0x20) /* invert source */
(PPERM_REVERSE 0x40) /* bit reverse source */
(PPERM_REV_INV 0x60) /* bit reverse & invert src */
(PPERM_ZERO 0x80) /* all 0's */
(PPERM_ONES 0xa0) /* all 1's */
(PPERM_SIGN 0xc0) /* propagate sign bit */
(PPERM_INV_SIGN 0xe0) /* invert & propagate sign */
(PPERM_SRC1 0x00) /* use first source byte */
(PPERM_SRC2 0x10) /* use second source byte */
])
;; Registers by name.
(define_constants
[(AX_REG 0)
(DX_REG 1)
(CX_REG 2)
(BX_REG 3)
(SI_REG 4)
(DI_REG 5)
(BP_REG 6)
(SP_REG 7)
(ST0_REG 8)
(ST1_REG 9)
(ST2_REG 10)
(ST3_REG 11)
(ST4_REG 12)
(ST5_REG 13)
(ST6_REG 14)
(ST7_REG 15)
(ARGP_REG 16)
(FLAGS_REG 17)
(FPSR_REG 18)
(FPCR_REG 19)
(FRAME_REG 20)
(XMM0_REG 21)
(XMM1_REG 22)
(XMM2_REG 23)
(XMM3_REG 24)
(XMM4_REG 25)
(XMM5_REG 26)
(XMM6_REG 27)
(XMM7_REG 28)
(MM0_REG 29)
(MM1_REG 30)
(MM2_REG 31)
(MM3_REG 32)
(MM4_REG 33)
(MM5_REG 34)
(MM6_REG 35)
(MM7_REG 36)
(R8_REG 37)
(R9_REG 38)
(R10_REG 39)
(R11_REG 40)
(R12_REG 41)
(R13_REG 42)
(R14_REG 43)
(R15_REG 44)
(XMM8_REG 45)
(XMM9_REG 46)
(XMM10_REG 47)
(XMM11_REG 48)
(XMM12_REG 49)
(XMM13_REG 50)
(XMM14_REG 51)
(XMM15_REG 52)
(XMM16_REG 53)
(XMM17_REG 54)
(XMM18_REG 55)
(XMM19_REG 56)
(XMM20_REG 57)
(XMM21_REG 58)
(XMM22_REG 59)
(XMM23_REG 60)
(XMM24_REG 61)
(XMM25_REG 62)
(XMM26_REG 63)
(XMM27_REG 64)
(XMM28_REG 65)
(XMM29_REG 66)
(XMM30_REG 67)
(XMM31_REG 68)
(MASK0_REG 69)
(MASK1_REG 70)
(MASK2_REG 71)
(MASK3_REG 72)
(MASK4_REG 73)
(MASK5_REG 74)
(MASK6_REG 75)
(MASK7_REG 76)
(BND0_REG 77)
(BND1_REG 78)
(BND2_REG 79)
(BND3_REG 80)
(FIRST_PSEUDO_REG 81)
])
;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
;; from i386.c.
;; In C guard expressions, put expressions which may be compile-time
;; constants first. This allows for better optimization. For
;; example, write "TARGET_64BIT && reload_completed", not
;; "reload_completed && TARGET_64BIT".
;; Processor type.
(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,nehalem,
atom,slm,haswell,generic,amdfam10,bdver1,bdver2,bdver3,
bdver4,btver2,znver1"
(const (symbol_ref "ix86_schedule")))
;; A basic instruction type. Refinements due to arguments to be
;; provided in other attributes.
(define_attr "type"
"other,multi,
alu,alu1,negnot,imov,imovx,lea,
incdec,ishift,ishiftx,ishift1,rotate,rotatex,rotate1,
imul,imulx,idiv,icmp,test,ibr,setcc,icmov,
push,pop,call,callv,leave,
str,bitmanip,
fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,
fxch,fistp,fisttp,frndint,
sse,ssemov,sseadd,sseadd1,sseiadd,sseiadd1,
ssemul,sseimul,ssediv,sselog,sselog1,
sseishft,sseishft1,ssecmp,ssecomi,
ssecvt,ssecvt1,sseicvt,sseins,
sseshuf,sseshuf1,ssemuladd,sse4arg,
lwp,mskmov,msklog,
mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft,
mpxmov,mpxmk,mpxchk,mpxld,mpxst"
(const_string "other"))
;; Main data type used by the insn
(define_attr "mode"
"unknown,none,QI,HI,SI,DI,TI,OI,XI,SF,DF,XF,TF,V16SF,V8SF,V4DF,V4SF,
V2DF,V2SF,V1DF,V8DF"
(const_string "unknown"))
;; The CPU unit operations uses.
(define_attr "unit" "integer,i387,sse,mmx,unknown"
(cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,
fxch,fistp,fisttp,frndint")
(const_string "i387")
(eq_attr "type" "sse,ssemov,sseadd,sseadd1,sseiadd,sseiadd1,
ssemul,sseimul,ssediv,sselog,sselog1,
sseishft,sseishft1,ssecmp,ssecomi,
ssecvt,ssecvt1,sseicvt,sseins,
sseshuf,sseshuf1,ssemuladd,sse4arg,mskmov")
(const_string "sse")
(eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
(const_string "mmx")
(eq_attr "type" "other")
(const_string "unknown")]
(const_string "integer")))
;; The (bounding maximum) length of an instruction immediate.
(define_attr "length_immediate" ""
(cond [(eq_attr "type" "incdec,setcc,icmov,str,lea,other,multi,idiv,leave,
bitmanip,imulx,msklog,mskmov,mpxmk,mpxmov,mpxchk,
mpxld,mpxst")
(const_int 0)
(eq_attr "unit" "i387,sse,mmx")
(const_int 0)
(eq_attr "type" "alu,alu1,negnot,imovx,ishift,ishiftx,ishift1,
rotate,rotatex,rotate1,imul,icmp,push,pop")
(symbol_ref "ix86_attr_length_immediate_default (insn, true)")
(eq_attr "type" "imov,test")
(symbol_ref "ix86_attr_length_immediate_default (insn, false)")
(eq_attr "type" "call")
(if_then_else (match_operand 0 "constant_call_address_operand")
(const_int 4)
(const_int 0))
(eq_attr "type" "callv")
(if_then_else (match_operand 1 "constant_call_address_operand")
(const_int 4)
(const_int 0))
;; We don't know the size before shorten_branches. Expect
;; the instruction to fit for better scheduling.
(eq_attr "type" "ibr")
(const_int 1)
]
(symbol_ref "/* Update immediate_length and other attributes! */
gcc_unreachable (),1")))
;; The (bounding maximum) length of an instruction address.
(define_attr "length_address" ""
(cond [(eq_attr "type" "str,other,multi,fxch")
(const_int 0)
(and (eq_attr "type" "call")
(match_operand 0 "constant_call_address_operand"))
(const_int 0)
(and (eq_attr "type" "callv")
(match_operand 1 "constant_call_address_operand"))
(const_int 0)
]
(symbol_ref "ix86_attr_length_address_default (insn)")))
;; Set when length prefix is used.
(define_attr "prefix_data16" ""
(cond [(eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1")
(const_int 0)
(eq_attr "mode" "HI")
(const_int 1)
(and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF,TI"))
(const_int 1)
]
(const_int 0)))
;; Set when string REP prefix is used.
(define_attr "prefix_rep" ""
(cond [(eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1")
(const_int 0)
(and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
(const_int 1)
(and (eq_attr "type" "ibr,call,callv")
(match_test "ix86_bnd_prefixed_insn_p (insn)"))
(const_int 1)
]
(const_int 0)))
;; Set when 0f opcode prefix is used.
(define_attr "prefix_0f" ""
(if_then_else
(ior (eq_attr "type" "imovx,setcc,icmov,bitmanip,msklog,mskmov,
mpxmk,mpxmov,mpxchk,mpxld,mpxst")
(eq_attr "unit" "sse,mmx"))
(const_int 1)
(const_int 0)))
;; Set when REX opcode prefix is used.
(define_attr "prefix_rex" ""
(cond [(not (match_test "TARGET_64BIT"))
(const_int 0)
(and (eq_attr "mode" "DI")
(and (eq_attr "type" "!push,pop,call,callv,leave,ibr")
(eq_attr "unit" "!mmx")))
(const_int 1)
(and (eq_attr "mode" "QI")
(match_test "x86_extended_QIreg_mentioned_p (insn)"))
(const_int 1)
(match_test "x86_extended_reg_mentioned_p (insn)")
(const_int 1)
(and (eq_attr "type" "imovx")
(match_operand:QI 1 "ext_QIreg_operand"))
(const_int 1)
]
(const_int 0)))
;; There are also additional prefixes in 3DNOW, SSSE3.
;; ssemuladd,sse4arg default to 0f24/0f25 and DREX byte,
;; sseiadd1,ssecvt1 to 0f7a with no DREX byte.
;; 3DNOW has 0f0f prefix, SSSE3 and SSE4_{1,2} 0f38/0f3a.
(define_attr "prefix_extra" ""
(cond [(eq_attr "type" "ssemuladd,sse4arg")
(const_int 2)
(eq_attr "type" "sseiadd1,ssecvt1")
(const_int 1)
]
(const_int 0)))
;; Set when BND opcode prefix may be used.
(define_attr "maybe_prefix_bnd" "" (const_int 0))
;; Prefix used: original, VEX or maybe VEX.
(define_attr "prefix" "orig,vex,maybe_vex,evex,maybe_evex"
(cond [(eq_attr "mode" "OI,V8SF,V4DF")
(const_string "vex")
(eq_attr "mode" "XI,V16SF,V8DF")
(const_string "evex")
]
(const_string "orig")))
;; VEX W bit is used.
(define_attr "prefix_vex_w" "" (const_int 0))
;; The length of VEX prefix
;; Only instructions with 0f prefix can have 2 byte VEX prefix,
;; 0f38/0f3a prefixes can't. In i386.md 0f3[8a] is
;; still prefix_0f 1, with prefix_extra 1.
(define_attr "length_vex" ""
(if_then_else (and (eq_attr "prefix_0f" "1")
(eq_attr "prefix_extra" "0"))
(if_then_else (eq_attr "prefix_vex_w" "1")
(symbol_ref "ix86_attr_length_vex_default (insn, true, true)")
(symbol_ref "ix86_attr_length_vex_default (insn, true, false)"))
(if_then_else (eq_attr "prefix_vex_w" "1")
(symbol_ref "ix86_attr_length_vex_default (insn, false, true)")
(symbol_ref "ix86_attr_length_vex_default (insn, false, false)"))))
;; 4-bytes evex prefix and 1 byte opcode.
(define_attr "length_evex" "" (const_int 5))
;; Set when modrm byte is used.
(define_attr "modrm" ""
(cond [(eq_attr "type" "str,leave")
(const_int 0)
(eq_attr "unit" "i387")
(const_int 0)
(and (eq_attr "type" "incdec")
(and (not (match_test "TARGET_64BIT"))
(ior (match_operand:SI 1 "register_operand")
(match_operand:HI 1 "register_operand"))))
(const_int 0)
(and (eq_attr "type" "push")
(not (match_operand 1 "memory_operand")))
(const_int 0)
(and (eq_attr "type" "pop")
(not (match_operand 0 "memory_operand")))
(const_int 0)
(and (eq_attr "type" "imov")
(and (not (eq_attr "mode" "DI"))
(ior (and (match_operand 0 "register_operand")
(match_operand 1 "immediate_operand"))
(ior (and (match_operand 0 "ax_reg_operand")
(match_operand 1 "memory_displacement_only_operand"))
(and (match_operand 0 "memory_displacement_only_operand")
(match_operand 1 "ax_reg_operand"))))))
(const_int 0)
(and (eq_attr "type" "call")
(match_operand 0 "constant_call_address_operand"))
(const_int 0)
(and (eq_attr "type" "callv")
(match_operand 1 "constant_call_address_operand"))
(const_int 0)
(and (eq_attr "type" "alu,alu1,icmp,test")
(match_operand 0 "ax_reg_operand"))
(symbol_ref "(get_attr_length_immediate (insn) <= (get_attr_mode (insn) != MODE_QI))")
]
(const_int 1)))
(define_attr "modrm_class" "none,incdec,op0,op01,op02,pushpop,unknown"
(cond [(eq_attr "modrm" "0")
(const_string "none")
(eq_attr "type" "alu,imul,ishift")
(const_string "op02")
(eq_attr "type" "imov,imovx,lea,alu1,icmp")
(const_string "op01")
(eq_attr "type" "incdec")
(const_string "incdec")
(eq_attr "type" "push,pop")
(const_string "pushpop")]
(const_string "unknown")))
;; The (bounding maximum) length of an instruction in bytes.
;; ??? fistp and frndint are in fact fldcw/{fistp,frndint}/fldcw sequences.
;; Later we may want to split them and compute proper length as for
;; other insns.
(define_attr "length" ""
(cond [(eq_attr "type" "other,multi,fistp,frndint")
(const_int 16)
(eq_attr "type" "fcmp")
(const_int 4)
(eq_attr "unit" "i387")
(plus (const_int 2)
(plus (attr "prefix_data16")
(attr "length_address")))
(ior (eq_attr "prefix" "evex")
(and (ior (eq_attr "prefix" "maybe_evex")
(eq_attr "prefix" "maybe_vex"))
(match_test "TARGET_AVX512F")))
(plus (attr "length_evex")
(plus (attr "length_immediate")
(plus (attr "modrm")
(attr "length_address"))))
(ior (eq_attr "prefix" "vex")
(and (ior (eq_attr "prefix" "maybe_vex")
(eq_attr "prefix" "maybe_evex"))
(match_test "TARGET_AVX")))
(plus (attr "length_vex")
(plus (attr "length_immediate")
(plus (attr "modrm")
(attr "length_address"))))]
(plus (plus (attr "modrm")
(plus (attr "prefix_0f")
(plus (attr "prefix_rex")
(plus (attr "prefix_extra")
(const_int 1)))))
(plus (attr "prefix_rep")
(plus (attr "prefix_data16")
(plus (attr "length_immediate")
(attr "length_address")))))))
;; The `memory' attribute is `none' if no memory is referenced, `load' or
;; `store' if there is a simple memory reference therein, or `unknown'
;; if the instruction is complex.
(define_attr "memory" "none,load,store,both,unknown"
(cond [(eq_attr "type" "other,multi,str,lwp")
(const_string "unknown")
(eq_attr "type" "lea,fcmov,fpspc,mpxmk,mpxchk")
(const_string "none")
(eq_attr "type" "fistp,leave")
(const_string "both")
(eq_attr "type" "frndint")
(const_string "load")
(eq_attr "type" "mpxld")
(const_string "load")
(eq_attr "type" "mpxst")
(const_string "store")
(eq_attr "type" "push")
(if_then_else (match_operand 1 "memory_operand")
(const_string "both")
(const_string "store"))
(eq_attr "type" "pop")
(if_then_else (match_operand 0 "memory_operand")
(const_string "both")
(const_string "load"))
(eq_attr "type" "setcc")
(if_then_else (match_operand 0 "memory_operand")
(const_string "store")
(const_string "none"))
(eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp")
(if_then_else (ior (match_operand 0 "memory_operand")
(match_operand 1 "memory_operand"))
(const_string "load")
(const_string "none"))
(eq_attr "type" "ibr")
(if_then_else (match_operand 0 "memory_operand")
(const_string "load")
(const_string "none"))
(eq_attr "type" "call")
(if_then_else (match_operand 0 "constant_call_address_operand")
(const_string "none")
(const_string "load"))
(eq_attr "type" "callv")
(if_then_else (match_operand 1 "constant_call_address_operand")
(const_string "none")
(const_string "load"))
(and (eq_attr "type" "alu1,negnot,ishift1,sselog1,sseshuf1")
(match_operand 1 "memory_operand"))
(const_string "both")
(and (match_operand 0 "memory_operand")
(match_operand 1 "memory_operand"))
(const_string "both")
(match_operand 0 "memory_operand")
(const_string "store")
(match_operand 1 "memory_operand")
(const_string "load")
(and (eq_attr "type"
"!alu1,negnot,ishift1,
imov,imovx,icmp,test,bitmanip,
fmov,fcmp,fsgn,
sse,ssemov,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt,
sselog1,sseshuf1,sseadd1,sseiadd1,sseishft1,
mmx,mmxmov,mmxcmp,mmxcvt,mskmov,msklog,mpxmov")
(match_operand 2 "memory_operand"))
(const_string "load")
(and (eq_attr "type" "icmov,ssemuladd,sse4arg")
(match_operand 3 "memory_operand"))
(const_string "load")
]
(const_string "none")))
;; Indicates if an instruction has both an immediate and a displacement.
(define_attr "imm_disp" "false,true,unknown"
(cond [(eq_attr "type" "other,multi")
(const_string "unknown")
(and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1")
(and (match_operand 0 "memory_displacement_operand")
(match_operand 1 "immediate_operand")))
(const_string "true")
(and (eq_attr "type" "alu,ishift,ishiftx,rotate,rotatex,imul,idiv")
(and (match_operand 0 "memory_displacement_operand")
(match_operand 2 "immediate_operand")))
(const_string "true")
]
(const_string "false")))
;; Indicates if an FP operation has an integer source.
(define_attr "fp_int_src" "false,true"
(const_string "false"))
;; Defines rounding mode of an FP operation.
(define_attr "i387_cw" "trunc,floor,ceil,mask_pm,uninitialized,any"
(const_string "any"))
;; Define attribute to classify add/sub insns that consumes carry flag (CF)
(define_attr "use_carry" "0,1" (const_string "0"))
;; Define attribute to indicate unaligned ssemov insns
(define_attr "movu" "0,1" (const_string "0"))
;; Used to control the "enabled" attribute on a per-instruction basis.
(define_attr "isa" "base,x64,x64_sse4,x64_sse4_noavx,x64_avx,nox64,
sse2,sse2_noavx,sse3,sse4,sse4_noavx,avx,noavx,
avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f,
avx512bw,noavx512bw,avx512dq,noavx512dq,
avx512vl,noavx512vl,x64_avx512dq,x64_avx512bw"
(const_string "base"))
(define_attr "enabled" ""
(cond [(eq_attr "isa" "x64") (symbol_ref "TARGET_64BIT")
(eq_attr "isa" "x64_sse4")
(symbol_ref "TARGET_64BIT && TARGET_SSE4_1")
(eq_attr "isa" "x64_sse4_noavx")
(symbol_ref "TARGET_64BIT && TARGET_SSE4_1 && !TARGET_AVX")
(eq_attr "isa" "x64_avx")
(symbol_ref "TARGET_64BIT && TARGET_AVX")
(eq_attr "isa" "x64_avx512dq")
(symbol_ref "TARGET_64BIT && TARGET_AVX512DQ")
(eq_attr "isa" "x64_avx512bw")
(symbol_ref "TARGET_64BIT && TARGET_AVX512BW")
(eq_attr "isa" "nox64") (symbol_ref "!TARGET_64BIT")
(eq_attr "isa" "sse2") (symbol_ref "TARGET_SSE2")
(eq_attr "isa" "sse2_noavx")
(symbol_ref "TARGET_SSE2 && !TARGET_AVX")
(eq_attr "isa" "sse3") (symbol_ref "TARGET_SSE3")
(eq_attr "isa" "sse4") (symbol_ref "TARGET_SSE4_1")
(eq_attr "isa" "sse4_noavx")
(symbol_ref "TARGET_SSE4_1 && !TARGET_AVX")
(eq_attr "isa" "avx") (symbol_ref "TARGET_AVX")
(eq_attr "isa" "noavx") (symbol_ref "!TARGET_AVX")
(eq_attr "isa" "avx2") (symbol_ref "TARGET_AVX2")
(eq_attr "isa" "noavx2") (symbol_ref "!TARGET_AVX2")
(eq_attr "isa" "bmi") (symbol_ref "TARGET_BMI")
(eq_attr "isa" "bmi2") (symbol_ref "TARGET_BMI2")
(eq_attr "isa" "fma4") (symbol_ref "TARGET_FMA4")
(eq_attr "isa" "fma") (symbol_ref "TARGET_FMA")
(eq_attr "isa" "avx512f") (symbol_ref "TARGET_AVX512F")
(eq_attr "isa" "noavx512f") (symbol_ref "!TARGET_AVX512F")
(eq_attr "isa" "avx512bw") (symbol_ref "TARGET_AVX512BW")
(eq_attr "isa" "noavx512bw") (symbol_ref "!TARGET_AVX512BW")
(eq_attr "isa" "avx512dq") (symbol_ref "TARGET_AVX512DQ")
(eq_attr "isa" "noavx512dq") (symbol_ref "!TARGET_AVX512DQ")
(eq_attr "isa" "avx512vl") (symbol_ref "TARGET_AVX512VL")
(eq_attr "isa" "noavx512vl") (symbol_ref "!TARGET_AVX512VL")
]
(const_int 1)))
(define_attr "preferred_for_size" "" (const_int 1))
(define_attr "preferred_for_speed" "" (const_int 1))
;; Describe a user's asm statement.
(define_asm_attributes
[(set_attr "length" "128")
(set_attr "type" "multi")])
(define_code_iterator plusminus [plus minus])
(define_code_iterator sat_plusminus [ss_plus us_plus ss_minus us_minus])
(define_code_iterator multdiv [mult div])
;; Base name for define_insn
(define_code_attr plusminus_insn
[(plus "add") (ss_plus "ssadd") (us_plus "usadd")
(minus "sub") (ss_minus "sssub") (us_minus "ussub")])
;; Base name for insn mnemonic.
(define_code_attr plusminus_mnemonic
[(plus "add") (ss_plus "adds") (us_plus "addus")
(minus "sub") (ss_minus "subs") (us_minus "subus")])
(define_code_attr multdiv_mnemonic
[(mult "mul") (div "div")])
;; Mark commutative operators as such in constraints.
(define_code_attr comm [(plus "%") (ss_plus "%") (us_plus "%")
(minus "") (ss_minus "") (us_minus "")])
;; Mapping of max and min
(define_code_iterator maxmin [smax smin umax umin])
;; Mapping of signed max and min
(define_code_iterator smaxmin [smax smin])
;; Mapping of unsigned max and min
(define_code_iterator umaxmin [umax umin])
;; Base name for integer and FP insn mnemonic
(define_code_attr maxmin_int [(smax "maxs") (smin "mins")
(umax "maxu") (umin "minu")])
(define_code_attr maxmin_float [(smax "max") (smin "min")])
(define_int_iterator IEEE_MAXMIN
[UNSPEC_IEEE_MAX
UNSPEC_IEEE_MIN])
(define_int_attr ieee_maxmin
[(UNSPEC_IEEE_MAX "max")
(UNSPEC_IEEE_MIN "min")])
;; Mapping of logic operators
(define_code_iterator any_logic [and ior xor])
(define_code_iterator any_or [ior xor])
(define_code_iterator fpint_logic [and xor])
;; Base name for insn mnemonic.
(define_code_attr logic [(and "and") (ior "or") (xor "xor")])
;; Mapping of logic-shift operators
(define_code_iterator any_lshift [ashift lshiftrt])
;; Mapping of shift-right operators
(define_code_iterator any_shiftrt [lshiftrt ashiftrt])
;; Mapping of all shift operators
(define_code_iterator any_shift [ashift lshiftrt ashiftrt])
;; Base name for define_insn
(define_code_attr shift_insn
[(ashift "ashl") (lshiftrt "lshr") (ashiftrt "ashr")])
;; Base name for insn mnemonic.
(define_code_attr shift [(ashift "sll") (lshiftrt "shr") (ashiftrt "sar")])
(define_code_attr vshift [(ashift "sll") (lshiftrt "srl") (ashiftrt "sra")])
;; Mapping of rotate operators
(define_code_iterator any_rotate [rotate rotatert])
;; Base name for define_insn
(define_code_attr rotate_insn [(rotate "rotl") (rotatert "rotr")])
;; Base name for insn mnemonic.
(define_code_attr rotate [(rotate "rol") (rotatert "ror")])
;; Mapping of abs neg operators
(define_code_iterator absneg [abs neg])
;; Base name for x87 insn mnemonic.
(define_code_attr absneg_mnemonic [(abs "abs") (neg "chs")])
;; Used in signed and unsigned widening multiplications.
(define_code_iterator any_extend [sign_extend zero_extend])
;; Prefix for insn menmonic.
(define_code_attr sgnprefix [(sign_extend "i") (zero_extend "")])
;; Prefix for define_insn
(define_code_attr u [(sign_extend "") (zero_extend "u")])
(define_code_attr s [(sign_extend "s") (zero_extend "u")])
(define_code_attr u_bool [(sign_extend "false") (zero_extend "true")])
;; Used in signed and unsigned truncations.
(define_code_iterator any_truncate [ss_truncate truncate us_truncate])
;; Instruction suffix for truncations.
(define_code_attr trunsuffix [(ss_truncate "s") (truncate "") (us_truncate "us")])
;; Used in signed and unsigned fix.
(define_code_iterator any_fix [fix unsigned_fix])
(define_code_attr fixsuffix [(fix "") (unsigned_fix "u")])
;; Used in signed and unsigned float.
(define_code_iterator any_float [float unsigned_float])
(define_code_attr floatsuffix [(float "") (unsigned_float "u")])
;; All integer modes.
(define_mode_iterator SWI1248x [QI HI SI DI])
;; All integer modes without QImode.
(define_mode_iterator SWI248x [HI SI DI])
;; All integer modes without QImode and HImode.
(define_mode_iterator SWI48x [SI DI])
;; All integer modes without SImode and DImode.
(define_mode_iterator SWI12 [QI HI])
;; All integer modes without DImode.
(define_mode_iterator SWI124 [QI HI SI])
;; All integer modes without QImode and DImode.
(define_mode_iterator SWI24 [HI SI])
;; Single word integer modes.
(define_mode_iterator SWI [QI HI SI (DI "TARGET_64BIT")])
;; Single word integer modes without QImode.
(define_mode_iterator SWI248 [HI SI (DI "TARGET_64BIT")])
;; Single word integer modes without QImode and HImode.
(define_mode_iterator SWI48 [SI (DI "TARGET_64BIT")])
;; All math-dependant single and double word integer modes.