mirrored from git://gcc.gnu.org/git/gcc.git
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i386-common.cc
2523 lines (2339 loc) · 83.1 KB
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i386-common.cc
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/* IA-32 common hooks.
Copyright (C) 1988-2024 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "diagnostic-core.h"
#include "tm.h"
#include "memmodel.h"
#include "tm_p.h"
#include "common/common-target.h"
#include "common/common-target-def.h"
#include "opts.h"
#include "flags.h"
/* Define a set of ISAs which are available when a given ISA is
enabled. MMX and SSE ISAs are handled separately. */
#define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
#define OPTION_MASK_ISA_3DNOW_SET \
(OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
#define OPTION_MASK_ISA_3DNOW_A_SET \
(OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET)
#define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
#define OPTION_MASK_ISA_SSE2_SET \
(OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
#define OPTION_MASK_ISA_SSE3_SET \
(OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
#define OPTION_MASK_ISA_SSSE3_SET \
(OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
#define OPTION_MASK_ISA_SSE4_1_SET \
(OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
#define OPTION_MASK_ISA_SSE4_2_SET \
(OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
#define OPTION_MASK_ISA_AVX_SET \
(OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \
| OPTION_MASK_ISA_XSAVE_SET)
#define OPTION_MASK_ISA_FMA_SET \
(OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
#define OPTION_MASK_ISA_AVX2_SET \
(OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
#define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR
#define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE
#define OPTION_MASK_ISA_XSAVEOPT_SET \
(OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE_SET)
#define OPTION_MASK_ISA_AVX512F_SET \
(OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET)
#define OPTION_MASK_ISA_AVX512CD_SET \
(OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET)
#define OPTION_MASK_ISA_AVX512PF_SET \
(OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET)
#define OPTION_MASK_ISA_AVX512ER_SET \
(OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET)
#define OPTION_MASK_ISA_AVX512DQ_SET \
(OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
#define OPTION_MASK_ISA_AVX512BW_SET \
(OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET)
#define OPTION_MASK_ISA_AVX512VL_SET \
(OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET)
#define OPTION_MASK_ISA_AVX512IFMA_SET \
(OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET)
#define OPTION_MASK_ISA2_AVXIFMA_SET OPTION_MASK_ISA2_AVXIFMA
#define OPTION_MASK_ISA_AVX512VBMI_SET \
(OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
#define OPTION_MASK_ISA2_AVX5124FMAPS_SET OPTION_MASK_ISA2_AVX5124FMAPS
#define OPTION_MASK_ISA2_AVX5124VNNIW_SET OPTION_MASK_ISA2_AVX5124VNNIW
#define OPTION_MASK_ISA_AVX512VBMI2_SET \
(OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW_SET)
#define OPTION_MASK_ISA_AVX512FP16_SET OPTION_MASK_ISA_AVX512BW_SET
#define OPTION_MASK_ISA2_AVX512FP16_SET OPTION_MASK_ISA2_AVX512FP16
#define OPTION_MASK_ISA_AVX512VNNI_SET \
(OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET)
#define OPTION_MASK_ISA2_AVXVNNI_SET OPTION_MASK_ISA2_AVXVNNI
#define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
(OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET)
#define OPTION_MASK_ISA_AVX512BITALG_SET \
(OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512BW_SET)
#define OPTION_MASK_ISA2_AVX512BF16_SET OPTION_MASK_ISA2_AVX512BF16
#define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
#define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
#define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
#define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX
#define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1
#define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT
#define OPTION_MASK_ISA_XSAVES_SET \
(OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET)
#define OPTION_MASK_ISA_XSAVEC_SET \
(OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET)
#define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
#define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET OPTION_MASK_ISA2_AVX512VP2INTERSECT
#define OPTION_MASK_ISA2_AMX_TILE_SET OPTION_MASK_ISA2_AMX_TILE
#define OPTION_MASK_ISA2_AMX_INT8_SET \
(OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_INT8)
#define OPTION_MASK_ISA2_AMX_BF16_SET \
(OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_BF16)
#define OPTION_MASK_ISA2_AVXVNNIINT8_SET OPTION_MASK_ISA2_AVXVNNIINT8
#define OPTION_MASK_ISA2_AVXNECONVERT_SET OPTION_MASK_ISA2_AVXNECONVERT
#define OPTION_MASK_ISA2_CMPCCXADD_SET OPTION_MASK_ISA2_CMPCCXADD
#define OPTION_MASK_ISA2_AMX_FP16_SET \
(OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_FP16)
#define OPTION_MASK_ISA2_PREFETCHI_SET OPTION_MASK_ISA2_PREFETCHI
#define OPTION_MASK_ISA2_RAOINT_SET OPTION_MASK_ISA2_RAOINT
#define OPTION_MASK_ISA2_AMX_COMPLEX_SET \
(OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_COMPLEX)
#define OPTION_MASK_ISA2_AVXVNNIINT16_SET OPTION_MASK_ISA2_AVXVNNIINT16
#define OPTION_MASK_ISA2_SM3_SET OPTION_MASK_ISA2_SM3
#define OPTION_MASK_ISA2_SHA512_SET OPTION_MASK_ISA2_SHA512
#define OPTION_MASK_ISA2_SM4_SET OPTION_MASK_ISA2_SM4
#define OPTION_MASK_ISA2_APX_F_SET OPTION_MASK_ISA2_APX_F
#define OPTION_MASK_ISA2_EVEX512_SET OPTION_MASK_ISA2_EVEX512
#define OPTION_MASK_ISA2_USER_MSR_SET OPTION_MASK_ISA2_USER_MSR
#define OPTION_MASK_ISA2_AVX10_1_256_SET OPTION_MASK_ISA2_AVX10_1_256
#define OPTION_MASK_ISA2_AVX10_1_512_SET \
(OPTION_MASK_ISA2_AVX10_1_256_SET | OPTION_MASK_ISA2_AVX10_1_512)
/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
as -msse4.2. */
#define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
#define OPTION_MASK_ISA_SSE4A_SET \
(OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
#define OPTION_MASK_ISA_FMA4_SET \
(OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
| OPTION_MASK_ISA_AVX_SET)
#define OPTION_MASK_ISA_XOP_SET \
(OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
#define OPTION_MASK_ISA_LWP_SET \
OPTION_MASK_ISA_LWP
/* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */
#define OPTION_MASK_ISA_AES_SET \
(OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
#define OPTION_MASK_ISA_SHA_SET \
(OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET)
#define OPTION_MASK_ISA_PCLMUL_SET \
(OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
#define OPTION_MASK_ISA_ABM_SET \
(OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT_SET)
#define OPTION_MASK_ISA2_PCONFIG_SET OPTION_MASK_ISA2_PCONFIG
#define OPTION_MASK_ISA2_WBNOINVD_SET OPTION_MASK_ISA2_WBNOINVD
#define OPTION_MASK_ISA2_SGX_SET OPTION_MASK_ISA2_SGX
#define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
#define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
#define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT
#define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
#define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
#define OPTION_MASK_ISA2_CX16_SET OPTION_MASK_ISA2_CX16
#define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
#define OPTION_MASK_ISA2_MOVBE_SET OPTION_MASK_ISA2_MOVBE
#define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
#define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
#define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
#define OPTION_MASK_ISA2_PTWRITE_SET OPTION_MASK_ISA2_PTWRITE
#define OPTION_MASK_ISA_F16C_SET \
(OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
#define OPTION_MASK_ISA2_MWAITX_SET OPTION_MASK_ISA2_MWAITX
#define OPTION_MASK_ISA2_MWAIT_SET OPTION_MASK_ISA2_MWAIT
#define OPTION_MASK_ISA2_CLZERO_SET OPTION_MASK_ISA2_CLZERO
#define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU
#define OPTION_MASK_ISA2_RDPID_SET OPTION_MASK_ISA2_RDPID
#define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI
#define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK
#define OPTION_MASK_ISA2_VAES_SET OPTION_MASK_ISA2_VAES
#define OPTION_MASK_ISA_VPCLMULQDQ_SET \
(OPTION_MASK_ISA_VPCLMULQDQ | OPTION_MASK_ISA_PCLMUL_SET \
| OPTION_MASK_ISA_AVX_SET)
#define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI
#define OPTION_MASK_ISA2_MOVDIR64B_SET OPTION_MASK_ISA2_MOVDIR64B
#define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG
#define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE
#define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD
#define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE
#define OPTION_MASK_ISA2_TSXLDTRK_SET OPTION_MASK_ISA2_TSXLDTRK
#define OPTION_MASK_ISA2_UINTR_SET OPTION_MASK_ISA2_UINTR
#define OPTION_MASK_ISA2_HRESET_SET OPTION_MASK_ISA2_HRESET
#define OPTION_MASK_ISA2_KL_SET OPTION_MASK_ISA2_KL
#define OPTION_MASK_ISA2_WIDEKL_SET \
(OPTION_MASK_ISA2_WIDEKL | OPTION_MASK_ISA2_KL_SET)
/* Define a set of ISAs which aren't available when a given ISA is
disabled. MMX and SSE ISAs are handled separately. */
#define OPTION_MASK_ISA_MMX_UNSET \
(OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
#define OPTION_MASK_ISA_3DNOW_UNSET \
(OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
#define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
#define OPTION_MASK_ISA_SSE_UNSET \
(OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
#define OPTION_MASK_ISA_SSE2_UNSET \
(OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
#define OPTION_MASK_ISA_SSE3_UNSET \
(OPTION_MASK_ISA_SSE3 \
| OPTION_MASK_ISA_SSSE3_UNSET \
| OPTION_MASK_ISA_SSE4A_UNSET )
#define OPTION_MASK_ISA_SSSE3_UNSET \
(OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
#define OPTION_MASK_ISA_SSE4_1_UNSET \
(OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
#define OPTION_MASK_ISA_SSE4_2_UNSET \
(OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
#define OPTION_MASK_ISA_AVX_UNSET \
(OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
| OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
| OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_VPCLMULQDQ_UNSET)
#define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
#define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR
#define OPTION_MASK_ISA_XSAVE_UNSET \
(OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \
| OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET \
| OPTION_MASK_ISA_AVX_UNSET)
#define OPTION_MASK_ISA2_XSAVE_UNSET \
(OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_AMX_TILE_UNSET)
#define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT
#define OPTION_MASK_ISA_AVX2_UNSET \
(OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
#define OPTION_MASK_ISA2_AVX2_UNSET \
(OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \
| OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVXNECONVERT_UNSET \
| OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET \
| OPTION_MASK_ISA2_AVX10_1_256_UNSET)
#define OPTION_MASK_ISA_AVX512F_UNSET \
(OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
| OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \
| OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
| OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512IFMA_UNSET \
| OPTION_MASK_ISA_AVX512VNNI_UNSET \
| OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET)
#define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
#define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF
#define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER
#define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
#define OPTION_MASK_ISA_AVX512BW_UNSET \
(OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET \
| OPTION_MASK_ISA_AVX512VBMI2_UNSET | OPTION_MASK_ISA_AVX512BITALG_UNSET)
#define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
#define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA
#define OPTION_MASK_ISA2_AVXIFMA_UNSET OPTION_MASK_ISA2_AVXIFMA
#define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
#define OPTION_MASK_ISA2_AVX5124FMAPS_UNSET OPTION_MASK_ISA2_AVX5124FMAPS
#define OPTION_MASK_ISA2_AVX5124VNNIW_UNSET OPTION_MASK_ISA2_AVX5124VNNIW
#define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2
#define OPTION_MASK_ISA_AVX512FP16_UNSET OPTION_MASK_ISA_AVX512BW_UNSET
#define OPTION_MASK_ISA2_AVX512FP16_UNSET OPTION_MASK_ISA2_AVX512FP16
#define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI
#define OPTION_MASK_ISA2_AVXVNNI_UNSET OPTION_MASK_ISA2_AVXVNNI
#define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ
#define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG
#define OPTION_MASK_ISA2_AVX512BF16_UNSET OPTION_MASK_ISA2_AVX512BF16
#define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
#define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
#define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
#define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX
#define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1
#define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
#define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
#define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
#define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
#define OPTION_MASK_ISA2_MWAITX_UNSET OPTION_MASK_ISA2_MWAITX
#define OPTION_MASK_ISA2_MWAIT_UNSET OPTION_MASK_ISA2_MWAIT
#define OPTION_MASK_ISA2_CLZERO_UNSET OPTION_MASK_ISA2_CLZERO
#define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU
#define OPTION_MASK_ISA2_RDPID_UNSET OPTION_MASK_ISA2_RDPID
#define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI
#define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK
#define OPTION_MASK_ISA2_VAES_UNSET OPTION_MASK_ISA2_VAES
#define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ
#define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI
#define OPTION_MASK_ISA2_MOVDIR64B_UNSET OPTION_MASK_ISA2_MOVDIR64B
#define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG
#define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE
#define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD
#define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE
#define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT
#define OPTION_MASK_ISA2_TSXLDTRK_UNSET OPTION_MASK_ISA2_TSXLDTRK
#define OPTION_MASK_ISA2_AMX_TILE_UNSET \
(OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_INT8_UNSET \
| OPTION_MASK_ISA2_AMX_BF16_UNSET | OPTION_MASK_ISA2_AMX_FP16_UNSET \
| OPTION_MASK_ISA2_AMX_COMPLEX_UNSET)
#define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8
#define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16
#define OPTION_MASK_ISA2_UINTR_UNSET OPTION_MASK_ISA2_UINTR
#define OPTION_MASK_ISA2_HRESET_UNSET OPTION_MASK_ISA2_HRESET
#define OPTION_MASK_ISA2_KL_UNSET \
(OPTION_MASK_ISA2_KL | OPTION_MASK_ISA2_WIDEKL_UNSET)
#define OPTION_MASK_ISA2_WIDEKL_UNSET OPTION_MASK_ISA2_WIDEKL
#define OPTION_MASK_ISA2_AVXVNNIINT8_UNSET OPTION_MASK_ISA2_AVXVNNIINT8
#define OPTION_MASK_ISA2_AVXNECONVERT_UNSET OPTION_MASK_ISA2_AVXNECONVERT
#define OPTION_MASK_ISA2_CMPCCXADD_UNSET OPTION_MASK_ISA2_CMPCCXADD
#define OPTION_MASK_ISA2_AMX_FP16_UNSET OPTION_MASK_ISA2_AMX_FP16
#define OPTION_MASK_ISA2_PREFETCHI_UNSET OPTION_MASK_ISA2_PREFETCHI
#define OPTION_MASK_ISA2_RAOINT_UNSET OPTION_MASK_ISA2_RAOINT
#define OPTION_MASK_ISA2_AMX_COMPLEX_UNSET OPTION_MASK_ISA2_AMX_COMPLEX
#define OPTION_MASK_ISA2_AVXVNNIINT16_UNSET OPTION_MASK_ISA2_AVXVNNIINT16
#define OPTION_MASK_ISA2_SM3_UNSET OPTION_MASK_ISA2_SM3
#define OPTION_MASK_ISA2_SHA512_UNSET OPTION_MASK_ISA2_SHA512
#define OPTION_MASK_ISA2_SM4_UNSET OPTION_MASK_ISA2_SM4
#define OPTION_MASK_ISA2_APX_F_UNSET OPTION_MASK_ISA2_APX_F
#define OPTION_MASK_ISA2_EVEX512_UNSET OPTION_MASK_ISA2_EVEX512
#define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR
#define OPTION_MASK_ISA2_AVX10_1_256_UNSET \
(OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512_UNSET)
#define OPTION_MASK_ISA2_AVX10_1_512_UNSET OPTION_MASK_ISA2_AVX10_1_512
/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
as -mno-sse4.1. */
#define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
#define OPTION_MASK_ISA_SSE4A_UNSET \
(OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
#define OPTION_MASK_ISA_FMA4_UNSET \
(OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
#define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
#define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
#define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
#define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
#define OPTION_MASK_ISA_PCLMUL_UNSET \
(OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_VPCLMULQDQ_UNSET)
#define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
#define OPTION_MASK_ISA2_PCONFIG_UNSET OPTION_MASK_ISA2_PCONFIG
#define OPTION_MASK_ISA2_WBNOINVD_UNSET OPTION_MASK_ISA2_WBNOINVD
#define OPTION_MASK_ISA2_SGX_UNSET OPTION_MASK_ISA2_SGX
#define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
#define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
#define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT
#define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
#define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
#define OPTION_MASK_ISA2_CX16_UNSET OPTION_MASK_ISA2_CX16
#define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
#define OPTION_MASK_ISA2_MOVBE_UNSET OPTION_MASK_ISA2_MOVBE
#define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
#define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
#define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
#define OPTION_MASK_ISA2_PTWRITE_UNSET OPTION_MASK_ISA2_PTWRITE
#define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
#define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \
(OPTION_MASK_ISA_MMX_UNSET \
| OPTION_MASK_ISA_SSE_UNSET)
#define OPTION_MASK_ISA2_AVX512F_UNSET \
(OPTION_MASK_ISA2_AVX512BW_UNSET \
| OPTION_MASK_ISA2_AVX5124FMAPS_UNSET \
| OPTION_MASK_ISA2_AVX5124VNNIW_UNSET \
| OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET)
#define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
OPTION_MASK_ISA2_SSE_UNSET
#define OPTION_MASK_ISA2_AVX_UNSET \
(OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_VAES_UNSET \
| OPTION_MASK_ISA2_SM3_UNSET | OPTION_MASK_ISA2_SHA512_UNSET \
| OPTION_MASK_ISA2_SM4_UNSET)
#define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET
#define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET
#define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
#define OPTION_MASK_ISA2_SSSE3_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
#define OPTION_MASK_ISA2_SSE3_UNSET OPTION_MASK_ISA2_SSSE3_UNSET
#define OPTION_MASK_ISA2_SSE2_UNSET \
(OPTION_MASK_ISA2_SSE3_UNSET | OPTION_MASK_ISA2_KL_UNSET)
#define OPTION_MASK_ISA2_SSE_UNSET OPTION_MASK_ISA2_SSE2_UNSET
#define OPTION_MASK_ISA2_AVX512BW_UNSET \
(OPTION_MASK_ISA2_AVX512BF16_UNSET \
| OPTION_MASK_ISA2_AVX512FP16_UNSET)
/* Set 1 << value as value of -malign-FLAG option. */
static void
set_malign_value (const char **flag, unsigned value)
{
char *r = XNEWVEC (char, 6);
sprintf (r, "%d", 1 << value);
*flag = r;
}
/* Implement TARGET_HANDLE_OPTION. */
bool
ix86_handle_option (struct gcc_options *opts,
struct gcc_options *opts_set ATTRIBUTE_UNUSED,
const struct cl_decoded_option *decoded,
location_t loc)
{
size_t code = decoded->opt_index;
int value = decoded->value;
switch (code)
{
case OPT_mgeneral_regs_only:
if (value)
{
HOST_WIDE_INT general_regs_only_flags = 0;
HOST_WIDE_INT general_regs_only_flags2 = 0;
/* NB: Enable the GPR only instructions which are enabled
implicitly by SSE ISAs unless they have been disabled
explicitly. */
if (TARGET_SSE4_2_P (opts->x_ix86_isa_flags))
{
if (!TARGET_EXPLICIT_CRC32_P (opts))
general_regs_only_flags |= OPTION_MASK_ISA_CRC32;
if (!TARGET_EXPLICIT_POPCNT_P (opts))
general_regs_only_flags |= OPTION_MASK_ISA_POPCNT;
}
if (TARGET_SSE3_P (opts->x_ix86_isa_flags))
{
if (!TARGET_EXPLICIT_MWAIT_P (opts))
general_regs_only_flags2 |= OPTION_MASK_ISA2_MWAIT;
}
/* Disable MMX, SSE and x87 instructions if only
general registers are allowed. */
opts->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
opts->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
opts->x_ix86_isa_flags |= general_regs_only_flags;
opts->x_ix86_isa_flags2 |= general_regs_only_flags2;
opts->x_ix86_isa_flags_explicit
|= (OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET
| general_regs_only_flags);
opts->x_ix86_isa_flags2_explicit
|= (OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET
| general_regs_only_flags2);
opts->x_target_flags &= ~MASK_80387;
}
else
gcc_unreachable ();
return true;
case OPT_mmmx:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
}
return true;
case OPT_m3dnow:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
}
return true;
case OPT_m3dnowa:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_A_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_UNSET;
}
return true;
case OPT_msse:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE_UNSET;
}
return true;
case OPT_msse2:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE2_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE2_UNSET;
}
return true;
case OPT_msse3:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE3_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE3_UNSET;
}
return true;
case OPT_mssse3:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSSE3_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSSE3_UNSET;
}
return true;
case OPT_msse4_1:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_1_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_1_UNSET;
}
return true;
case OPT_msse4_2:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_2_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_2_UNSET;
}
return true;
case OPT_mavx:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX_UNSET;
}
return true;
case OPT_mavx2:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET;
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX2_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX2_UNSET;
}
return true;
case OPT_mavx512f:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET;
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
opts->x_ix86_no_avx512_explicit = 1;
}
return true;
case OPT_mavx512cd:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET;
opts->x_ix86_no_avx512_explicit = 1;
}
return true;
case OPT_mavx512pf:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512PF_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512PF_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_UNSET;
}
return true;
case OPT_mavx512er:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512ER_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512ER_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_UNSET;
}
return true;
case OPT_mrdpid:
if (value)
{
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RDPID_SET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_SET;
}
else
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_RDPID_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_UNSET;
}
return true;
case OPT_mgfni:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_GFNI_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_UNSET;
}
return true;
case OPT_mshstk:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHSTK_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHSTK_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_UNSET;
}
return true;
case OPT_mvaes:
if (value)
{
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_VAES_SET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_SET;
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
}
else
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_VAES_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_UNSET;
}
return true;
case OPT_mvpclmulqdq:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
}
return true;
case OPT_mmovdiri:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVDIRI_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MOVDIRI_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_UNSET;
}
return true;
case OPT_mmovdir64b:
if (value)
{
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVDIR64B_SET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_SET;
}
else
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVDIR64B_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_UNSET;
}
return true;
case OPT_mcldemote:
if (value)
{
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLDEMOTE_SET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_SET;
}
else
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLDEMOTE_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_UNSET;
}
return true;
case OPT_mwaitpkg:
if (value)
{
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WAITPKG_SET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_SET;
}
else
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WAITPKG_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_UNSET;
}
return true;
case OPT_menqcmd:
if (value)
{
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_ENQCMD_SET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_SET;
}
else
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_ENQCMD_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_UNSET;
}
return true;
case OPT_mkl:
if (value)
{
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_KL_SET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_KL_SET;
/* The Keylocker instructions need XMM registers from SSE2. */
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
}
else
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_KL_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_KL_UNSET;
}
return true;
case OPT_mwidekl:
if (value)
{
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WIDEKL_SET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WIDEKL_SET;
/* The Widekl instructions need XMM registers from SSE2. */
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
}
else
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WIDEKL_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WIDEKL_UNSET;
}
return true;
case OPT_mserialize:
if (value)
{
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SERIALIZE_SET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_SET;
}
else
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SERIALIZE_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_UNSET;
}
return true;
case OPT_muintr:
if (value)
{
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_UINTR_SET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_SET;
}
else
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_UINTR_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_UNSET;
}
return true;
case OPT_mhreset:
if (value)
{
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_HRESET_SET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_SET;
}
else
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_HRESET_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_UNSET;
}
return true;
case OPT_mavx5124fmaps:
if (value)
{
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX5124FMAPS_SET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124FMAPS_SET;
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
}
else
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX5124FMAPS_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124FMAPS_UNSET;
}
return true;
case OPT_mavx5124vnniw:
if (value)
{
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX5124VNNIW_SET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124VNNIW_SET;
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
}
else
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX5124VNNIW_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124VNNIW_UNSET;
}
return true;
case OPT_mavx512vbmi2:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI2_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET;
opts->x_ix86_no_avx512_explicit = 1;
}
return true;
case OPT_mavx512fp16:
if (value)
{
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512FP16_SET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_SET;
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512FP16_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512FP16_SET;
}
else
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512FP16_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_UNSET;
opts->x_ix86_no_avx512_explicit = 1;
}
return true;
case OPT_mavx512vnni:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VNNI_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET;
opts->x_ix86_no_avx512_explicit = 1;
}
return true;
case OPT_mavx512vpopcntdq:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
opts->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
opts->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
opts->x_ix86_no_avx512_explicit = 1;
}
return true;
case OPT_mavx512bitalg:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BITALG_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BITALG_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET;
opts->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512BITALG_UNSET;
opts->x_ix86_no_avx512_explicit = 1;
}
return true;
case OPT_mavx512bf16:
if (value)
{
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512BF16_SET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_SET;
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
}
else
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BF16_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_UNSET;
opts->x_ix86_no_avx512_explicit = 1;
}
return true;
case OPT_mavxvnni:
if (value)
{
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNI_SET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXVNNI_SET;