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aarch64.md
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aarch64.md
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;; Machine description for AArch64 architecture.
;; Copyright (C) 2009-2024 Free Software Foundation, Inc.
;; Contributed by ARM Ltd.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful, but
;; WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
;; General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Register numbers
(define_constants
[
(R0_REGNUM 0)
(R1_REGNUM 1)
(R2_REGNUM 2)
(R3_REGNUM 3)
(R4_REGNUM 4)
(R5_REGNUM 5)
(R6_REGNUM 6)
(R7_REGNUM 7)
(R8_REGNUM 8)
(R9_REGNUM 9)
(R10_REGNUM 10)
(R11_REGNUM 11)
(R12_REGNUM 12)
(R13_REGNUM 13)
(R14_REGNUM 14)
(R15_REGNUM 15)
(R16_REGNUM 16)
(R17_REGNUM 17)
(R18_REGNUM 18)
(R19_REGNUM 19)
(R20_REGNUM 20)
(R21_REGNUM 21)
(R22_REGNUM 22)
(R23_REGNUM 23)
(R24_REGNUM 24)
(R25_REGNUM 25)
(R26_REGNUM 26)
(R27_REGNUM 27)
(R28_REGNUM 28)
(R29_REGNUM 29)
(R30_REGNUM 30)
(SP_REGNUM 31)
(V0_REGNUM 32)
(V1_REGNUM 33)
(V2_REGNUM 34)
(V3_REGNUM 35)
(V4_REGNUM 36)
(V5_REGNUM 37)
(V6_REGNUM 38)
(V7_REGNUM 39)
(V8_REGNUM 40)
(V9_REGNUM 41)
(V10_REGNUM 42)
(V11_REGNUM 43)
(V12_REGNUM 44)
(V13_REGNUM 45)
(V14_REGNUM 46)
(V15_REGNUM 47)
(V16_REGNUM 48)
(V17_REGNUM 49)
(V18_REGNUM 50)
(V19_REGNUM 51)
(V20_REGNUM 52)
(V21_REGNUM 53)
(V22_REGNUM 54)
(V23_REGNUM 55)
(V24_REGNUM 56)
(V25_REGNUM 57)
(V26_REGNUM 58)
(V27_REGNUM 59)
(V28_REGNUM 60)
(V29_REGNUM 61)
(V30_REGNUM 62)
(V31_REGNUM 63)
(SFP_REGNUM 64)
(AP_REGNUM 65)
(CC_REGNUM 66)
;; Defined only to make the DWARF description simpler.
(VG_REGNUM 67)
(P0_REGNUM 68)
(P1_REGNUM 69)
(P2_REGNUM 70)
(P3_REGNUM 71)
(P4_REGNUM 72)
(P5_REGNUM 73)
(P6_REGNUM 74)
(P7_REGNUM 75)
(P8_REGNUM 76)
(P9_REGNUM 77)
(P10_REGNUM 78)
(P11_REGNUM 79)
(P12_REGNUM 80)
(P13_REGNUM 81)
(P14_REGNUM 82)
(P15_REGNUM 83)
(LAST_SAVED_REGNUM 83)
(FFR_REGNUM 84)
;; "FFR token": a fake register used for representing the scheduling
;; restrictions on FFR-related operations.
(FFRT_REGNUM 85)
;; ----------------------------------------------------------------
;; Fake registers
;; ----------------------------------------------------------------
;; These registers represent abstract things, rather than real
;; architected registers.
;; Sometimes we use placeholder instructions to mark where later
;; ABI-related lowering is needed. These placeholders read and
;; write this register. Instructions that depend on the lowering
;; read the register.
(LOWERING_REGNUM 86)
;; Represents the contents of the current function's TPIDR2 block,
;; in abstract form.
(TPIDR2_BLOCK_REGNUM 87)
;; Holds the value that the current function wants PSTATE.ZA to be.
;; The actual value can sometimes vary, because it does not track
;; changes to PSTATE.ZA that happen during a lazy save and restore.
;; Those effects are instead tracked by ZA_SAVED_REGNUM.
(SME_STATE_REGNUM 88)
;; Instructions write to this register if they set TPIDR2_EL0 to a
;; well-defined value. Instructions read from the register if they
;; depend on the result of such writes.
;;
;; The register does not model the architected TPIDR2_ELO, just the
;; current function's management of it.
(TPIDR2_SETUP_REGNUM 89)
;; Represents the property "has an incoming lazy save been committed?".
(ZA_FREE_REGNUM 90)
;; Represents the property "are the current function's ZA contents
;; stored in the lazy save buffer, rather than in ZA itself?".
(ZA_SAVED_REGNUM 91)
;; Represents the contents of the current function's ZA state in
;; abstract form. At various times in the function, these contents
;; might be stored in ZA itself, or in the function's lazy save buffer.
;;
;; The contents persist even when the architected ZA is off. Private-ZA
;; functions have no effect on its contents.
(ZA_REGNUM 92)
;; Similarly represents the contents of the current function's ZT0 state.
(ZT0_REGNUM 93)
(FIRST_FAKE_REGNUM LOWERING_REGNUM)
(LAST_FAKE_REGNUM ZT0_REGNUM)
;; ----------------------------------------------------------------
;; The pair of scratch registers used for stack probing with -fstack-check.
;; Leave R9 alone as a possible choice for the static chain.
;; Note that the use of these registers is mutually exclusive with the use
;; of STACK_CLASH_SVE_CFA_REGNUM, which is for -fstack-clash-protection
;; rather than -fstack-check.
(PROBE_STACK_FIRST_REGNUM 10)
(PROBE_STACK_SECOND_REGNUM 11)
;; Scratch register used by stack clash protection to calculate
;; SVE CFA offsets during probing.
(STACK_CLASH_SVE_CFA_REGNUM 11)
;; Scratch registers for prologue/epilogue use.
(EP0_REGNUM 12)
(EP1_REGNUM 13)
;; A couple of call-clobbered registers that we need to reserve when
;; tracking speculation this is not ABI, so is subject to change.
(SPECULATION_SCRATCH_REGNUM 14)
(SPECULATION_TRACKER_REGNUM 15)
;; Scratch registers used in frame layout.
(IP0_REGNUM 16)
(IP1_REGNUM 17)
(FP_REGNUM 29)
(LR_REGNUM 30)
]
)
(define_c_enum "unspec" [
UNSPEC_AUTIA1716
UNSPEC_AUTIB1716
UNSPEC_AUTIASP
UNSPEC_AUTIBSP
UNSPEC_CALLEE_ABI
UNSPEC_CASESI
UNSPEC_CPYMEM
UNSPEC_CRC32B
UNSPEC_CRC32CB
UNSPEC_CRC32CH
UNSPEC_CRC32CW
UNSPEC_CRC32CX
UNSPEC_CRC32H
UNSPEC_CRC32W
UNSPEC_CRC32X
UNSPEC_FCVTZS
UNSPEC_FCVTZU
UNSPEC_FJCVTZS
UNSPEC_FRINT32Z
UNSPEC_FRINT32X
UNSPEC_FRINT64Z
UNSPEC_FRINT64X
UNSPEC_URECPE
UNSPEC_FRECPE
UNSPEC_FRECPS
UNSPEC_FRECPX
UNSPEC_FRINTA
UNSPEC_FRINTI
UNSPEC_FRINTM
UNSPEC_FRINTN
UNSPEC_FRINTP
UNSPEC_FRINTX
UNSPEC_FRINTZ
UNSPEC_GOTSMALLPIC
UNSPEC_GOTSMALLPIC28K
UNSPEC_GOTSMALLTLS
UNSPEC_GOTTINYPIC
UNSPEC_GOTTINYTLS
UNSPEC_STP
UNSPEC_LDP_FST
UNSPEC_LDP_SND
UNSPEC_LD1
UNSPEC_LD2
UNSPEC_LD2_DREG
UNSPEC_LD2_DUP
UNSPEC_LD3
UNSPEC_LD3_DREG
UNSPEC_LD3_DUP
UNSPEC_LD4
UNSPEC_LD4_DREG
UNSPEC_LD4_DUP
UNSPEC_LD2_LANE
UNSPEC_LD3_LANE
UNSPEC_LD4_LANE
UNSPEC_LD64B
UNSPEC_ST64B
UNSPEC_ST64BV
UNSPEC_ST64BV_RET
UNSPEC_ST64BV0
UNSPEC_ST64BV0_RET
UNSPEC_MB
UNSPEC_MOVMEM
UNSPEC_NOP
UNSPEC_PACIA1716
UNSPEC_PACIB1716
UNSPEC_PACIASP
UNSPEC_PACIBSP
UNSPEC_PRLG_STK
UNSPEC_REV
UNSPEC_RBIT
UNSPEC_SADALP
UNSPEC_SCVTF
UNSPEC_SETMEM
UNSPEC_SISD_NEG
UNSPEC_SISD_SSHL
UNSPEC_SISD_USHL
UNSPEC_SSHL_2S
UNSPEC_ST1
UNSPEC_ST2
UNSPEC_ST3
UNSPEC_ST4
UNSPEC_ST2_LANE
UNSPEC_ST3_LANE
UNSPEC_ST4_LANE
UNSPEC_TLS
UNSPEC_TLSDESC
UNSPEC_TLSLE12
UNSPEC_TLSLE24
UNSPEC_TLSLE32
UNSPEC_TLSLE48
UNSPEC_UADALP
UNSPEC_UCVTF
UNSPEC_USHL_2S
UNSPEC_VSTRUCTDUMMY
UNSPEC_SSP_SYSREG
UNSPEC_SP_SET
UNSPEC_SP_TEST
UNSPEC_RSQRT
UNSPEC_RSQRTE
UNSPEC_RSQRTS
UNSPEC_NZCV
UNSPEC_XPACLRI
UNSPEC_LD1_SVE
UNSPEC_ST1_SVE
UNSPEC_LDNT1_SVE
UNSPEC_STNT1_SVE
UNSPEC_LD1RQ
UNSPEC_LD1_GATHER
UNSPEC_LDFF1_GATHER
UNSPEC_LDNT1_GATHER
UNSPEC_ST1_SCATTER
UNSPEC_STNT1_SCATTER
UNSPEC_PRED_X
UNSPEC_PRED_Z
UNSPEC_PTEST
UNSPEC_PTRUE
UNSPEC_UNPACKSHI
UNSPEC_UNPACKUHI
UNSPEC_UNPACKSLO
UNSPEC_UNPACKULO
UNSPEC_PACK
UNSPEC_WHILEGE
UNSPEC_WHILEGT
UNSPEC_WHILEHI
UNSPEC_WHILEHS
UNSPEC_WHILELE
UNSPEC_WHILELO
UNSPEC_WHILELS
UNSPEC_WHILELT
UNSPEC_WHILERW
UNSPEC_WHILEWR
UNSPEC_LDN
UNSPEC_STN
UNSPEC_INSR
UNSPEC_CLASTA
UNSPEC_CLASTB
UNSPEC_FADDA
UNSPEC_REV_SUBREG
UNSPEC_REINTERPRET
UNSPEC_SPECULATION_TRACKER
UNSPEC_SPECULATION_TRACKER_REV
UNSPEC_COPYSIGN
UNSPEC_TTEST ; Represent transaction test.
UNSPEC_UPDATE_FFR
UNSPEC_UPDATE_FFRT
UNSPEC_RDFFR
UNSPEC_WRFFR
UNSPEC_SYSREG_RDI
UNSPEC_SYSREG_RTI
UNSPEC_SYSREG_WDI
UNSPEC_SYSREG_WTI
UNSPEC_PLDX
;; Represents an SVE-style lane index, in which the indexing applies
;; within the containing 128-bit block.
UNSPEC_SVE_LANE_SELECT
UNSPEC_SVE_CNT_PAT
UNSPEC_SVE_PREFETCH
UNSPEC_SVE_PREFETCH_GATHER
UNSPEC_SVE_COMPACT
UNSPEC_SVE_SPLICE
UNSPEC_GEN_TAG ; Generate a 4-bit MTE tag.
UNSPEC_GEN_TAG_RND ; Generate a random 4-bit MTE tag.
UNSPEC_TAG_SPACE ; Translate address to MTE tag address space.
UNSPEC_LD1RO
UNSPEC_SALT_ADDR
UNSPEC_SAVE_NZCV
UNSPEC_RESTORE_NZCV
UNSPECV_PATCHABLE_AREA
UNSPEC_LDAP1_LANE
UNSPEC_STL1_LANE
;; Wraps a constant integer that should be multiplied by the number
;; of quadwords in an SME vector.
UNSPEC_SME_VQ
])
(define_c_enum "unspecv" [
UNSPECV_EH_RETURN ; Represent EH_RETURN
UNSPECV_GET_FPCR ; Represent fetch of FPCR content.
UNSPECV_SET_FPCR ; Represent assign of FPCR content.
UNSPECV_GET_FPSR ; Represent fetch of FPSR content.
UNSPECV_SET_FPSR ; Represent assign of FPSR content.
UNSPECV_BLOCKAGE ; Represent a blockage
UNSPECV_PROBE_STACK_RANGE ; Represent stack range probing.
UNSPECV_SPECULATION_BARRIER ; Represent speculation barrier.
UNSPECV_BTI_NOARG ; Represent BTI.
UNSPECV_BTI_C ; Represent BTI c.
UNSPECV_BTI_J ; Represent BTI j.
UNSPECV_BTI_JC ; Represent BTI jc.
UNSPECV_TSTART ; Represent transaction start.
UNSPECV_TCOMMIT ; Represent transaction commit.
UNSPECV_TCANCEL ; Represent transaction cancel.
UNSPEC_RNDR ; Represent RNDR
UNSPEC_RNDRRS ; Represent RNDRRS
]
)
;; These constants are used as a const_int in various SVE unspecs
;; to indicate whether the governing predicate is known to be a PTRUE.
(define_constants
[; Indicates that the predicate might not be a PTRUE.
(SVE_MAYBE_NOT_PTRUE 0)
; Indicates that the predicate is known to be a PTRUE.
(SVE_KNOWN_PTRUE 1)])
;; These constants are used as a const_int in predicated SVE FP arithmetic
;; to indicate whether the operation is allowed to make additional lanes
;; active without worrying about the effect on faulting behavior.
(define_constants
[; Indicates either that all lanes are active or that the instruction may
; operate on inactive inputs even if doing so could induce a fault.
(SVE_RELAXED_GP 0)
; Indicates that some lanes might be inactive and that the instruction
; must not operate on inactive inputs if doing so could induce a fault.
(SVE_STRICT_GP 1)])
(include "constraints.md")
(include "predicates.md")
(include "iterators.md")
;; -------------------------------------------------------------------
;; Instruction types and attributes
;; -------------------------------------------------------------------
; The "type" attribute is included here from AArch32 backend to be able
; to share pipeline descriptions.
(include "../arm/types.md")
;; It is important to set the fp or simd attributes to yes when a pattern
;; alternative uses the FP or SIMD register files, usually signified by use of
;; the 'w' constraint. This will ensure that the alternative will be
;; disabled when compiling with -mgeneral-regs-only or with the +nofp/+nosimd
;; architecture extensions. If all the alternatives in a pattern use the
;; FP or SIMD registers then the pattern predicate should include TARGET_FLOAT
;; or TARGET_SIMD.
;; Attributes of the architecture required to support the instruction (or
;; alternative). This attribute is used to compute attribute "enabled", use type
;; "any" to enable an alternative in all cases.
;;
;; As a convenience, "fp_q" means "fp" + the ability to move between
;; Q registers and is equivalent to "simd".
(define_enum "arches" [any rcpc8_4 fp fp_q base_simd nobase_simd
simd nosimd sve fp16 sme])
(define_enum_attr "arch" "arches" (const_string "any"))
;; Whether a normal INSN in fact contains a call. Sometimes we represent
;; calls to functions that use an ad-hoc ABI as normal insns, both for
;; optimization reasons and to avoid the need to describe the ABI to
;; target-independent code.
(define_attr "is_call" "no,yes" (const_string "no"))
;; [For compatibility with Arm in pipeline models]
;; Attribute that specifies whether or not the instruction touches fp
;; registers.
;; Note that this attribute is not used anywhere in either the arm or aarch64
;; backends except in the scheduling description for xgene1. In that
;; scheduling description this attribute is used to subclass the load_4 and
;; load_8 types.
(define_attr "fp" "no,yes"
(if_then_else
(eq_attr "arch" "fp")
(const_string "yes")
(const_string "no")))
(define_attr "arch_enabled" "no,yes"
(if_then_else
(ior
(eq_attr "arch" "any")
(and (eq_attr "arch" "rcpc8_4")
(match_test "AARCH64_ISA_RCPC8_4"))
(and (eq_attr "arch" "fp")
(match_test "TARGET_FLOAT"))
(and (eq_attr "arch" "base_simd")
(match_test "TARGET_BASE_SIMD"))
(and (eq_attr "arch" "nobase_simd")
(match_test "!TARGET_BASE_SIMD"))
(and (eq_attr "arch" "fp_q, simd")
(match_test "TARGET_SIMD"))
(and (eq_attr "arch" "nosimd")
(match_test "!TARGET_SIMD"))
(and (eq_attr "arch" "fp16")
(match_test "TARGET_FP_F16INST"))
(and (eq_attr "arch" "sve")
(match_test "TARGET_SVE"))
(and (eq_attr "arch" "sme")
(match_test "TARGET_SME")))
(const_string "yes")
(const_string "no")))
;; Attribute that controls whether an alternative is enabled or not.
;; Currently it is only used to disable alternatives which touch fp or simd
;; registers when -mgeneral-regs-only is specified or to require a special
;; architecture support.
(define_attr "enabled" "no,yes" (attr "arch_enabled"))
;; Attribute that specifies whether we are dealing with a branch to a
;; label that is far away, i.e. further away than the maximum/minimum
;; representable in a signed 21-bits number.
;; 0 :=: no
;; 1 :=: yes
(define_attr "far_branch" "" (const_int 0))
;; Attribute that specifies whether the alternative uses MOVPRFX.
(define_attr "movprfx" "no,yes" (const_string "no"))
;; Attribute to specify that an alternative has the length of a single
;; instruction plus a speculation barrier.
(define_attr "sls_length" "none,retbr,casesi" (const_string "none"))
(define_attr "length" ""
(cond [(eq_attr "movprfx" "yes")
(const_int 8)
(eq_attr "sls_length" "retbr")
(cond [(match_test "!aarch64_harden_sls_retbr_p ()") (const_int 4)
(match_test "TARGET_SB") (const_int 8)]
(const_int 12))
(eq_attr "sls_length" "casesi")
(cond [(match_test "!aarch64_harden_sls_retbr_p ()") (const_int 16)
(match_test "TARGET_SB") (const_int 20)]
(const_int 24))
]
(const_int 4)))
;; Strictly for compatibility with AArch32 in pipeline models, since AArch64 has
;; no predicated insns.
(define_attr "predicated" "yes,no" (const_string "no"))
;; Set to true on an insn that requires the speculation tracking state to be
;; in the tracking register before the insn issues. Otherwise the compiler
;; may chose to hold the tracking state encoded in SP.
(define_attr "speculation_barrier" "true,false" (const_string "false"))
;; This attribute is attached to multi-register instructions that have
;; two forms: one in which the registers are consecutive and one in
;; which they are strided. The consecutive and strided forms have
;; different define_insns, with different operands. The mapping between
;; the RTL of the consecutive form and the RTL of the strided form varies
;; from one type of instruction to another.
;;
;; The attribute gives two pieces of information:
;; - does the current instruction have consecutive or strided registers?
;; - what kind of RTL rewrite is needed to move between forms?
;;
;; For example, all consecutive LD*1 instructions have the same basic
;; RTL structure. The same applies to all strided LD*1 instructions.
;; The RTL mapping therefore applies at LD1 granularity, rather than
;; being broken down into individual types of load.
(define_attr "stride_type"
"none,ld1_consecutive,ld1_strided,st1_consecutive,st1_strided"
(const_string "none"))
;; Attribute used to identify load pair and store pair instructions.
;; Currently the attribute is only applied to the non-writeback ldp/stp
;; patterns.
(define_attr "ldpstp" "ldp,stp,none" (const_string "none"))
;; -------------------------------------------------------------------
;; Pipeline descriptions and scheduling
;; -------------------------------------------------------------------
;; Processor types.
(include "aarch64-tune.md")
;; Scheduling
(include "../arm/cortex-a53.md")
(include "../arm/cortex-a57.md")
(include "../arm/exynos-m1.md")
(include "falkor.md")
(include "saphira.md")
(include "thunderx.md")
(include "../arm/xgene1.md")
(include "thunderx2t99.md")
(include "tsv110.md")
(include "thunderx3t110.md")
;; -------------------------------------------------------------------
;; Jumps and other miscellaneous insns
;; -------------------------------------------------------------------
(define_insn "aarch64_read_sysregdi"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec_volatile:DI [(match_operand 1 "aarch64_sysreg_string" "")]
UNSPEC_SYSREG_RDI))]
""
"mrs\t%x0, %1"
)
(define_insn "aarch64_read_sysregti"
[(set (match_operand:TI 0 "register_operand" "=r")
(unspec_volatile:TI [(match_operand 1 "aarch64_sysreg_string" "")]
UNSPEC_SYSREG_RTI))]
"TARGET_D128"
"mrrs\t%x0, %H0, %x1"
)
(define_insn "aarch64_write_sysregdi"
[(unspec_volatile:DI [(match_operand 0 "aarch64_sysreg_string" "")
(match_operand:DI 1 "register_operand" "rZ")]
UNSPEC_SYSREG_WDI)]
""
"msr\t%0, %x1"
)
(define_insn "aarch64_write_sysregti"
[(unspec_volatile:TI [(match_operand 0 "aarch64_sysreg_string" "")
(match_operand:TI 1 "register_operand" "r")]
UNSPEC_SYSREG_WTI)]
"TARGET_D128"
"msrr\t%x0, %x1, %H1"
)
(define_insn "indirect_jump"
[(set (pc) (match_operand:DI 0 "register_operand" "r"))]
""
{
output_asm_insn ("br\\t%0", operands);
return aarch64_sls_barrier (aarch64_harden_sls_retbr_p ());
}
[(set_attr "type" "branch")
(set_attr "sls_length" "retbr")]
)
(define_insn "jump"
[(set (pc) (label_ref (match_operand 0 "" "")))]
""
"b\\t%l0"
[(set_attr "type" "branch")]
)
(define_expand "cbranch<mode>4"
[(set (pc) (if_then_else (match_operator 0 "aarch64_comparison_operator"
[(match_operand:GPI 1 "register_operand")
(match_operand:GPI 2 "aarch64_plus_operand")])
(label_ref (match_operand 3 "" ""))
(pc)))]
""
"
operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1],
operands[2]);
operands[2] = const0_rtx;
"
)
(define_expand "cbranch<mode>4"
[(set (pc) (if_then_else (match_operator 0 "aarch64_comparison_operator"
[(match_operand:GPF 1 "register_operand")
(match_operand:GPF 2 "aarch64_fp_compare_operand")])
(label_ref (match_operand 3 "" ""))
(pc)))]
""
"
operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1],
operands[2]);
operands[2] = const0_rtx;
"
)
(define_expand "cbranchcc4"
[(set (pc) (if_then_else
(match_operator 0 "aarch64_comparison_operator"
[(match_operand 1 "cc_register")
(match_operand 2 "const0_operand")])
(label_ref (match_operand 3 "" ""))
(pc)))]
""
"")
(define_insn "@ccmp<CC_ONLY:mode><GPI:mode>"
[(set (match_operand:CC_ONLY 1 "cc_register")
(if_then_else:CC_ONLY
(match_operator 4 "aarch64_comparison_operator"
[(match_operand 0 "cc_register")
(const_int 0)])
(compare:CC_ONLY
(match_operand:GPI 2 "register_operand")
(match_operand:GPI 3 "aarch64_ccmp_operand"))
(unspec:CC_ONLY
[(match_operand 5 "immediate_operand")]
UNSPEC_NZCV)))]
""
{@ [ cons: 2 , 3 ; attrs: type ]
[ r , r ; alus_sreg ] ccmp\t%<w>2, %<w>3, %k5, %m4
[ r , Uss ; alus_imm ] ccmp\t%<w>2, %3, %k5, %m4
[ r , Usn ; alus_imm ] ccmn\t%<w>2, #%n3, %k5, %m4
}
)
(define_insn "@ccmp<CCFP_CCFPE:mode><GPF:mode>"
[(set (match_operand:CCFP_CCFPE 1 "cc_register" "")
(if_then_else:CCFP_CCFPE
(match_operator 4 "aarch64_comparison_operator"
[(match_operand 0 "cc_register" "")
(const_int 0)])
(compare:CCFP_CCFPE
(match_operand:GPF 2 "register_operand" "w")
(match_operand:GPF 3 "register_operand" "w"))
(unspec:CCFP_CCFPE
[(match_operand 5 "immediate_operand")]
UNSPEC_NZCV)))]
"TARGET_FLOAT"
"fccmp<e>\\t%<s>2, %<s>3, %k5, %m4"
[(set_attr "type" "fccmp<s>")]
)
(define_insn "@ccmp<CC_ONLY:mode><GPI:mode>_rev"
[(set (match_operand:CC_ONLY 1 "cc_register")
(if_then_else:CC_ONLY
(match_operator 4 "aarch64_comparison_operator"
[(match_operand 0 "cc_register")
(const_int 0)])
(unspec:CC_ONLY
[(match_operand 5 "immediate_operand")]
UNSPEC_NZCV)
(compare:CC_ONLY
(match_operand:GPI 2 "register_operand")
(match_operand:GPI 3 "aarch64_ccmp_operand"))))]
""
{@ [ cons: 2 , 3 ; attrs: type ]
[ r , r ; alus_sreg ] ccmp\t%<w>2, %<w>3, %k5, %M4
[ r , Uss ; alus_imm ] ccmp\t%<w>2, %3, %k5, %M4
[ r , Usn ; alus_imm ] ccmn\t%<w>2, #%n3, %k5, %M4
}
)
(define_insn "@ccmp<CCFP_CCFPE:mode><GPF:mode>_rev"
[(set (match_operand:CCFP_CCFPE 1 "cc_register" "")
(if_then_else:CCFP_CCFPE
(match_operator 4 "aarch64_comparison_operator"
[(match_operand 0 "cc_register" "")
(const_int 0)])
(unspec:CCFP_CCFPE
[(match_operand 5 "immediate_operand")]
UNSPEC_NZCV)
(compare:CCFP_CCFPE
(match_operand:GPF 2 "register_operand" "w")
(match_operand:GPF 3 "register_operand" "w"))))]
"TARGET_FLOAT"
"fccmp<e>\\t%<s>2, %<s>3, %k5, %M4"
[(set_attr "type" "fccmp<s>")]
)
;; Expansion of signed mod by a power of 2 using CSNEG.
;; For x0 % n where n is a power of 2 produce:
;; negs x1, x0
;; and x0, x0, #(n - 1)
;; and x1, x1, #(n - 1)
;; csneg x0, x0, x1, mi
(define_expand "mod<mode>3"
[(match_operand:GPI 0 "register_operand")
(match_operand:GPI 1 "register_operand")
(match_operand:GPI 2 "const_int_operand")]
""
{
HOST_WIDE_INT val = INTVAL (operands[2]);
if (val <= 0
|| exact_log2 (val) <= 0
|| !aarch64_bitmask_imm (val - 1, <MODE>mode))
FAIL;
rtx mask = GEN_INT (val - 1);
/* In the special case of x0 % 2 we can do the even shorter:
cmp x0, xzr
and x0, x0, 1
cneg x0, x0, lt. */
if (val == 2)
{
rtx masked = gen_reg_rtx (<MODE>mode);
rtx ccreg = aarch64_gen_compare_reg (LT, operands[1], const0_rtx);
emit_insn (gen_and<mode>3 (masked, operands[1], mask));
rtx x = gen_rtx_LT (VOIDmode, ccreg, const0_rtx);
emit_insn (gen_csneg3<mode>_insn (operands[0], x, masked, masked));
DONE;
}
rtx neg_op = gen_reg_rtx (<MODE>mode);
rtx_insn *insn = emit_insn (gen_neg<mode>2_compare0 (neg_op, operands[1]));
/* Extract the condition register and mode. */
rtx cmp = XVECEXP (PATTERN (insn), 0, 0);
rtx cc_reg = SET_DEST (cmp);
rtx cond = gen_rtx_GE (VOIDmode, cc_reg, const0_rtx);
rtx masked_pos = gen_reg_rtx (<MODE>mode);
emit_insn (gen_and<mode>3 (masked_pos, operands[1], mask));
rtx masked_neg = gen_reg_rtx (<MODE>mode);
emit_insn (gen_and<mode>3 (masked_neg, neg_op, mask));
emit_insn (gen_csneg3<mode>_insn (operands[0], cond,
masked_neg, masked_pos));
DONE;
}
)
(define_insn "condjump"
[(set (pc) (if_then_else (match_operator 0 "aarch64_comparison_operator"
[(match_operand 1 "cc_register" "") (const_int 0)])
(label_ref (match_operand 2 "" ""))
(pc)))]
""
{
/* GCC's traditional style has been to use "beq" instead of "b.eq", etc.,
but the "." is required for SVE conditions. */
bool use_dot_p = GET_MODE (operands[1]) == CC_NZCmode;
if (get_attr_length (insn) == 8)
return aarch64_gen_far_branch (operands, 2, "Lbcond",
use_dot_p ? "b.%M0\\t" : "b%M0\\t");
else
return use_dot_p ? "b.%m0\\t%l2" : "b%m0\\t%l2";
}
[(set_attr "type" "branch")
(set (attr "length")
(if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -1048576))
(lt (minus (match_dup 2) (pc)) (const_int 1048572)))
(const_int 4)
(const_int 8)))
(set (attr "far_branch")
(if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -1048576))
(lt (minus (match_dup 2) (pc)) (const_int 1048572)))
(const_int 0)
(const_int 1)))]
)
;; For a 24-bit immediate CST we can optimize the compare for equality
;; and branch sequence from:
;; mov x0, #imm1
;; movk x0, #imm2, lsl 16 /* x0 contains CST. */
;; cmp x1, x0
;; b<ne,eq> .Label
;; into the shorter:
;; sub x0, x1, #(CST & 0xfff000)
;; subs x0, x0, #(CST & 0x000fff)
;; b<ne,eq> .Label
(define_insn_and_split "*compare_condjump<GPI:mode>"
[(set (pc) (if_then_else (EQL
(match_operand:GPI 0 "register_operand" "r")
(match_operand:GPI 1 "aarch64_imm24" "n"))
(label_ref:P (match_operand 2 "" ""))
(pc)))]
"!aarch64_move_imm (INTVAL (operands[1]), <GPI:MODE>mode)
&& !aarch64_plus_operand (operands[1], <GPI:MODE>mode)
&& !reload_completed"
"#"
"&& true"
[(const_int 0)]
{
HOST_WIDE_INT lo_imm = UINTVAL (operands[1]) & 0xfff;
HOST_WIDE_INT hi_imm = UINTVAL (operands[1]) & 0xfff000;
rtx tmp = gen_reg_rtx (<GPI:MODE>mode);
emit_insn (gen_add<GPI:mode>3 (tmp, operands[0], GEN_INT (-hi_imm)));
emit_insn (gen_add<GPI:mode>3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
rtx cmp_rtx = gen_rtx_fmt_ee (<EQL:CMP>, <GPI:MODE>mode,
cc_reg, const0_rtx);
emit_jump_insn (gen_condjump (cmp_rtx, cc_reg, operands[2]));
DONE;
}
)
(define_expand "casesi"
[(match_operand:SI 0 "register_operand") ; Index
(match_operand:SI 1 "const_int_operand") ; Lower bound
(match_operand:SI 2 "const_int_operand") ; Total range
(match_operand:DI 3 "" "") ; Table label
(match_operand:DI 4 "" "")] ; Out of range label
""
{
if (operands[1] != const0_rtx)
{
rtx reg = gen_reg_rtx (SImode);
/* Canonical RTL says that if you have:
(minus (X) (CONST))
then this should be emitted as:
(plus (X) (-CONST))
The use of trunc_int_for_mode ensures that the resulting
constant can be represented in SImode, this is important
for the corner case where operand[1] is INT_MIN. */
operands[1]
= GEN_INT (trunc_int_for_mode (-UINTVAL (operands[1]), SImode));
if (!(*insn_data[CODE_FOR_addsi3].operand[2].predicate)
(operands[1], SImode))
operands[1] = force_reg (SImode, operands[1]);
emit_insn (gen_addsi3 (reg, operands[0], operands[1]));
operands[0] = reg;
}
if (!aarch64_plus_operand (operands[2], SImode))
operands[2] = force_reg (SImode, operands[2]);
emit_jump_insn (gen_cbranchsi4 (gen_rtx_GTU (SImode, const0_rtx,
const0_rtx),
operands[0], operands[2], operands[4]));
operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[3]));
operands[2]
= gen_rtx_UNSPEC (Pmode, gen_rtvec (2, operands[2], operands[0]),
UNSPEC_CASESI);
operands[2] = gen_rtx_MEM (DImode, operands[2]);
MEM_READONLY_P (operands[2]) = 1;
MEM_NOTRAP_P (operands[2]) = 1;
emit_jump_insn (gen_casesi_dispatch (operands[2], operands[3]));
DONE;
}
)
(define_expand "casesi_dispatch"
[(parallel
[(set (pc) (match_operand:DI 0 ""))
(clobber (reg:CC CC_REGNUM))
(clobber (match_scratch:DI 2))
(clobber (match_scratch:DI 3))
(use (label_ref:DI (match_operand 1 "")))])]
"")
(define_insn "*casesi_dispatch"
[(parallel
[(set (pc)
(mem:DI (unspec [(match_operand:DI 0 "register_operand" "r")
(match_operand:SI 1 "register_operand" "r")]
UNSPEC_CASESI)))
(clobber (reg:CC CC_REGNUM))
(clobber (match_scratch:DI 3 "=r"))
(clobber (match_scratch:DI 4 "=r"))
(use (label_ref:DI (match_operand 2 "" "")))])]
""
"*
return aarch64_output_casesi (operands);
"
[(set_attr "sls_length" "casesi")
(set_attr "type" "branch")]
)
(define_insn "nop"
[(unspec[(const_int 0)] UNSPEC_NOP)]
""
"nop"
[(set_attr "type" "no_insn")]
)
(define_insn "prefetch"
[(prefetch (match_operand:DI 0 "aarch64_prefetch_operand" "Dp")
(match_operand:QI 1 "const_int_operand" "")
(match_operand:QI 2 "const_int_operand" ""))]
""
{
const char * pftype[2][4] =
{
{"prfm\\tPLDL1STRM, %0",
"prfm\\tPLDL3KEEP, %0",
"prfm\\tPLDL2KEEP, %0",
"prfm\\tPLDL1KEEP, %0"},
{"prfm\\tPSTL1STRM, %0",
"prfm\\tPSTL3KEEP, %0",
"prfm\\tPSTL2KEEP, %0",
"prfm\\tPSTL1KEEP, %0"},
};
int locality = INTVAL (operands[2]);
gcc_assert (IN_RANGE (locality, 0, 3));
/* PRFM accepts the same addresses as a 64-bit LDR so wrap
the address into a DImode MEM so that aarch64_print_operand knows
how to print it. */
operands[0] = gen_rtx_MEM (DImode, operands[0]);
return pftype[INTVAL(operands[1])][locality];
}
[(set_attr "type" "load_4")]
)
(define_insn "aarch64_pldx"
[(unspec [(match_operand 0 "" "")
(match_operand:DI 1 "aarch64_prefetch_operand" "Dp")] UNSPEC_PLDX)]
""
{
operands[1] = gen_rtx_MEM (DImode, operands[1]);
return "prfm\\t%0, %1";
}
[(set_attr "type" "load_4")]
)
(define_insn "trap"
[(trap_if (const_int 1) (const_int 8))]
""