SystemVerilog filetype syntax highlighting

[matsalleh92]

SystemVerilog is almost identical syntax to Verilog. It could be quite easy to support SystemVerilog filetype (.sv) using same rules as Verilog which is already implemented.

[elextr]

What filetype are you editing the .sv files as?

[cousteaulecommandant]

You can add the *.sv extension for Verilog in Tools > Configuration Files > file_extensions.conf, so that whenever you open a .sv file in Geany it gets detected and highlighted as a Verilog file.
But I'm not sure having Geany include that extension association by default would be a good idea.

Keep in mind that there will still be many SystemVerilog keywords that won't be highlighted as such, such as class, interface, package, import, assert, logic, etc. (You can also add those yourself in Tools > Configuration Files > Filetype Configuration > Programming Languages > filetypes.verilog, under [keywords].)
Also, the parser will not generate symbols for classes, structs, interfaces, etc in the list of symbols the way it does for other object-oriented languages such as C++; and it is possible that some SystemVerilog-only constructs lead to incorrect highlighting/folding when ignored or interpreted as plain Verilog. (There's no way to change this via config files.) So ultimately, SystemVerilog support will not be complete; just a workaround to view SystemVerilog files with almost correct syntax highlighting, but it won't be perfect.

It could be useful to have Geany include *.sv as an alternative extension for Verilog files by default (I personally have it configured that way), but I don't know if that would be a good idea since as I said this is more a workaround than an actual implementation of support for SystemVerilog, and adding that extension by default could be seen as Geany implicitly claiming to support SystemVerilog, when it really doesn't. (I don't know what's the policy on file extensions in this project; is it OK to add file extensions even if they're not exactly the same file type?)

A proper solution would be to actually implement a proper SystemVerilog parser in Geany (extending the one for Verilog), and then support both languages, but that's not as trivial as just pretending that .sv are plain Verilog files.

[elextr]

I don't know what's the policy on file extensions in this project; is it OK to add file extensions even if they're not exactly the same file type?

To emphasise, adding an extension tells Geany to treat *.sv files as Verilog, not that Geany supports SystemVerilog.

Probably better would be to add a custom filetype (rt"fine"m) that adds the keywords and assign *.sv to that. But as @cousteaulecommandant says the parser behaviour is not configurable, and possibly lexer subtleties may be wrong too. Custom filetypes are a "best effort" thing.

A proper solution would be to actually implement a proper SystemVerilog parser in Geany (extending the one for Verilog)

That would be even better, so your wish is my command 😁

So now all "somebody" has to do is make a built-in Geany filetype using that, see how the Verilog filetype is done, read HACKING and for example look at recent new filetypes such as Julia