MAR_LOAD logic creates a gated clock

[Gecko05]

MAR_LOAD signal creates a gated clock. Need to find a logic that won't generate gated clocks in the design.
Already tried using a natural number variable to count from 0 to 7 instead of the 8 clock signals, but that doesn't seem to solve the issue.

[Gecko05]

Apparently the registers' implementation was causing this. I wasn't using a rising_edge clock detection to load new values into the registers and somehow this caused the gated clock.