1_Sample_N_Samples_and_Continuous_Modes.md

1 Sample, N Samples, and Continuous Modes

The Python ELVIS III API provides functions for you to perform three I/O modes of signal acquisition and generation: 1 sample, n samples, and continuous. Use the following table to learn about these modes.

Note: N samples and continuous modes are available only for analog signals.

Operation	I/O Mode	Description	Use Case
Signal Acquisition	1 Sample	The NI ELVIS III acquires one sample for a channel. This mode uses software-timed acquisition. The sample rate of acquisition depends on the software loop rate on the real-time processor. Various factors can affect this loop rate, such as simultaneous running of multiple programs on the NI ELVIS III target.	Acquiring the most recent value or periodically monitoring low frequency signals, such as the temperature.
	N Samples	The NI ELVIS III acquires a finite number of samples for a channel. This mode has the following characteristics: Hardware-timed acquisition—The FPGA target on the NI ELVIS III has a 40 MHz clock, which controls the rate of acquisition. The sample rate depends on the hardware clock, which is faster than a software loop. A hardware clock is more accurate than a software loop. Therefore, you can have accurate control over the acquisition time between each sample. Buffered acquisition—FPGA transfers the samples from the FPGA target to an intermediate memory buffer using direct memory access (DMA) before LabVIEW reads these samples on the real-time processor. Finite acquisition—Acquires less than 10,000 samples on each channel. Gaps in the acquired signal exist between sequential n samples acquisitions.	Acquiring finite high frequency signals, such as an audio signal.
	Continuous	The NI ELVIS III continuously acquires samples for a channel until the acquisition is stopped. This mode has the following characteristics: Hardware-timed acquisition—The FPGA target on the NI ELVIS III has a 40 MHz clock, which controls the rate of acquisition. The sample rate depends on the hardware clock, which is faster than a software loop. A hardware clock is more accurate than a software loop. Therefore, you can have accurate control over the acquisition time between each sample. Buffered acquisition—FPGA transfers the samples from the FPGA target to an intermediate memory buffer using direct memory access (DMA) before LabVIEW reads these samples on the real-time processor. Continuous acquisition—Continuously acquires samples on each channel at a defined sampling rate until the acquisition is stopped. You can achieve continuous signal acquisition without gaps by using this mode.	Continuously acquiring signals for a long period of time.
Signal Generation	1 Sample	The NI ELVIS III generates one sample for a channel. This mode uses software-timed generation. The sample rate of generation depends on the software loop rate on the real-time processor. Various factors can affect this loop rate, such as the simultaneous running of multiple programs on the NI ELVIS III target.	Generating the most recent value or generating low frequency signals. For example, generating a known voltage to stimulate a device.
	N Samples	The NI ELVIS III generates a finite number of samples for a channel. This mode has the following characteristics: Hardware-timed generation—The FPGA target on the NI ELVIS III has a 40 MHz clock, which controls the rate of generation. The sample rate depends on the hardware clock, which is faster than a software loop. A hardware clock is more accurate than a software loop. Therefore, you can have accurate control over the time between each sample. Buffered generation—The real-time processor takes the samples from LabVIEW and places them in an intermediate memory buffer using DMA before FPGA gets the samples from the buffer. Finite generation—generates less than 10,000 samples on each channel. Gaps in the generated signal exist between sequential n samples generations.	Generating finite time-varying signals, such as an AC sine wave.
	Continuous	The NI ELVIS III continuously generates samples for a channel until the signal generation is stopped. This mode has the following characteristics: Hardware-timed generation—The FPGA target on the NI ELVIS III has a 40 MHz clock, which controls the rate of generation. The sample rate depends on the hardware clock, which is faster than a software loop. A hardware clock is more accurate than a software loop. Therefore, you can have accurate control over the time between each sample. Buffered generation—The real-time processor takes the samples from LabVIEW and places them in an intermediate memory buffer using DMA before FPGA gets the samples from the buffer. Continuous generation—Continuously generates samples on each channel at a defined update rate until the generation is stopped. You can achieve continuous signal generation without gaps by using this mode.	Continuously generating signals for a long period of time.