[ghdl --synth] $fatal not verilog task

[suppamax]

Description
ghdl --synth --out=verilog generates code which includes $fatal task, which is not a verilog task

Expected behaviour
maybe combining $display and $finish?

How to reproduce?
any code which executes

ghdl/src/synth/netlists-disp_verilog.adb

Line 1084 in aff4872

" $fatal(1, ""assertion failure \l0"");" & NL, Inst);

or

ghdl/src/synth/netlists-disp_verilog.adb

Line 1097 in aff4872

" $fatal(1, ""assertion(cover) failure \l0"");" & NL,

[tgingold]

Yes, but it's a systemverilog task. Use `--no-formal`

[suppamax]

OK, I just assumed you were targeting plain verilog, not SV.

[tgingold]

assertions in the netlist is useful for formal verification, hence the use of SV specific routines.
But if you want a pure verilog output, use --no-formal.