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This is neither a bug nor a feature request. It is just an interesting issue that came out when using GHDL with tools at machine level. The context is the following:
VUnit context is loaded in a testbench, and this is compiled with GHDL.
The disassembled (gdb) binary (produced after elaboration, ghdl -e) contains several branch instructions such as CBZ WZR <address> or CBNZ xZR <address>, where CBZ/CBNZ mean compare and branch if (not) zero; and WZR/xZR are hardcoded zero registers (32/64 bits respectively).
Instructions such as CBZ WZR <address> don't make sense. Comparing WZR with zero will always be true. So, it should have been compiled to B <address> (a direct branch, not a conditional one). By the same token, CBNZ xZR <address> should be a nop or not exists at all.
The resulting code (although ugly) works ok. I am just curious about why such strange code is generated from VUnit and not from other VHDL sources. However, I don't know how to further debug this:
Is it because how VUnit libraries are coded?
Is it because how GHDL manages/manipulates sources during elaboration?
Does it have nothing to do with either VUnit or GHDL, and is this done by LLVM?
I'd appreciate any hint, even if it involves not being worth to dig further.
The text was updated successfully, but these errors were encountered:
The number of LLVM optimisation passes enabled in ghdl is very limited. That's certainly something to improve.
Once enabled, I suppose these instructions shouldn't appear
No, it is not an advanced task.
LLVM has a long list of optimization passes. You need to find the most interesting ones and the best order.
There is a couple of passes already added in src/ortho/llvm-nodebug/ortho_code_main.adb (See code about PassManager).
Optimizations are enabled with -O.
This is neither a bug nor a feature request. It is just an interesting issue that came out when using GHDL with tools at machine level. The context is the following:
-fPIC
enabled; see Context of Work around current limitations ofghdl --list-link
#640.ghdl -e
) contains several branch instructions such asCBZ WZR <address>
orCBNZ xZR <address>
, whereCBZ
/CBNZ
mean compare and branch if (not) zero; andWZR
/xZR
are hardcoded zero registers (32/64 bits respectively).Instructions such as
CBZ WZR <address>
don't make sense. ComparingWZR
with zero will always be true. So, it should have been compiled toB <address>
(a direct branch, not a conditional one). By the same token,CBNZ xZR <address>
should be anop
or not exists at all.The resulting code (although ugly) works ok. I am just curious about why such strange code is generated from VUnit and not from other VHDL sources. However, I don't know how to further debug this:
I'd appreciate any hint, even if it involves not being worth to dig further.
The text was updated successfully, but these errors were encountered: