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primes.mdl
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primes.mdl
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OutDataType "fixdt(1,16,0)"
OutScaling "[]"
RndMeth "Floor"
SaturateOnIntegerOverflow off
}
Block {
BlockType Scope
Name "Scope"
Ports [1]
Position [345, 54, 375, 86]
Location [656, 107, 980, 354]
Open on
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
TimeRange "5000"
YMin "0"
YMax "200"
SaveName "p7m"
DataFormat "Array"
}
Block {
BlockType UnitDelay
Name "Unit Delay"
Position [100, 123, 135, 157]
Orientation "left"
}
Block {
BlockType SubSystem
Name "isprime"
Ports [2, 2]
Position [70, 38, 135, 102]
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
MaskType "Is Prime"
MaskDescription "This block takes two inputs, the first is a pos"
"itive number n0 and the second is a reset condition. When the reset input is "
"one, then the block resets its internal state to n0, and it starts dividing n"
"0 for decreasing numbers, until either a factor is found or n0 is found to be"
" prime.\n\nWhen either of the two conditions is met, then the stop output is "
"set to 1, and the isprime output indicates whether n0 is prime or not. Note t"
"hat if stop==0, then a decision about the primeness of n0 has not been reache"
"d yet, and the value of the isprime output is not (yet) significant.\n\nThe e"
"quations of this block are essentially equivalent to the following ones:\nx(t"
"+1) = x(t)-sgn(mod(n0,x(t)-1))*sgn(x(t)-3)\ny(t) = sgn(mod(n0,x(t)-1))"
"\nwhere sgn(x)=ceil(x/(abs(x)+eps)) is the sign function, (that is +1 for x>"
"0, 0 for x=0, and -1 for x<0) and n0 is prime when y(inf)=1, while it is not"
" prime when y(inf)==0 "
MaskHelp "This block takes two inputs, the first is a pos"
"itive number n0 and the second is a reset condition. When the reset input is "
"one, then the block resets its internal state to n0, and it starts dividing n"
"0 for decreasing numbers, until either a factor is found or n0 is found to be"
" prime.\n<p>\nWhen either of the two conditions is met, then the stop output "
"is set to 1, and the isprime output indicates whether n0 is prime or not. Not"
"e that if stop==0, then a decision about the primeness of n0 has not been rea"
"ched yet, and the value of the isprime output is not (yet) significant.\n<p>"
"\nThe equations of this block are essentially equivalent to the following one"
"s: <br>\nx(t+1) = x(t)-sgn(mod(n0,x(t)-1))*sgn(x(t)-3) <br>\ny(t) = sgn(m"
"od(n0,x(t)-1)) <br>\nwhere sgn(x)=ceil(x/(abs(x)+eps)) is the sign function, "
" (that is +1 for x more than 0, 0 for x=0, and -1 for x less than 0) and n0 "
"is prime when y(inf)=1, while it is not prime when y(inf)==0"
MaskPromptString "Sample Time"
MaskStyleString "edit"
MaskTunableValueString "on"
MaskEnableString "on"
MaskVisibilityString "on"
MaskToolTipString "on"
MaskVariables "T=@1;"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskIconUnits "autoscale"
MaskValueString "1"
System {
Name "isprime"
Location [90, 463, 863, 759]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
Block {
BlockType Inport
Name "n0"
Position [230, 163, 260, 177]
Port "1"
IconDisplay "Port number"
OutDataType "fixdt(1,16,0)"
OutScaling "[]"
LatchInput off
}
Block {
BlockType Inport
Name "reset"
Position [230, 118, 260, 132]
Port "2"
IconDisplay "Port number"
OutDataType "fixdt(1,16,0)"
OutScaling "[]"
LatchInput off
}
Block {
BlockType Reference
Name "Compare\nTo Constant"
Ports [1, 1]
Position [600, 45, 630, 75]
ShowName off
SourceBlock "simulink/Logic and Bit\nOperations/Compare"
"\nTo Constant"
SourceType "Compare To Constant"
ShowPortLabels "on"
relop ">"
const "0"
LogicOutDataTypeMode "uint8"
ZeroCross "on"
}
Block {
BlockType Reference
Name "Compare\nTo Constant1"
Ports [1, 1]
Position [600, 105, 630, 135]
ShowName off
SourceBlock "simulink/Logic and Bit\nOperations/Compare"
"\nTo Constant"
SourceType "Compare To Constant"
ShowPortLabels "on"
relop "=="
const "0"
LogicOutDataTypeMode "boolean"
ZeroCross "on"
}
Block {
BlockType Constant
Name "Constant2"
Position [445, 249, 475, 271]
Orientation "left"
ShowName off
OutDataType "fixdt(1,16,0)"
OutScaling "[]"
}
Block {
BlockType Product
Name "Divide1"
Ports [2, 1]
Position [560, 91, 575, 149]
ShowName off
Inputs "**"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutDataType "fixdt(1,16,0)"
OutScaling "[]"
RndMeth "Floor"
SaturateOnIntegerOverflow off
}
Block {
BlockType Constant
Name "Initial \nCondition n2"
Position [485, 153, 515, 177]
NamePlacement "alternate"
ShowName off
Value "3"
OutDataType "fixdt(1,16,0)"
OutScaling "[]"
}
Block {
BlockType Math
Name "Math\nFunction"
Ports [2, 1]
Position [160, 221, 195, 274]
Orientation "left"
ShowName off
Operator "mod"
OutDataType "fixdt(1,16,0)"
OutScaling "[]"
}
Block {
BlockType Sum
Name "Sum1"
Ports [2, 1]
Position [400, 215, 420, 235]
Orientation "left"
ShowName off
IconShape "round"
Inputs "|+-"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutDataType "fixdt(1,16,0)"
OutScaling "[]"
SaturateOnIntegerOverflow off
}
Block {
BlockType Sum
Name "Sum2"
Ports [2, 1]
Position [520, 125, 540, 145]
ShowName off
IconShape "round"
Inputs "|+-"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutDataType "fixdt(1,16,0)"
OutScaling "[]"
SaturateOnIntegerOverflow off
}
Block {
BlockType Switch
Name "Switch"
Position [330, 185, 365, 235]
Orientation "left"
Threshold "0.5"
InputSameDT off
SaturateOnIntegerOverflow off
Port {
PortNumber 1
Name "x(t+1)"
PropagatedSignals "x(t)"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
ShowSigGenPortName on
}
}
Block {
BlockType SubSystem
Name "Unit Delay\nResettable\nExternal IC"
Ports [3, 1]
Position [330, 117, 365, 153]
ShowName off
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
MaskType "Unit Delay Resettable External Initial Cond"
"ition"
MaskDescription "Normally, the output is the signal u delaye"
"d by one sample period.\nWhen the reset signal R is true, the state and the o"
"utput are always set equal to the initial condition signal IC. This reset ac"
"tion is vectorized and supports scalar expansion."
MaskPromptString "Sample time:"
MaskStyleString "edit"
MaskTunableValueString "on"
MaskEnableString "on"
MaskVisibilityString "on"
MaskToolTipString "on"
MaskVariables "tsamp=@1;"
MaskDisplay "dpoly(1,[1 0],'z')"
MaskSelfModifiable on
MaskIconFrame on
MaskIconOpaque off
MaskIconRotate "none"
MaskIconUnits "normalized"
MaskValueString "T"
Port {
PortNumber 1
Name "x(t)"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
ShowSigGenPortName on
}
System {
Name "Unit Delay\nResettable\nExternal IC"
Location [247, 216, 1021, 535]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
Block {
BlockType Inport
Name "R"
Position [25, 143, 55, 157]
Port "1"
IconDisplay "Port number"
OutDataType "fixdt(1,16,0)"
OutScaling "[]"
LatchInput off
}
Block {
BlockType Inport
Name "IC"
Position [25, 108, 55, 122]
Port "2"
IconDisplay "Port number"
OutDataType "fixdt(1,16,0)"
OutScaling "[]"
LatchInput off
}
Block {
BlockType Inport
Name "u"
Position [25, 178, 55, 192]
Port "3"
IconDisplay "Port number"
OutDataType "fixdt(1,16,0)"
OutScaling "[]"
LatchInput off
}
Block {
BlockType Constant
Name "FixPt\nConstant"
Position [320, 90, 360, 130]
ShowName off
DisableCoverage on
Value "0"
OutDataType "fixdt(1,16,0)"
OutScaling "[]"
}
Block {
BlockType Reference
Name "FixPt\nData Type\nDuplicate1"
Ports [4]
Position [335, 220, 375, 300]
SourceBlock "simulink/Signal\nAttributes/Data Type\n"
"Duplicate"
SourceType "Data Type Duplicate"
NumInputPorts "4"
}
Block {
BlockType Logic
Name "FixPt\nLogical\nOperator"
Ports [2, 1]
Position [505, 57, 545, 128]
NamePlacement "alternate"
ShowName off
DisableCoverage on
Operator "OR"
AllPortsSameDT off
}
Block {
BlockType UnitDelay
Name "FixPt\nUnit Delay1"
Position [225, 130, 265, 170]
ShowName off
DisableCoverage on
X0 "0.0"
SampleTime "tsamp"
Port {
PortNumber 1
Name "Xold"
PropagatedSignals "Xnew"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
ShowSigGenPortName on
}
}
Block {
BlockType UnitDelay
Name "FixPt\nUnit Delay2"
Position [410, 90, 450, 130]
ShowName off
DisableCoverage on
X0 "1"
SampleTime "tsamp"
}
Block {
BlockType Switch
Name "Init"
Position [575, 14, 620, 176]
ShowName off
Criteria "u2 ~= 0"
InputSameDT off
SaturateOnIntegerOverflow off
ZeroCross off