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asmz.go
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asmz.go
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// Based on github.com/go-asm/go/cmd/obj/ppc64/asm9.go.
//
// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
// Portions Copyright © 1997-1999 Vita Nuova Limited
// Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
// Portions Copyright © 2004,2006 Bruce Ellis
// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
// Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
// Portions Copyright © 2009 The Go Authors. All rights reserved.
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
package s390x
import (
"fmt"
"log"
"math"
"sort"
"github.com/go-asm/go/cmd/obj"
"github.com/go-asm/go/cmd/objabi"
)
// ctxtz holds state while assembling a single function.
// Each function gets a fresh ctxtz.
// This allows for multiple functions to be safely concurrently assembled.
type ctxtz struct {
ctxt *obj.Link
newprog obj.ProgAlloc
cursym *obj.LSym
autosize int32
instoffset int64
pc int64
}
// instruction layout.
const (
funcAlign = 16
)
type Optab struct {
as obj.As // opcode
i uint8 // handler index
a1 uint8 // From
a2 uint8 // Reg
a3 uint8 // RestArgs[0]
a4 uint8 // RestArgs[1]
a5 uint8 // RestArgs[2]
a6 uint8 // To
}
var optab = []Optab{
// zero-length instructions
{i: 0, as: obj.ATEXT, a1: C_ADDR, a6: C_TEXTSIZE},
{i: 0, as: obj.ATEXT, a1: C_ADDR, a3: C_LCON, a6: C_TEXTSIZE},
{i: 0, as: obj.APCDATA, a1: C_LCON, a6: C_LCON},
{i: 0, as: obj.AFUNCDATA, a1: C_SCON, a6: C_ADDR},
{i: 0, as: obj.ANOP},
{i: 0, as: obj.ANOP, a1: C_SAUTO},
// move register
{i: 1, as: AMOVD, a1: C_REG, a6: C_REG},
{i: 1, as: AMOVB, a1: C_REG, a6: C_REG},
{i: 1, as: AMOVBZ, a1: C_REG, a6: C_REG},
{i: 1, as: AMOVW, a1: C_REG, a6: C_REG},
{i: 1, as: AMOVWZ, a1: C_REG, a6: C_REG},
{i: 1, as: AFMOVD, a1: C_FREG, a6: C_FREG},
{i: 1, as: AMOVDBR, a1: C_REG, a6: C_REG},
// load constant
{i: 26, as: AMOVD, a1: C_LACON, a6: C_REG},
{i: 26, as: AMOVW, a1: C_LACON, a6: C_REG},
{i: 26, as: AMOVWZ, a1: C_LACON, a6: C_REG},
{i: 3, as: AMOVD, a1: C_DCON, a6: C_REG},
{i: 3, as: AMOVW, a1: C_DCON, a6: C_REG},
{i: 3, as: AMOVWZ, a1: C_DCON, a6: C_REG},
{i: 3, as: AMOVB, a1: C_DCON, a6: C_REG},
{i: 3, as: AMOVBZ, a1: C_DCON, a6: C_REG},
// store constant
{i: 72, as: AMOVD, a1: C_SCON, a6: C_LAUTO},
{i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LAUTO},
{i: 72, as: AMOVW, a1: C_SCON, a6: C_LAUTO},
{i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LAUTO},
{i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LAUTO},
{i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LAUTO},
{i: 72, as: AMOVB, a1: C_SCON, a6: C_LAUTO},
{i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LAUTO},
{i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LAUTO},
{i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LAUTO},
{i: 72, as: AMOVD, a1: C_SCON, a6: C_LOREG},
{i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LOREG},
{i: 72, as: AMOVW, a1: C_SCON, a6: C_LOREG},
{i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LOREG},
{i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LOREG},
{i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LOREG},
{i: 72, as: AMOVB, a1: C_SCON, a6: C_LOREG},
{i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LOREG},
{i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LOREG},
{i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LOREG},
// store
{i: 35, as: AMOVD, a1: C_REG, a6: C_LAUTO},
{i: 35, as: AMOVW, a1: C_REG, a6: C_LAUTO},
{i: 35, as: AMOVWZ, a1: C_REG, a6: C_LAUTO},
{i: 35, as: AMOVBZ, a1: C_REG, a6: C_LAUTO},
{i: 35, as: AMOVB, a1: C_REG, a6: C_LAUTO},
{i: 35, as: AMOVDBR, a1: C_REG, a6: C_LAUTO},
{i: 35, as: AMOVHBR, a1: C_REG, a6: C_LAUTO},
{i: 35, as: AMOVD, a1: C_REG, a6: C_LOREG},
{i: 35, as: AMOVW, a1: C_REG, a6: C_LOREG},
{i: 35, as: AMOVWZ, a1: C_REG, a6: C_LOREG},
{i: 35, as: AMOVBZ, a1: C_REG, a6: C_LOREG},
{i: 35, as: AMOVB, a1: C_REG, a6: C_LOREG},
{i: 35, as: AMOVDBR, a1: C_REG, a6: C_LOREG},
{i: 35, as: AMOVHBR, a1: C_REG, a6: C_LOREG},
{i: 74, as: AMOVD, a1: C_REG, a6: C_ADDR},
{i: 74, as: AMOVW, a1: C_REG, a6: C_ADDR},
{i: 74, as: AMOVWZ, a1: C_REG, a6: C_ADDR},
{i: 74, as: AMOVBZ, a1: C_REG, a6: C_ADDR},
{i: 74, as: AMOVB, a1: C_REG, a6: C_ADDR},
// load
{i: 36, as: AMOVD, a1: C_LAUTO, a6: C_REG},
{i: 36, as: AMOVW, a1: C_LAUTO, a6: C_REG},
{i: 36, as: AMOVWZ, a1: C_LAUTO, a6: C_REG},
{i: 36, as: AMOVBZ, a1: C_LAUTO, a6: C_REG},
{i: 36, as: AMOVB, a1: C_LAUTO, a6: C_REG},
{i: 36, as: AMOVDBR, a1: C_LAUTO, a6: C_REG},
{i: 36, as: AMOVHBR, a1: C_LAUTO, a6: C_REG},
{i: 36, as: AMOVD, a1: C_LOREG, a6: C_REG},
{i: 36, as: AMOVW, a1: C_LOREG, a6: C_REG},
{i: 36, as: AMOVWZ, a1: C_LOREG, a6: C_REG},
{i: 36, as: AMOVBZ, a1: C_LOREG, a6: C_REG},
{i: 36, as: AMOVB, a1: C_LOREG, a6: C_REG},
{i: 36, as: AMOVDBR, a1: C_LOREG, a6: C_REG},
{i: 36, as: AMOVHBR, a1: C_LOREG, a6: C_REG},
{i: 75, as: AMOVD, a1: C_ADDR, a6: C_REG},
{i: 75, as: AMOVW, a1: C_ADDR, a6: C_REG},
{i: 75, as: AMOVWZ, a1: C_ADDR, a6: C_REG},
{i: 75, as: AMOVBZ, a1: C_ADDR, a6: C_REG},
{i: 75, as: AMOVB, a1: C_ADDR, a6: C_REG},
// interlocked load and op
{i: 99, as: ALAAG, a1: C_REG, a2: C_REG, a6: C_LOREG},
// integer arithmetic
{i: 2, as: AADD, a1: C_REG, a2: C_REG, a6: C_REG},
{i: 2, as: AADD, a1: C_REG, a6: C_REG},
{i: 22, as: AADD, a1: C_LCON, a2: C_REG, a6: C_REG},
{i: 22, as: AADD, a1: C_LCON, a6: C_REG},
{i: 12, as: AADD, a1: C_LOREG, a6: C_REG},
{i: 12, as: AADD, a1: C_LAUTO, a6: C_REG},
{i: 21, as: ASUB, a1: C_LCON, a2: C_REG, a6: C_REG},
{i: 21, as: ASUB, a1: C_LCON, a6: C_REG},
{i: 12, as: ASUB, a1: C_LOREG, a6: C_REG},
{i: 12, as: ASUB, a1: C_LAUTO, a6: C_REG},
{i: 4, as: AMULHD, a1: C_REG, a6: C_REG},
{i: 4, as: AMULHD, a1: C_REG, a2: C_REG, a6: C_REG},
{i: 62, as: AMLGR, a1: C_REG, a6: C_REG},
{i: 2, as: ADIVW, a1: C_REG, a2: C_REG, a6: C_REG},
{i: 2, as: ADIVW, a1: C_REG, a6: C_REG},
{i: 10, as: ASUB, a1: C_REG, a2: C_REG, a6: C_REG},
{i: 10, as: ASUB, a1: C_REG, a6: C_REG},
{i: 47, as: ANEG, a1: C_REG, a6: C_REG},
{i: 47, as: ANEG, a6: C_REG},
// integer logical
{i: 6, as: AAND, a1: C_REG, a2: C_REG, a6: C_REG},
{i: 6, as: AAND, a1: C_REG, a6: C_REG},
{i: 23, as: AAND, a1: C_LCON, a6: C_REG},
{i: 12, as: AAND, a1: C_LOREG, a6: C_REG},
{i: 12, as: AAND, a1: C_LAUTO, a6: C_REG},
{i: 6, as: AANDW, a1: C_REG, a2: C_REG, a6: C_REG},
{i: 6, as: AANDW, a1: C_REG, a6: C_REG},
{i: 24, as: AANDW, a1: C_LCON, a6: C_REG},
{i: 12, as: AANDW, a1: C_LOREG, a6: C_REG},
{i: 12, as: AANDW, a1: C_LAUTO, a6: C_REG},
{i: 7, as: ASLD, a1: C_REG, a6: C_REG},
{i: 7, as: ASLD, a1: C_REG, a2: C_REG, a6: C_REG},
{i: 7, as: ASLD, a1: C_SCON, a2: C_REG, a6: C_REG},
{i: 7, as: ASLD, a1: C_SCON, a6: C_REG},
{i: 13, as: ARNSBG, a1: C_SCON, a3: C_SCON, a4: C_SCON, a5: C_REG, a6: C_REG},
// compare and swap
{i: 79, as: ACSG, a1: C_REG, a2: C_REG, a6: C_SOREG},
// floating point
{i: 32, as: AFADD, a1: C_FREG, a6: C_FREG},
{i: 33, as: AFABS, a1: C_FREG, a6: C_FREG},
{i: 33, as: AFABS, a6: C_FREG},
{i: 34, as: AFMADD, a1: C_FREG, a2: C_FREG, a6: C_FREG},
{i: 32, as: AFMUL, a1: C_FREG, a6: C_FREG},
{i: 36, as: AFMOVD, a1: C_LAUTO, a6: C_FREG},
{i: 36, as: AFMOVD, a1: C_LOREG, a6: C_FREG},
{i: 75, as: AFMOVD, a1: C_ADDR, a6: C_FREG},
{i: 35, as: AFMOVD, a1: C_FREG, a6: C_LAUTO},
{i: 35, as: AFMOVD, a1: C_FREG, a6: C_LOREG},
{i: 74, as: AFMOVD, a1: C_FREG, a6: C_ADDR},
{i: 67, as: AFMOVD, a1: C_ZCON, a6: C_FREG},
{i: 81, as: ALDGR, a1: C_REG, a6: C_FREG},
{i: 81, as: ALGDR, a1: C_FREG, a6: C_REG},
{i: 82, as: ACEFBRA, a1: C_REG, a6: C_FREG},
{i: 83, as: ACFEBRA, a1: C_FREG, a6: C_REG},
{i: 48, as: AFIEBR, a1: C_SCON, a2: C_FREG, a6: C_FREG},
{i: 49, as: ACPSDR, a1: C_FREG, a2: C_FREG, a6: C_FREG},
{i: 50, as: ALTDBR, a1: C_FREG, a6: C_FREG},
{i: 51, as: ATCDB, a1: C_FREG, a6: C_SCON},
// load symbol address (plus offset)
{i: 19, as: AMOVD, a1: C_SYMADDR, a6: C_REG},
{i: 93, as: AMOVD, a1: C_GOTADDR, a6: C_REG},
{i: 94, as: AMOVD, a1: C_TLS_LE, a6: C_REG},
{i: 95, as: AMOVD, a1: C_TLS_IE, a6: C_REG},
// system call
{i: 5, as: ASYSCALL},
{i: 77, as: ASYSCALL, a1: C_SCON},
// branch
{i: 16, as: ABEQ, a6: C_SBRA},
{i: 16, as: ABRC, a1: C_SCON, a6: C_SBRA},
{i: 11, as: ABR, a6: C_LBRA},
{i: 16, as: ABC, a1: C_SCON, a2: C_REG, a6: C_LBRA},
{i: 18, as: ABR, a6: C_REG},
{i: 18, as: ABR, a1: C_REG, a6: C_REG},
{i: 15, as: ABR, a6: C_ZOREG},
{i: 15, as: ABC, a6: C_ZOREG},
// compare and branch
{i: 89, as: ACGRJ, a1: C_SCON, a2: C_REG, a3: C_REG, a6: C_SBRA},
{i: 89, as: ACMPBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA},
{i: 89, as: ACLGRJ, a1: C_SCON, a2: C_REG, a3: C_REG, a6: C_SBRA},
{i: 89, as: ACMPUBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA},
{i: 90, as: ACGIJ, a1: C_SCON, a2: C_REG, a3: C_ADDCON, a6: C_SBRA},
{i: 90, as: ACGIJ, a1: C_SCON, a2: C_REG, a3: C_SCON, a6: C_SBRA},
{i: 90, as: ACMPBEQ, a1: C_REG, a3: C_ADDCON, a6: C_SBRA},
{i: 90, as: ACMPBEQ, a1: C_REG, a3: C_SCON, a6: C_SBRA},
{i: 90, as: ACLGIJ, a1: C_SCON, a2: C_REG, a3: C_ADDCON, a6: C_SBRA},
{i: 90, as: ACMPUBEQ, a1: C_REG, a3: C_ANDCON, a6: C_SBRA},
// branch on count
{i: 41, as: ABRCT, a1: C_REG, a6: C_SBRA},
{i: 41, as: ABRCTG, a1: C_REG, a6: C_SBRA},
// move on condition
{i: 17, as: AMOVDEQ, a1: C_REG, a6: C_REG},
// load on condition
{i: 25, as: ALOCGR, a1: C_SCON, a2: C_REG, a6: C_REG},
// find leftmost one
{i: 8, as: AFLOGR, a1: C_REG, a6: C_REG},
// population count
{i: 9, as: APOPCNT, a1: C_REG, a6: C_REG},
// compare
{i: 70, as: ACMP, a1: C_REG, a6: C_REG},
{i: 71, as: ACMP, a1: C_REG, a6: C_LCON},
{i: 70, as: ACMPU, a1: C_REG, a6: C_REG},
{i: 71, as: ACMPU, a1: C_REG, a6: C_LCON},
{i: 70, as: AFCMPO, a1: C_FREG, a6: C_FREG},
{i: 70, as: AFCMPO, a1: C_FREG, a2: C_REG, a6: C_FREG},
// test under mask
{i: 91, as: ATMHH, a1: C_REG, a6: C_ANDCON},
// insert program mask
{i: 92, as: AIPM, a1: C_REG},
// set program mask
{i: 76, as: ASPM, a1: C_REG},
// 32-bit access registers
{i: 68, as: AMOVW, a1: C_AREG, a6: C_REG},
{i: 68, as: AMOVWZ, a1: C_AREG, a6: C_REG},
{i: 69, as: AMOVW, a1: C_REG, a6: C_AREG},
{i: 69, as: AMOVWZ, a1: C_REG, a6: C_AREG},
// macros
{i: 96, as: ACLEAR, a1: C_LCON, a6: C_LOREG},
{i: 96, as: ACLEAR, a1: C_LCON, a6: C_LAUTO},
// load/store multiple
{i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LOREG},
{i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LAUTO},
{i: 98, as: ALMG, a1: C_LOREG, a2: C_REG, a6: C_REG},
{i: 98, as: ALMG, a1: C_LAUTO, a2: C_REG, a6: C_REG},
// bytes
{i: 40, as: ABYTE, a1: C_SCON},
{i: 40, as: AWORD, a1: C_LCON},
{i: 31, as: ADWORD, a1: C_LCON},
{i: 31, as: ADWORD, a1: C_DCON},
// fast synchronization
{i: 80, as: ASYNC},
// store clock
{i: 88, as: ASTCK, a6: C_SAUTO},
{i: 88, as: ASTCK, a6: C_SOREG},
// storage and storage
{i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LOREG},
{i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LAUTO},
{i: 84, as: AMVC, a1: C_SCON, a3: C_LAUTO, a6: C_LAUTO},
// address
{i: 85, as: ALARL, a1: C_LCON, a6: C_REG},
{i: 85, as: ALARL, a1: C_SYMADDR, a6: C_REG},
{i: 86, as: ALA, a1: C_SOREG, a6: C_REG},
{i: 86, as: ALA, a1: C_SAUTO, a6: C_REG},
{i: 87, as: AEXRL, a1: C_SYMADDR, a6: C_REG},
// undefined (deliberate illegal instruction)
{i: 78, as: obj.AUNDEF},
// 2 byte no-operation
{i: 66, as: ANOPH},
// vector instructions
// VRX store
{i: 100, as: AVST, a1: C_VREG, a6: C_SOREG},
{i: 100, as: AVST, a1: C_VREG, a6: C_SAUTO},
{i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG},
{i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO},
// VRX load
{i: 101, as: AVL, a1: C_SOREG, a6: C_VREG},
{i: 101, as: AVL, a1: C_SAUTO, a6: C_VREG},
{i: 101, as: AVLEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG},
{i: 101, as: AVLEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG},
// VRV scatter
{i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG},
{i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO},
// VRV gather
{i: 103, as: AVGEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG},
{i: 103, as: AVGEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG},
// VRS element shift/rotate and load gr to/from vr element
{i: 104, as: AVESLG, a1: C_SCON, a2: C_VREG, a6: C_VREG},
{i: 104, as: AVESLG, a1: C_REG, a2: C_VREG, a6: C_VREG},
{i: 104, as: AVESLG, a1: C_SCON, a6: C_VREG},
{i: 104, as: AVESLG, a1: C_REG, a6: C_VREG},
{i: 104, as: AVLGVG, a1: C_SCON, a2: C_VREG, a6: C_REG},
{i: 104, as: AVLGVG, a1: C_REG, a2: C_VREG, a6: C_REG},
{i: 104, as: AVLVGG, a1: C_SCON, a2: C_REG, a6: C_VREG},
{i: 104, as: AVLVGG, a1: C_REG, a2: C_REG, a6: C_VREG},
// VRS store multiple
{i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SOREG},
{i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SAUTO},
// VRS load multiple
{i: 106, as: AVLM, a1: C_SOREG, a2: C_VREG, a6: C_VREG},
{i: 106, as: AVLM, a1: C_SAUTO, a2: C_VREG, a6: C_VREG},
// VRS store with length
{i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SOREG},
{i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SAUTO},
// VRS load with length
{i: 108, as: AVLL, a1: C_REG, a3: C_SOREG, a6: C_VREG},
{i: 108, as: AVLL, a1: C_REG, a3: C_SAUTO, a6: C_VREG},
// VRI-a
{i: 109, as: AVGBM, a1: C_ANDCON, a6: C_VREG},
{i: 109, as: AVZERO, a6: C_VREG},
{i: 109, as: AVREPIG, a1: C_ADDCON, a6: C_VREG},
{i: 109, as: AVREPIG, a1: C_SCON, a6: C_VREG},
{i: 109, as: AVLEIG, a1: C_SCON, a3: C_ADDCON, a6: C_VREG},
{i: 109, as: AVLEIG, a1: C_SCON, a3: C_SCON, a6: C_VREG},
// VRI-b generate mask
{i: 110, as: AVGMG, a1: C_SCON, a3: C_SCON, a6: C_VREG},
// VRI-c replicate
{i: 111, as: AVREPG, a1: C_UCON, a2: C_VREG, a6: C_VREG},
// VRI-d element rotate and insert under mask and
// shift left double by byte
{i: 112, as: AVERIMG, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
{i: 112, as: AVSLDB, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
// VRI-d fp test data class immediate
{i: 113, as: AVFTCIDB, a1: C_SCON, a2: C_VREG, a6: C_VREG},
// VRR-a load reg
{i: 114, as: AVLR, a1: C_VREG, a6: C_VREG},
// VRR-a compare
{i: 115, as: AVECG, a1: C_VREG, a6: C_VREG},
// VRR-b
{i: 117, as: AVCEQG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
{i: 117, as: AVFAEF, a1: C_VREG, a2: C_VREG, a6: C_VREG},
{i: 117, as: AVPKSG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
// VRR-c
{i: 118, as: AVAQ, a1: C_VREG, a2: C_VREG, a6: C_VREG},
{i: 118, as: AVAQ, a1: C_VREG, a6: C_VREG},
{i: 118, as: AVNOT, a1: C_VREG, a6: C_VREG},
{i: 123, as: AVPDI, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
// VRR-c shifts
{i: 119, as: AVERLLVG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
{i: 119, as: AVERLLVG, a1: C_VREG, a6: C_VREG},
// VRR-d
{i: 120, as: AVACQ, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG},
// VRR-e
{i: 121, as: AVSEL, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG},
// VRR-f
{i: 122, as: AVLVGP, a1: C_REG, a2: C_REG, a6: C_VREG},
}
var oprange [ALAST & obj.AMask][]Optab
var xcmp [C_NCLASS][C_NCLASS]bool
func spanz(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
if ctxt.Retpoline {
ctxt.Diag("-spectre=ret not supported on s390x")
ctxt.Retpoline = false // don't keep printing
}
p := cursym.Func().Text
if p == nil || p.Link == nil { // handle external functions and ELF section symbols
return
}
if oprange[AORW&obj.AMask] == nil {
ctxt.Diag("s390x ops not initialized, call s390x.buildop first")
}
c := ctxtz{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)}
buffer := make([]byte, 0)
changed := true
loop := 0
nrelocs0 := len(c.cursym.R)
for changed {
if loop > 100 {
c.ctxt.Diag("stuck in spanz loop")
break
}
changed = false
buffer = buffer[:0]
for i := range c.cursym.R[nrelocs0:] {
c.cursym.R[nrelocs0+i] = obj.Reloc{}
}
c.cursym.R = c.cursym.R[:nrelocs0] // preserve marker relocations generated by the compiler
for p := c.cursym.Func().Text; p != nil; p = p.Link {
pc := int64(len(buffer))
if pc != p.Pc {
changed = true
}
p.Pc = pc
c.pc = p.Pc
c.asmout(p, &buffer)
if pc == int64(len(buffer)) {
switch p.As {
case obj.ANOP, obj.AFUNCDATA, obj.APCDATA, obj.ATEXT:
// ok
default:
c.ctxt.Diag("zero-width instruction\n%v", p)
}
}
}
loop++
}
c.cursym.Size = int64(len(buffer))
if c.cursym.Size%funcAlign != 0 {
c.cursym.Size += funcAlign - (c.cursym.Size % funcAlign)
}
c.cursym.Grow(c.cursym.Size)
copy(c.cursym.P, buffer)
// Mark nonpreemptible instruction sequences.
// We use REGTMP as a scratch register during call injection,
// so instruction sequences that use REGTMP are unsafe to
// preempt asynchronously.
obj.MarkUnsafePoints(c.ctxt, c.cursym.Func().Text, c.newprog, c.isUnsafePoint, nil)
}
// Return whether p is an unsafe point.
func (c *ctxtz) isUnsafePoint(p *obj.Prog) bool {
if p.From.Reg == REGTMP || p.To.Reg == REGTMP || p.Reg == REGTMP {
return true
}
for _, a := range p.RestArgs {
if a.Reg == REGTMP {
return true
}
}
return p.Mark&USETMP != 0
}
func isint32(v int64) bool {
return int64(int32(v)) == v
}
func isuint32(v uint64) bool {
return uint64(uint32(v)) == v
}
func (c *ctxtz) aclass(a *obj.Addr) int {
switch a.Type {
case obj.TYPE_NONE:
return C_NONE
case obj.TYPE_REG:
if REG_R0 <= a.Reg && a.Reg <= REG_R15 {
return C_REG
}
if REG_F0 <= a.Reg && a.Reg <= REG_F15 {
return C_FREG
}
if REG_AR0 <= a.Reg && a.Reg <= REG_AR15 {
return C_AREG
}
if REG_V0 <= a.Reg && a.Reg <= REG_V31 {
return C_VREG
}
return C_GOK
case obj.TYPE_MEM:
switch a.Name {
case obj.NAME_EXTERN,
obj.NAME_STATIC:
if a.Sym == nil {
// must have a symbol
break
}
c.instoffset = a.Offset
if a.Sym.Type == objabi.STLSBSS {
if c.ctxt.Flag_shared {
return C_TLS_IE // initial exec model
}
return C_TLS_LE // local exec model
}
return C_ADDR
case obj.NAME_GOTREF:
return C_GOTADDR
case obj.NAME_AUTO:
if a.Reg == REGSP {
// unset base register for better printing, since
// a.Offset is still relative to pseudo-SP.
a.Reg = obj.REG_NONE
}
c.instoffset = int64(c.autosize) + a.Offset
if c.instoffset >= -BIG && c.instoffset < BIG {
return C_SAUTO
}
return C_LAUTO
case obj.NAME_PARAM:
if a.Reg == REGSP {
// unset base register for better printing, since
// a.Offset is still relative to pseudo-FP.
a.Reg = obj.REG_NONE
}
c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
if c.instoffset >= -BIG && c.instoffset < BIG {
return C_SAUTO
}
return C_LAUTO
case obj.NAME_NONE:
c.instoffset = a.Offset
if c.instoffset == 0 {
return C_ZOREG
}
if c.instoffset >= -BIG && c.instoffset < BIG {
return C_SOREG
}
return C_LOREG
}
return C_GOK
case obj.TYPE_TEXTSIZE:
return C_TEXTSIZE
case obj.TYPE_FCONST:
if f64, ok := a.Val.(float64); ok && math.Float64bits(f64) == 0 {
return C_ZCON
}
c.ctxt.Diag("cannot handle the floating point constant %v", a.Val)
case obj.TYPE_CONST,
obj.TYPE_ADDR:
switch a.Name {
case obj.NAME_NONE:
c.instoffset = a.Offset
if a.Reg != 0 {
if -BIG <= c.instoffset && c.instoffset <= BIG {
return C_SACON
}
if isint32(c.instoffset) {
return C_LACON
}
return C_DACON
}
case obj.NAME_EXTERN,
obj.NAME_STATIC:
s := a.Sym
if s == nil {
return C_GOK
}
c.instoffset = a.Offset
return C_SYMADDR
case obj.NAME_AUTO:
if a.Reg == REGSP {
// unset base register for better printing, since
// a.Offset is still relative to pseudo-SP.
a.Reg = obj.REG_NONE
}
c.instoffset = int64(c.autosize) + a.Offset
if c.instoffset >= -BIG && c.instoffset < BIG {
return C_SACON
}
return C_LACON
case obj.NAME_PARAM:
if a.Reg == REGSP {
// unset base register for better printing, since
// a.Offset is still relative to pseudo-FP.
a.Reg = obj.REG_NONE
}
c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
if c.instoffset >= -BIG && c.instoffset < BIG {
return C_SACON
}
return C_LACON
default:
return C_GOK
}
if c.instoffset == 0 {
return C_ZCON
}
if c.instoffset >= 0 {
if c.instoffset <= 0x7fff {
return C_SCON
}
if c.instoffset <= 0xffff {
return C_ANDCON
}
if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) { /* && (instoffset & (1<<31)) == 0) */
return C_UCON
}
if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) {
return C_LCON
}
return C_DCON
}
if c.instoffset >= -0x8000 {
return C_ADDCON
}
if c.instoffset&0xffff == 0 && isint32(c.instoffset) {
return C_UCON
}
if isint32(c.instoffset) {
return C_LCON
}
return C_DCON
case obj.TYPE_BRANCH:
return C_SBRA
}
return C_GOK
}
func (c *ctxtz) oplook(p *obj.Prog) *Optab {
// Return cached optab entry if available.
if p.Optab != 0 {
return &optab[p.Optab-1]
}
if len(p.RestArgs) > 3 {
c.ctxt.Diag("too many RestArgs: got %v, maximum is 3\n", len(p.RestArgs))
return nil
}
// Initialize classes for all arguments.
p.From.Class = int8(c.aclass(&p.From) + 1)
p.To.Class = int8(c.aclass(&p.To) + 1)
for i := range p.RestArgs {
p.RestArgs[i].Addr.Class = int8(c.aclass(&p.RestArgs[i].Addr) + 1)
}
// Mirrors the argument list in Optab.
args := [...]int8{
p.From.Class - 1,
C_NONE, // p.Reg
C_NONE, // p.RestArgs[0]
C_NONE, // p.RestArgs[1]
C_NONE, // p.RestArgs[2]
p.To.Class - 1,
}
// Fill in argument class for p.Reg.
switch {
case REG_R0 <= p.Reg && p.Reg <= REG_R15:
args[1] = C_REG
case REG_V0 <= p.Reg && p.Reg <= REG_V31:
args[1] = C_VREG
case REG_F0 <= p.Reg && p.Reg <= REG_F15:
args[1] = C_FREG
case REG_AR0 <= p.Reg && p.Reg <= REG_AR15:
args[1] = C_AREG
}
// Fill in argument classes for p.RestArgs.
for i, a := range p.RestArgs {
args[2+i] = a.Class - 1
}
// Lookup op in optab.
ops := oprange[p.As&obj.AMask]
cmp := [len(args)]*[C_NCLASS]bool{}
for i := range cmp {
cmp[i] = &xcmp[args[i]]
}
for i := range ops {
op := &ops[i]
if cmp[0][op.a1] && cmp[1][op.a2] &&
cmp[2][op.a3] && cmp[3][op.a4] &&
cmp[4][op.a5] && cmp[5][op.a6] {
p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
return op
}
}
// Cannot find a case; abort.
s := ""
for _, a := range args {
s += fmt.Sprintf(" %v", DRconv(int(a)))
}
c.ctxt.Diag("illegal combination %v%v\n", p.As, s)
c.ctxt.Diag("prog: %v\n", p)
return nil
}
func cmp(a int, b int) bool {
if a == b {
return true
}
switch a {
case C_DCON:
if b == C_LCON {
return true
}
fallthrough
case C_LCON:
if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON {
return true
}
case C_ADDCON:
if b == C_ZCON || b == C_SCON {
return true
}
case C_ANDCON:
if b == C_ZCON || b == C_SCON {
return true
}
case C_UCON:
if b == C_ZCON || b == C_SCON {
return true
}
case C_SCON:
if b == C_ZCON {
return true
}
case C_LACON:
if b == C_SACON {
return true
}
case C_LBRA:
if b == C_SBRA {
return true
}
case C_LAUTO:
if b == C_SAUTO {
return true
}
case C_LOREG:
if b == C_ZOREG || b == C_SOREG {
return true
}
case C_SOREG:
if b == C_ZOREG {
return true
}
case C_ANY:
return true
}
return false
}
type ocmp []Optab
func (x ocmp) Len() int {
return len(x)
}
func (x ocmp) Swap(i, j int) {
x[i], x[j] = x[j], x[i]
}
func (x ocmp) Less(i, j int) bool {
p1 := &x[i]
p2 := &x[j]
n := int(p1.as) - int(p2.as)
if n != 0 {
return n < 0
}
n = int(p1.a1) - int(p2.a1)
if n != 0 {
return n < 0
}
n = int(p1.a2) - int(p2.a2)
if n != 0 {
return n < 0
}
n = int(p1.a3) - int(p2.a3)
if n != 0 {
return n < 0
}
n = int(p1.a4) - int(p2.a4)
if n != 0 {
return n < 0
}
return false
}
func opset(a, b obj.As) {
oprange[a&obj.AMask] = oprange[b&obj.AMask]
}
func buildop(ctxt *obj.Link) {
if oprange[AORW&obj.AMask] != nil {
// Already initialized; stop now.
// This happens in the cmd/asm tests,
// each of which re-initializes the arch.
return
}
for i := 0; i < C_NCLASS; i++ {
for n := 0; n < C_NCLASS; n++ {
if cmp(n, i) {
xcmp[i][n] = true
}
}
}
sort.Sort(ocmp(optab))
for i := 0; i < len(optab); i++ {
r := optab[i].as
start := i
for ; i+1 < len(optab); i++ {
if optab[i+1].as != r {
break
}
}
oprange[r&obj.AMask] = optab[start : i+1]
// opset() aliases optab ranges for similar instructions, to reduce the number of optabs in the array.
// oprange[] is used by oplook() to find the Optab entry that applies to a given Prog.
switch r {
case AADD:
opset(AADDC, r)
opset(AADDW, r)
opset(AADDE, r)
opset(AMULLD, r)
opset(AMULLW, r)
case ADIVW:
opset(ADIVD, r)
opset(ADIVDU, r)
opset(ADIVWU, r)
opset(AMODD, r)
opset(AMODDU, r)
opset(AMODW, r)
opset(AMODWU, r)
case AMULHD:
opset(AMULHDU, r)
case AMOVBZ:
opset(AMOVH, r)
opset(AMOVHZ, r)
case ALA:
opset(ALAY, r)
case AMVC:
opset(AMVCIN, r)
opset(ACLC, r)
opset(AXC, r)
opset(AOC, r)
opset(ANC, r)
case ASTCK:
opset(ASTCKC, r)
opset(ASTCKE, r)
opset(ASTCKF, r)
case ALAAG:
opset(ALAA, r)
opset(ALAAL, r)
opset(ALAALG, r)
opset(ALAN, r)
opset(ALANG, r)
opset(ALAX, r)
opset(ALAXG, r)
opset(ALAO, r)
opset(ALAOG, r)
case ASTMG:
opset(ASTMY, r)
case ALMG:
opset(ALMY, r)
case ABEQ:
opset(ABGE, r)
opset(ABGT, r)
opset(ABLE, r)
opset(ABLT, r)
opset(ABNE, r)
opset(ABVC, r)
opset(ABVS, r)
opset(ABLEU, r)
opset(ABLTU, r)
case ABR:
opset(ABL, r)
case ABC:
opset(ABCL, r)
case AFABS:
opset(AFNABS, r)
opset(ALPDFR, r)
opset(ALNDFR, r)
opset(AFNEG, r)
opset(AFNEGS, r)
opset(ALEDBR, r)
opset(ALDEBR, r)
opset(AFSQRT, r)
opset(AFSQRTS, r)
case AFADD:
opset(AFADDS, r)
opset(AFDIV, r)
opset(AFDIVS, r)
opset(AFSUB, r)
opset(AFSUBS, r)
case AFMADD:
opset(AFMADDS, r)
opset(AFMSUB, r)
opset(AFMSUBS, r)
case AFMUL:
opset(AFMULS, r)
case AFCMPO:
opset(AFCMPU, r)
opset(ACEBR, r)
case AAND:
opset(AOR, r)
opset(AXOR, r)
case AANDW:
opset(AORW, r)
opset(AXORW, r)