verilog model of cells uses compiler directives not implemented in yosys

[chaufe]

@proppy

Expected Behavior

The verilog model should only use language constructs supported by the tool chain, i.e. only compiler directives implemented in the synthesis tool yosys.

Actual Behavior

The current verilog module uses the compiler directive `suppress_faults that is not implemented in yosys.
In consequence, when loading the verilog model into yosys, i.e. via the openlane variable VERILOG_FILES_BLACKBOX,
yosys will stop with error:

5. Executing Verilog-2005 frontend:

/content/eda/share/pdk/gf180mcuC/libs.ref/gf180mcu_fd_io/verilog/gf180mcu_fd_io.v
/content/eda/share/pdk/gf180mcuC/libs.ref/gf180mcu_fd_io/verilog/gf180mcu_fd_io.v:17: ERROR: Unimplemented compiler directive or undefined macro `suppress_faults.
child process exited abnormally

Steps to Reproduce the Problem

1. within config.tcl,

set ::env(VERILOG_FILES_BLACKBOX)   /content/eda/share/pdk/gf180mcuC/libs.ref/gf180mcu_fd_io/verilog/gf180mcu_fd_io.v

2. run flow.tcl -to synthesis

Specifications

• Version: yosys 0.26+53
• Platform: colab using https://github.com/proppy/conda-eda/releases/download/v0.0-1452-g75fd8b9/digital.gf180mcuc-0-Linux-x86_64.sh