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Add verilog test benches for each of the standard cells. #4

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mithro opened this issue Jul 20, 2022 · 0 comments

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mithro commented Jul 20, 2022

Each of the standard cell should have a Verilog test bench which tests the functionality.

mithro mentioned this issue

Set up some type of CI for this repository google/gf180mcu-pdk#4

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mithro mentioned this issue

Adding missing user defined primitives. #27

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