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gameboy.c
executable file
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gameboy.c
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/**********
gameboy.c
--------------------
GameBoy emulator
Credits: Greg Tourville
*/
#include "gameboy.h"
#include "sound.h"
#define printf(...) ;
// CART /////////////////////////////
u8* ROM;
u8* CRAM;
u32 ROM_SIZE;
u32 CRAM_SIZE;
// memory banks and other things
u16 rom_bank;
u16 rom_banks;
u8 wram_bank;
u8 vram_bank;
u8 cram_bank;
u8 cram_banks;
u8 cram_enable;
u8 cram_mode;
// cart mbc / memory info
u8 CART_MBC[] =
{
0, 1, 1, 1,-1, 2, 2,-1, 0, 0,-1, 0, 0, 0,-1, 3,
3, 3, 3, 3,-1,-1,-1,-1,-1, 5, 5, 5, 5, 5, 5, 0
};
u8 CART_RAM[] =
{
0, 0, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0,
1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0
};
u16 NUM_ROM_BANKS[] =
{
2, 4, 8,16,32,64,128, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0,72,80,96, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
u8 NUM_RAM_BANKS[] = {0, 1, 1, 4, 16};
// GB ///////////////////////////////
u8 gb_bios_enable = 1;
u8 opt_use_gb_bios = 1;
u8 gb_halt = 0;
u8 gb_ime = 1;
u8 gb_keys = 0;
u8 gb_mbc = 0;
u8 gb_cram = 0;
u8 gb_frame = 0;
u8 gb_rtc[5];
u8 lcd_mode = 0;
// CGB
u8 cgb_enable = 0;
u8 cgb_double = 0;
// CPU
u8 OP;
u8 inst_cycles;
// screen
u8 gb_fb[LCD_HEIGHT][LCD_WIDTH];
u16 cgb_fb[LCD_HEIGHT][LCD_WIDTH];
// char debug_msg[0x100];
// MEMORY ///////////////////////////
u8 WRAM[WRAM_SIZE];
u8 VRAM[VRAM_SIZE];
u8 HRAM[HRAM_SIZE];
u8 OAM[OAM_SIZE];
// TIMERS
u32 cpu_count;
u32 lcd_count;
u32 audio_count;
u32 div_count;
u32 tima_count;
u8 tac_enable;
u8 tac_rate;
const u32 TAC_CYCLES[4] = {1024, 16, 64, 256};
// PALETTES
u8 BGP[4];
u8 OBJP[8];
// CGB PALETTES
u16 BCPD[4*8];
u16 OCPD[4*8];
// 8-bit convenience
u8* R_BCPD = (u8*)BCPD;
u8* R_OCPD = (u8*)OCPD;
// REGISTERS
u8 R_P1; u8 R_SB; u8 R_SC; u8 R_DIV;
u8 R_TIMA; u8 R_TMA; u8 R_TAC; u8 R_IF;
u8 R_LCDC; u8 R_STAT;
u8 R_SCY; u8 R_SCX; u8 R_LY; u8 R_LYC;
u8 R_DMA; u8 R_BGP; u8 R_OBP0; u8 R_OBP1;
u8 R_WY; u8 R_WX; u8 R_IE;
// CGB REGISTERS
u8 R_HDMA; u8 R_BCPS; u8 R_OCPS; u8 R_KEY1;
u16 R_HDMAS;
u16 R_HDMAD;
// Read
u8 READ(u16 addr)
{
switch ((addr >> 12) & 0xF)
{
case 0x0:
#ifdef DMG_BIOS_ENABLE
if (gb_bios_enable && addr < 0x100)
{
return DMG_BIOS[addr];
}
#endif
case 0x1:
case 0x2:
case 0x3:
return ROM[addr];
case 0x4:
case 0x5:
case 0x6:
case 0x7:
if (gb_mbc == 1 && cram_mode)
return ROM[addr + ((rom_bank & 0x1F) - 1)*ROM_BANK_SIZE];
else
return ROM[addr + (rom_bank-1)*ROM_BANK_SIZE];
case 0x8:
case 0x9:
return VRAM[addr - VRAM_ADDR];
//return VRAM[addr - VRAM_ADDR + vram_bank*VRAM_BANK_SIZE];
case 0xA:
case 0xB:
if (gb_cram && cram_enable)
{
if (gb_mbc == 3 && cram_bank >= 0x08)
return gb_rtc[cram_bank - 0x08];
else if ((cram_mode || gb_mbc != 1) && cram_bank < cram_banks)
return CRAM[addr - CART_RAM_ADDR + cram_bank*CRAM_BANK_SIZE];
else
return CRAM[addr - CART_RAM_ADDR];
}
return 0;
case 0xC:
return WRAM[addr - WRAM_0_ADDR];
case 0xD:
return WRAM[addr - WRAM_1_ADDR + wram_bank*WRAM_BANK_SIZE];
case 0xE:
return WRAM[addr - ECHO_ADDR];
case 0xF:
if (addr < OAM_ADDR)
return WRAM[addr - ECHO_ADDR + (wram_bank-1)*WRAM_BANK_SIZE];
if (addr < UNUSED_ADDR)
return OAM[addr - OAM_ADDR];
if (addr < IO_ADDR)
return 0; // unused
switch (addr & 0xFF) // 0xFF00 .. 0xFFFF
{
// I/O Registers
case 0x00:
return 0xC0 | R_P1;
case 0x01: return R_SB;
case 0x02: return R_SC;
// Timer Registers
case 0x04: return R_DIV;
case 0x05: return R_TIMA;
case 0x06: return R_TMA;
case 0x07: return R_TAC;
// Interrupt Flag Register
case 0x0F: return R_IF;
// Sound Registers
case 0x10: case 0x11: case 0x12: case 0x13:
case 0x14: case 0x15: case 0x16: case 0x17:
case 0x18: case 0x19: case 0x1A: case 0x1B:
case 0x1C: case 0x1D: case 0x1E: case 0x1F:
case 0x20: case 0x21: case 0x22: case 0x23:
case 0x24: case 0x25: case 0x26:/*case 0x27:
case 0x28: case 0x29: case 0x2A: case 0x2B:
case 0x2C: case 0x2D: case 0x2E: case 0x2F:*/
case 0x30: case 0x31: case 0x32: case 0x33:
case 0x34: case 0x35: case 0x36: case 0x37:
case 0x38: case 0x39: case 0x3A: case 0x3B:
case 0x3C: case 0x3D: case 0x3E: case 0x3F:
return AUDIO_READ(addr & 0xFF);
// LCD Registers
case 0x40: return R_LCDC;
case 0x41:
return (R_STAT & STAT_USER_BITS) |
(R_LCDC & LCDC_ENABLE ? lcd_mode : LCD_VBLANK);
case 0x42: return R_SCY;
case 0x43: return R_SCX;
case 0x44: return R_LY;
case 0x45: return R_LYC;
// CGB speed setting
case 0x4D: return (cgb_double << 7) | (R_KEY1 & 0x01);
// CGB vram bank
case 0x4F: return vram_bank;
// DMA Register
case 0x46: return R_DMA;
// Drawing Registers
case 0x47: return R_BGP;
case 0x48: return R_OBP0;
case 0x49: return R_OBP1;
case 0x4A: return R_WY;
case 0x4B: return R_WX;
// CGB HDMA
case 0x51: return (R_HDMAS >> 8) & 0xFF;
case 0x52: return (R_HDMAS & 0xFF);
case 0x53: return (R_HDMAD >> 8) & 0xFF;
case 0x54: return (R_HDMAD & 0xFF);
case 0x55: return R_HDMA;
// CGB Palette Registers
case 0x68: return R_BCPS;
case 0x69: return R_BCPD[R_BCPS & PAL_INDEX];
case 0x6A: return R_OCPS;
case 0x6B: return R_OCPD[R_OCPS & PAL_INDEX];
// CGB wram bank
case 0x70: return wram_bank;
// Interrupt Enable Register
case 0xFF: return R_IE;
// High RAM
default:
if (addr >= HRAM_ADDR)
{
return HRAM[addr - HRAM_ADDR];
}
}
}
return 0;
}
// Write
void WRITE(u16 addr, u8 val)
{
switch (addr >> 12)
{
case 0x0:
case 0x1:
if (gb_mbc == 2 && addr & 0x10)
return;
else if (gb_mbc > 0 && gb_cram)
cram_enable = ((val & 0x0F) == 0x0A);
return;
case 0x2:
if (gb_mbc == 5)
{
rom_bank = (rom_bank & 0x100) | val;
rom_bank = rom_bank % rom_banks;
return;
}
case 0x3:
if (gb_mbc == 1)
{
//rom_bank = val & 0x7;
rom_bank = (val & 0x1F) | (rom_bank & 0x60);
if ((rom_bank & 0x1F) == 0x00)
rom_bank++;
}
else if (gb_mbc == 2 && addr & 0x10)
{
rom_bank = val & 0x0F;
if (!rom_bank)
rom_bank++;
}
else if (gb_mbc == 3)
{
rom_bank = val & 0x7F;
if (!rom_bank)
rom_bank++;
}
else if (gb_mbc == 5)
rom_bank = (val & 0x01) << 8 | (rom_bank & 0xFF);
rom_bank = rom_bank % rom_banks;
return;
case 0x4:
case 0x5:
if (gb_mbc == 1)
{
cram_bank = (val & 3);
rom_bank = ((val & 3) << 5) | (rom_bank & 0x1F);
rom_bank = rom_bank % rom_banks;
}
else if (gb_mbc == 3)
cram_bank = val;
else if (gb_mbc == 5)
cram_bank = (val & 0x0F);
return;
case 0x6:
case 0x7:
//if (gb_mbc == 1 && gb_cram)
cram_mode = (val & 1);
return;
case 0x8:
case 0x9:
VRAM[addr - VRAM_ADDR + vram_bank*VRAM_BANK_SIZE] = val;
return;
case 0xA:
case 0xB:
if (gb_cram && cram_enable)
{
if (gb_mbc == 3 && cram_bank >= 0x08)
gb_rtc[cram_bank - 0x08] = val;
//else if ((cram_mode || gb_mbc != 1) && cram_bank < cram_banks)
else if (cram_mode && cram_bank < cram_banks)
CRAM[addr - CART_RAM_ADDR + cram_bank*CRAM_BANK_SIZE] = val;
else
CRAM[addr - CART_RAM_ADDR] = val;
}
return;
case 0xC:
WRAM[addr - WRAM_0_ADDR] = val;
return;
case 0xD:
WRAM[addr - WRAM_1_ADDR + wram_bank*WRAM_BANK_SIZE] = val;
return;
case 0xE:
WRAM[addr - ECHO_ADDR] = val;
return;
case 0xF:
if (addr < OAM_ADDR)
{
WRAM[addr - ECHO_ADDR + (wram_bank-1)*WRAM_BANK_SIZE] = val;
return;
}
if (addr < UNUSED_ADDR)
{
OAM[addr - OAM_ADDR] = val;
return;
}
if (addr < IO_ADDR)
return; // unused
switch (addr & 0xFF) // 0xFF00 .. 0xFFFF
{
// I/O Registers
case 0x00: // Controls
R_P1 = val & 0x30;
UpdateP1();
return;
case 0x01: R_SB = val; return;
case 0x02: R_SC = val; return;
// Timer Registers
case 0x04: R_DIV = 0x00; return;
case 0x05: R_TIMA = val; return;
case 0x06: R_TMA = val; return;
case 0x07:
R_TAC = val;
tac_enable = R_TAC & TAC_ENABLE;
tac_rate = R_TAC & TAC_RATE;
return;
// Interrupt Flag Register
case 0x0F:
R_IF = val;
return;
// Sound Registers
case 0x10: case 0x11: case 0x12: case 0x13:
case 0x14: case 0x15: case 0x16: case 0x17:
case 0x18: case 0x19: case 0x1A: case 0x1B:
case 0x1C: case 0x1D: case 0x1E: case 0x1F:
case 0x20: case 0x21: case 0x22: case 0x23:
case 0x24: case 0x25: case 0x26:/*case 0x27:
case 0x28: case 0x29: case 0x2A: case 0x2B:
case 0x2C: case 0x2D: case 0x2E: case 0x2F:*/
case 0x30: case 0x31: case 0x32: case 0x33:
case 0x34: case 0x35: case 0x36: case 0x37:
case 0x38: case 0x39: case 0x3A: case 0x3B:
case 0x3C: case 0x3D: case 0x3E: case 0x3F:
AUDIO_WRITE(addr & 0xFF, val);
return;
// LCD Registers
case 0x40: R_LCDC = val; return;
case 0x41: R_STAT = val; return;
case 0x42: R_SCY = val; return;
case 0x43: R_SCX = val; return;
case 0x44: R_LY = val; return;
case 0x45: R_LYC = val; return;
// DMA Register
case 0x46:
{
u8 offset;
R_DMA = (val % 0xF1);
for (offset = 0; offset < OAM_SIZE; offset++)
{
OAM[offset] = READ((R_DMA << 8) + offset);
}
return;
}
// DMG Palette Registers
case 0x47:
R_BGP = val;
BGP[0] = (R_BGP & 0x03);
BGP[1] = (R_BGP >> 2) & 0x03;
BGP[2] = (R_BGP >> 4) & 0x03;
BGP[3] = (R_BGP >> 6) & 0x03;
return;
case 0x48:
R_OBP0 = val;
OBJP[0] = (R_OBP0 & 0x03);
OBJP[1] = (R_OBP0 >> 2) & 0x03;
OBJP[2] = (R_OBP0 >> 4) & 0x03;
OBJP[3] = (R_OBP0 >> 6) & 0x03;
return;
case 0x49:
R_OBP1 = val;
OBJP[4] = (R_OBP1 & 0x03);
OBJP[5] = (R_OBP1 >> 2) & 0x03;
OBJP[6] = (R_OBP1 >> 4) & 0x03;
OBJP[7] = (R_OBP1 >> 6) & 0x03;
return;
// Window position
case 0x4A: R_WY = val; return;
case 0x4B: R_WX = val; return;
// CGB speed setting
case 0x4D:
R_KEY1 = val & 0x1;
return;
// CGB VRAM bank
case 0x4F:
if (cgb_enable)
{
vram_bank = val & 0x1;
}
return;
// turn off boot rom
case 0x50: gb_bios_enable = 0; return;
// CGB HDMA
case 0x51:
printf("HDMA\n");
if (cgb_enable && (R_HDMA & HDMA_OFF))
R_HDMAS = (val << 8) | (R_HDMAS & 0x00F0);
return;
case 0x52:
printf("HDMA\n");
if (cgb_enable && (R_HDMA & HDMA_OFF))
R_HDMAS = (R_HDMAS & 0xFF00) | (val & 0x00F0);
return;
case 0x53:
printf("HDMA\n");
if (cgb_enable && (R_HDMA & HDMA_OFF))
R_HDMAD = 0x8000 | ((val << 8) & 0x1F00) | (R_HDMAD & 0x00F0);
return;
case 0x54:
printf("HDMA\n");
if (cgb_enable && (R_HDMA & HDMA_OFF))
R_HDMAD = 0x8000 | (R_HDMAD & 0x1F00) | (val & 0x00F0);
return;
case 0x55:
printf("HDMA\n");
if (val & HDMA_HBLANK)
{
// set length to copy
R_HDMA = val & HDMA_LENGTH;
}
else
{
if (R_HDMA & HDMA_OFF)
{
u16 i;
// blocking DMA
for (i = 0; i < (val + 1) * 0x10; i++)
WRITE(R_HDMAD+i, READ(R_HDMAS+i));
inst_cycles += 8 * (cgb_double + 1) * (val + 1);
R_HDMA = 0xFF;
}
else
{
// disable hblank dma
R_HDMA |= HDMA_OFF;
}
}
return;
// CGB Palette Registers
case 0x68: R_BCPS = val; return;
case 0x69:
R_BCPD[R_BCPS & PAL_INDEX] = val;
if (R_BCPS & PAL_AUTO_INCREMENT)
R_BCPS = PAL_CONTROL_BITS & (R_BCPS + 1);
return;
case 0x6A: R_OCPS = val; return;
case 0x6B:
R_OCPD[R_OCPS & PAL_INDEX] = val;
if (R_OCPS & PAL_AUTO_INCREMENT)
R_OCPS = PAL_CONTROL_BITS & (R_OCPS + 1);
return;
// CGB WRAM bank
case 0x70:
if (cgb_enable)
{
wram_bank = val & 0x7;
if (wram_bank == 0x0)
wram_bank = 0x1;
}
return;
// Interrupt Enable Register
case 0xFF: R_IE = val; return;
// High RAM
default:
if (addr >= HRAM_ADDR)
{
HRAM[addr - HRAM_ADDR] = val;
}
return;
}
}
}
// CPU //////////////////////////////
u8 OP_CYCLES[0x100] = {
// 0 1 2 3 4 5 6 7 8 9 A B C D E F
4,12, 8, 8, 4, 4, 8, 4,20, 8, 8, 8, 4, 4, 8, 4, // 0x00
4,12, 8, 8, 4, 4, 8, 4, 8, 8, 8, 8, 4, 4, 8, 4, // 0x10
8,12, 8, 8, 4, 4, 8, 4, 8, 8, 8, 8, 4, 4, 8, 4, // 0x20
8,12, 8, 8,12,12,12, 4, 8, 8, 8, 8, 4, 4, 8, 4, // 0x30
4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4, // 0x40
4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4, // 0x50
4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4, // 0x60
8, 8, 8, 8, 8, 8, 4, 8, 4, 4, 4, 4, 4, 4, 8, 4, // 0x70
4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4, // 0x80
4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4, // 0x90
4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4, // 0xA0
4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4, // 0xB0
8,12,12,12,12,16, 8,32, 8, 8,12, 8,12,12, 8,32, // 0xC0
8,12,12, 0,12,16, 8,32, 8, 8,12, 0,12, 0, 8,32, // 0xD0
12,12, 8, 0, 0,16, 8,32,16, 4,16, 0, 0, 0, 8,32, // 0xE0
12,12, 8, 4, 0,16, 8,32,12, 8,16, 4, 0, 0, 8,32 // 0xF0
};
// CPU REGISTERS
u8 R_A;
u8 R_B; u8 R_C;
u8 R_D; u8 R_E;
u8 R_H; u8 R_L;
u16 SP;
u16 PC;
#define R_BC (R_B << 8 | R_C)
#define R_DE (R_D << 8 | R_E)
#define R_HL (R_H << 8 | R_L)
// FLAG REGISTER
u8 F_Z;
u8 F_N;
u8 F_H;
u8 F_C;
// random variables
u8 N; s8 SN;
u16 NN; u32 NNNN;
u8 D1, D2; // DAA
void RunFrame()
{
gb_frame = 0;
while (!gb_frame)
StepCPU();
}
void StepCPU()
{
// handle interrupts
if ((gb_ime || gb_halt) && (R_IF & R_IE & ANY_INTR))
{
// disable halt
gb_halt = 0;
if (gb_ime)
{
// disable interrupts
gb_ime = 0;
// PUSH PC
WRITE(--SP, PC >> 8);
WRITE(--SP, PC & 0xFF);
// Call interrupt handler
if (R_IF & R_IE & VBLANK_INTR)
{
PC = VBLANK_INTR_ADDR;
R_IF ^= VBLANK_INTR;
}
else if (R_IF & R_IE & LCDC_INTR)
{
PC = LCDC_INTR_ADDR;
R_IF ^= LCDC_INTR;
}
else if (R_IF & R_IE & TIMER_INTR)
{
PC = TIMER_INTR_ADDR;
R_IF ^= TIMER_INTR;
}
else if (R_IF & R_IE & SERIAL_INTR)
{
PC = SERIAL_INTR_ADDR;
R_IF ^= SERIAL_INTR;
}
else if (R_IF & R_IE & CONTROL_INTR)
{
PC = CONTROL_INTR_ADDR;
R_IF ^= CONTROL_INTR;
}
}
}
// Execute one instruction
OP = (gb_halt ? 0x00 : READ(PC++));
inst_cycles = OP_CYCLES[OP];
printf("%i;", OP);
switch (OP)
{
case 0x00: // NOP
break;
case 0x01: // LD BC, imm
R_C = READ(PC++);
R_B = READ(PC++);
break;
case 0x02: // LD (BC), A
WRITE(R_BC, R_A);
break;
case 0x03: // INC BC
NN = R_BC + 1;
R_B = NN >> 8;
R_C = NN & 0xFF;
break;
case 0x04: // INC B
R_B++;
F_Z = (R_B == 0x00);
F_N = 0;
F_H = ((R_B & 0x0F) == 0x00);
break;
case 0x05: // DEC B
R_B--;
F_Z = (R_B == 0x00);
F_N = 1;
F_H = ((R_B & 0x0F) == 0x0F);
break;
case 0x06: // LD B, imm
R_B = READ(PC++);
break;
case 0x07: // RLCA
R_A = (R_A << 1) | (R_A >> 7);
F_Z = 0;
F_N = 0;
F_H = 0;
F_C = (R_A & 0x01);
break;
case 0x08: // LD (imm), SP
NN = READ(PC++);
NN |= READ(PC++) << 8;
WRITE(NN++, SP & 0xFF);
WRITE(NN, SP >> 8);
break;
case 0x09: // ADD HL, BC
NNNN = R_HL + R_BC;
F_N = 0;
F_H = (NNNN ^ R_HL ^ R_BC) & 0x1000 ? 1 : 0;
F_C = (NNNN & 0xFFFF0000) ? 1 : 0;
R_H = (NNNN & 0x0000FF00) >> 8;
R_L = (NNNN & 0x000000FF);
break;
case 0x0A: // LD A, (BC)
R_A = READ(R_BC);
break;
case 0x0B: // DEC BC
NN = R_BC - 1;
R_B = NN >> 8;
R_C = NN & 0xFF;
break;
case 0x0C: // INC C
R_C++;
F_Z = (R_C == 0x00);
F_N = 0;
F_H = ((R_C & 0x0F) == 0x00);
break;
case 0x0D: // DEC C
R_C--;
F_Z = (R_C == 0x00);
F_N = 1;
F_H = ((R_C & 0x0F) == 0x0F);
break;
case 0x0E: // LD C, imm
R_C = READ(PC++);
break;
case 0x0F: // RRCA
F_C = R_A & 0x01;
R_A = (R_A >> 1) | (R_A << 7);
F_Z = 0;
F_N = 0;
F_H = 0;
break;
case 0x10: // STOP
gb_halt = 1;
if (cgb_enable)
{
// check for CGB speed change
if (R_KEY1 & 0x01)
{
printf("DOUBLE SPEED\n");
cgb_double = !cgb_double;
R_KEY1 = 0x00;
}
}
break;
case 0x11: // LD DE, imm
R_E = READ(PC++);
R_D = READ(PC++);
break;
case 0x12: // LD (DE), A
WRITE(R_DE, R_A);
break;
case 0x13: // INC DE
NN = R_DE + 1;
R_D = NN >> 8;
R_E = NN & 0xFF;
break;
case 0x14: // INC D
R_D++;
F_Z = (R_D == 0x00);
F_N = 0;
F_H = ((R_D & 0x0F) == 0x00);
break;
case 0x15: // DEC D
R_D--;
F_Z = (R_D == 0x00);
F_N = 1;
F_H = ((R_D & 0x0F) == 0x0F);
break;
case 0x16: // LD D, imm
R_D = READ(PC++);
break;
case 0x17: // RLA
N = R_A;
R_A = R_A << 1 | F_C;
F_Z = 0;
F_N = 0;
F_H = 0;
F_C = (N >> 7) & 0x01;
break;
case 0x18: // JR imm
SN = (s8)READ(PC++);
PC += SN;
break;
case 0x19: // ADD HL, DE
NNNN = R_HL + R_DE;
F_N = 0;
F_H = (NNNN ^ R_HL ^ R_DE) & 0x1000 ? 1 : 0;
F_C = (NNNN & 0xFFFF0000) ? 1 : 0;
R_H = (NNNN & 0x0000FF00) >> 8;
R_L = (NNNN & 0x000000FF);
break;
case 0x1A: // LD A, (DE)
R_A = READ(R_DE);
break;
case 0x1B: // DEC DE
NN = R_DE - 1;
R_D = NN >> 8;
R_E = NN & 0xFF;
break;
case 0x1C: // INC E
R_E++;
F_Z = (R_E == 0x00);
F_N = 0;
F_H = ((R_E & 0x0F) == 0x00);
break;
case 0x1D: // DEC E
R_E--;
F_Z = (R_E == 0x00);
F_N = 1;
F_H = ((R_E & 0x0F) == 0x0F);
break;
case 0x1E: // LD E, imm
R_E = READ(PC++);
break;
case 0x1F: // RRA
N = R_A;
R_A = R_A >> 1 | (F_C << 7);
F_Z = 0;
F_N = 0;
F_H = 0;
F_C = N & 0x1;
break;
case 0x20: // JP NZ, imm
SN = (s8)READ(PC++);
if (!F_Z)
{
PC += SN;
}
break;
case 0x21: // LD HL, imm
R_L = READ(PC++);
R_H = READ(PC++);
break;
case 0x22: // LDI (HL), A
WRITE(R_HL, R_A);
NN = R_HL + 1;
R_H = NN >> 8;
R_L = NN & 0xFF;
break;
case 0x23: // INC HL
NN = R_HL + 1;
R_H = NN >> 8;
R_L = NN & 0xFF;
break;
case 0x24: // INC H
R_H++;
F_Z = (R_H == 0x00);
F_N = 0;
F_H = ((R_H & 0x0F) == 0x00);
break;
case 0x25: // DEC H
R_H--;
F_Z = (R_H == 0x00);
F_N = 1;
F_H = ((R_H & 0x0F) == 0x0F);
break;
case 0x26: // LD H, imm
R_H = READ(PC++);
break;
case 0x27: // DAA
D1 = R_A >> 4;
D2 = R_A & 0x0F;
if (F_N)
{
if (F_H) D2 -= 6;
if (F_C) D1 -= 6;
if (D2>9) D2 -= 6;
if (D1 > 9)
{
D1 -= 6;
F_C = 1;
}
}
else
{
if (F_H) D2 += 6;
if (F_C) D1 += 6;
if (D2 > 9)
{
D2 -= 10;
D1++;
}
if (D1 > 9)
{
D1 -= 10;
F_C = 1;
}
}
R_A = ((D1 << 4) & 0xF0) | (D2 & 0x0F);
F_Z = (R_A == 0);
F_H = 0;
break;
case 0x28: // JP Z, imm
SN = (s8)READ(PC++);
if (F_Z)
{
PC += SN;
}
break;
case 0x29: // ADD HL, HL
NNNN = R_HL + R_HL;
F_N = 0;
F_H = (NNNN & 0x1000) ? 1 : 0;
F_C = (NNNN & 0xFFFF0000) ? 1 : 0;
R_H = (NNNN & 0x0000FF00) >> 8;
R_L = (NNNN & 0x000000FF);
break;
case 0x2A: // LDI A, (HL)
R_A = READ(R_HL);
NN = R_HL + 1;
R_H = NN >> 8;
R_L = NN & 0xFF;
break;
case 0x2B: // DEC HL
NN = R_HL - 1;
R_H = NN >> 8;
R_L = NN & 0xFF;
break;
case 0x2C: // INC L
R_L++;
F_Z = (R_L == 0x00);
F_N = 0;
F_H = ((R_L & 0x0F) == 0x00);
break;
case 0x2D: // DEC L
R_L--;
F_Z = (R_L == 0x00);
F_N = 1;
F_H = ((R_L & 0x0F) == 0x0F);
break;
case 0x2E: // LD L, imm
R_L = READ(PC++);
break;
case 0x2F: // CPL
R_A = R_A ^ 0xFF;
F_N = 1;
F_H = 1;
break;
case 0x30: // JP NC, imm
SN = (s8)READ(PC++);
if (!F_C)
{
PC += SN;
}
break;
case 0x31: // LD SP, imm
SP = READ(PC++);
SP |= READ(PC++) << 8;
break;
case 0x32: // LDD (HL), A
WRITE(R_HL, R_A);
NN = R_HL - 1;
R_H = NN >> 8;
R_L = NN & 0xFF;
break;
case 0x33: // INC SP
SP++;
break;
case 0x34: // INC (HL)
N = READ(R_HL) + 1;
F_Z = (N == 0x00);
F_N = 0;
F_H = ((N & 0x0F) == 0x00);
WRITE(R_HL, N);
break;
case 0x35: // DEC (HL)
N = READ(R_HL) - 1;
F_Z = (N == 0x00);
F_N = 1;
F_H = ((N & 0x0F) == 0x0F);
WRITE(R_HL, N);
break;
case 0x36: // LD (HL), imm
WRITE(R_HL, READ(PC++));
break;
case 0x37: // SCF
F_N = 0;
F_H = 0;
F_C = 1;
break;
case 0x38: // JP C, imm
SN = (s8)READ(PC++);