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017-02-of-03-dts-add-ixp43x-watchguard-xtm21w.diff
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017-02-of-03-dts-add-ixp43x-watchguard-xtm21w.diff
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--- a/arch/arm/boot/dts/intel-ixp43x-watchguard-xtm21w.dts 1970-01-01 12:00:00.000000000 +1200
+++ b/arch/arm/boot/dts/intel-ixp43x-watchguard-xtm21w.dts 2023-10-10 18:49:14.912883281 +1300
@@ -0,0 +1,294 @@
+// SPDX-License-Identifier: ISC
+/*
+ * Device Tree file for the Watchguard XTM21-W
+ * firewall device.
+ */
+
+/dts-v1/;
+
+#include "intel-ixp43x.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Watchguard XTM21W";
+ compatible = "watchguard,xtm21w","intel,ixp43x";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memory@0 {
+ /*
+ * The Watchuard XTM21W has 256 MB of memory
+ */
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
+ stdout-path = "uart0:115200n8";
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ i2c {
+ compatible = "i2c-gpio";
+ /*
+ * Watchguard vendor kernel used IRQ 5 for SDA and IRQ 4 for SCL
+ */
+ sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio0 4 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* RTC: Seiko Instruments S-35390A */
+ s35390a@30 {
+ compatible = "sii,s35390a";
+ reg = <0x30>;
+ };
+ };
+
+ soc {
+ interrupt-controller@c8003000 {
+ compatible = "intel,ixp43x-interrupt";
+ };
+
+ bus@c4000000 {
+ compatible = "intel,ixp43x-expansion-bus-controller", "syscon";
+ /* Uses at least up to 0x230 */
+ reg = <0xc4000000 0x1000>;
+
+ /* 16 MB NOR FLASH */
+ flash@0,0 {
+ compatible = "intel,ixp4xx-flash", "cfi-flash";
+ bank-width = <2>;
+ /* Enable writes on the expansion bus */
+ intel,ixp4xx-eb-write-enable = <1>;
+ /* 16 MB of Flash mapped in at CS0 */
+ reg = <0 0x00000000 0x1000000>;
+
+ partitions {
+// compatible = "redboot-fis";
+ /*
+ * The stock Watchguard Redboot flash layout is staticly defined.
+ * Running 'fis init' will setup 3 partitions with different erasebock sizes.
+ * 0x000000000000-0x000000080000 : "RedBoot"
+ * 0x0000000f0000-0x0000000ff000 : "FIS directory"
+ * 0x0000000ff000-0x000000100000 : "RedBoot config"
+ *
+ * dev: size erasesize name
+ * mtd0: 00080000 00010000 "RedBoot"
+ * mtd1: 0000f000 00008000 "FIS directory"
+ * mtd2: 00001000 00004000 "RedBoot config"
+ */
+// fis-index-block = <0xf>;
+ compatible = "fixed-partitions";
+ /*
+ * Partition info from a boot log
+ *
+ */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "Redboot";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+ partition@80000 {
+ label = "cfg0";
+ reg = <0x80000 0x20000>;
+ read-only;
+ };
+ partition@a0000 {
+ label = "cfg1";
+ reg = <0xa0000 0x10000>;
+ read-only;
+ };
+ partition@b0000 {
+ label = "mfg";
+ reg = <0xb0000 0x10000>;
+ read-only;
+ };
+ partition@c0000 {
+ label = "bootOpt";
+ reg = <0xc0000 0x10000>;
+ read-only;
+ };
+ partition@d0000 {
+ label = "Unused";
+ reg = <0xd0000 0x10000>;
+ read-only;
+ };
+ partition@e0000 {
+ label = "RedbootConfig";
+ reg = <0xe0000 0x20000>;
+ read-only;
+ };
+ };
+ };
+
+ gpio-nand@1,0 {
+ /* Some designs have a NAND on CS1 enable it here if present */
+ status = "ok";
+
+ /*
+ *
+ * 256MB of Samsung GPIO controlled SLC NAND
+ *
+ */
+ compatible = "gpio-control-nand";
+
+ /* Expansion bus set-up */
+ intel,ixp4xx-eb-t1 = <0>;
+ intel,ixp4xx-eb-t2 = <0>;
+ intel,ixp4xx-eb-t3 = <1>; // 1 cycle extra strobe phase
+ intel,ixp4xx-eb-t4 = <0>;
+ intel,ixp4xx-eb-t5 = <0>;
+ intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
+ intel,ixp4xx-eb-byte-access-on-halfword = <0>;
+ intel,ixp4xx-eb-mux-address-and-data = <0>;
+ intel,ixp4xx-eb-ahb-split-transfers = <0>;
+ intel,ixp4xx-eb-write-enable = <1>;
+ intel,ixp4xx-eb-byte-access = <1>;
+
+ /* 512 bytes memory window */
+ reg = <1 0x00000000 0x200>;
+// nand-on-flash-bbt;
+ nand-ecc-mode = "soft_bch";
+ nand-ecc-step-size = <512>;
+ nand-ecc-strength = <4>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ rdy-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+ nce-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+ ale-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+ cle-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+ nwp-gpios = <0>;
+
+ label = "ixp400 NAND";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ fs@0 {
+ label = "SysA Kernel";
+ reg = <0x0 0x400000>;
+ };
+ fs@400000 {
+ label = "SysA Code";
+ reg = <0x400000 0x7C00000>;
+ };
+ };
+ };
+ };
+
+ pci@c0000000 {
+ status = "ok";
+ /*
+ * Watchguard kernel did apply the PCI prefetch workaround (eg hammering errata)
+ * PCI: IXP43x Richland silicon detected - PCI Non-Prefetch Workaround Enabled
+ * Hence we set it to ixp42x-pci compatible to enforce this, despite being ixp43x
+ * FIXME: This workaround may not be required
+ */
+ compatible = "intel,ixp42x-pci";
+ /*
+ * Taken from IXDP425 PCI boardfile.
+ * PCI slots on the BIXMB425BD base card.
+ * We have up to 4 slots (IDSEL) with 4 swizzled IRQs.
+ */
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map =
+ /* IDSEL 2 */
+ <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT A on mini-PCI slot is GPIO 10 */
+ };
+
+ /* EthA: NPE-A --> RTL8366SR --> PHY 32 = eth3, PHY 33 = eth4, PHY 34 = eth5 */
+ etha: ethernet@c800c000 {
+ status = "ok";
+ queue-rx = <&qmgr 2>;
+ queue-txready = <&qmgr 19>;
+ phy-mode = "rgmii";
+ intel,npe-handle = <&npe 0>;
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+ };
+
+ /* EthC: NPE-C --> Marvell DSA Switch 88E6060 --> PHY 16 = eth0, PHY 17 = eth1, PHY 18 = eth2 */
+ ethc: ethernet@c800a000 {
+ status = "okay";
+ queue-rx = <&qmgr 4>;
+ queue-txready = <&qmgr 21>;
+ phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /*
+ * PHY 0..4 are internal to the MV88E6060 switch but appear
+ * as independent devices.
+ */
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+
+ /* The switch uses MDIO addresses 16 thru 31 */
+ switch@16 {
+ compatible = "marvell,mv88e6060";
+ reg = <16>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ phy-handle = <&phy0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ phy-handle = <&phy1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ phy-handle = <&phy2>;
+ };
+
+ port@5 {
+ /* Port 5 is the CPU port according to the MV88E6060 datasheet */
+ reg = <5>;
+ phy-mode = "rgmii-id";
+ ethernet = <ðc>;
+ label = "cpu";
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+ };
+ };
+ };
+ };
+ };
+ };
+};