examples/gray_counter.ipynb

{
 "cells": [
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "# Procedural elements\n",
    "\n",
    "There are cases where you construct a logic out of a chain of primitive elements.\n",
    "Take a gray counter, for example. It is used often for cross-clock-domain negotations\n",
    "(dual clock FIFO fill counters).\n",
    "\n",
    "\n",
    "## Gray counter\n",
    "\n",
    "This gray counter example is a bit 'overdone' in comparison to the classical\n",
    "examples to demonstrate configureability and procedural concatenation of elements."
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "### Gray 'primitive'\n",
    "\n",
    "This `gray_unit` is a (configureable) element to construct gray counters of arbitrary length."
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 1,
   "metadata": {},
   "outputs": [],
   "source": [
    "from myirl.emulation.myhdl import *\n",
    "\n",
    "_in = Signal\n",
    "_out = Signal.Output\n",
    "\n",
    "@block\n",
    "def gray_unit(\n",
    "    clk : ClkSignal,\n",
    "    ce : _in, reset : ResetSignal,\n",
    "    flavor : _in,\n",
    "    ia : _in,\n",
    "    ib: _in,\n",
    "    oa : _out,\n",
    "    ob : _out,\n",
    "    NEW_STYLE = False,\n",
    "    *, INITVAL = False\n",
    "):\n",
    "    a = Signal(INITVAL, name='a')\n",
    "\n",
    "    @always_seq(clk.posedge, reset)\n",
    "    def worker():\n",
    "        if ce == 1:\n",
    "            a.next = a ^ ((ia ^ flavor) & ib)\n",
    "            \n",
    "    if NEW_STYLE:\n",
    "        wire0 = oa.wireup(a)\n",
    "        wire1 = ob.wireup(ib & ~(ia ^ flavor)) \n",
    "    else: \n",
    "        @always_comb\n",
    "        def assign():\n",
    "            oa.next = a\n",
    "            ob.next = ib & ~(ia ^ flavor)\n",
    "\n",
    "    return instances()"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "From this element, we construct a gray counter using a few auxiliaries:"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 2,
   "metadata": {},
   "outputs": [],
   "source": [
    "import myhdl\n",
    "\n",
    "def graycode(v, size):\n",
    "    bv = intbv(v)[size:]\n",
    "    z = bv ^ myhdl.concat(\"0\", bv[size:1])\n",
    "    # print \"Gray code:\", z, len(bv)\n",
    "    return intbv(z)[size:]\n",
    "\n",
    "def parity(v):\n",
    "    \"\"\"Return parity bit from value v\"\"\"\n",
    "    p = False\n",
    "    for i in v:\n",
    "        if i:\n",
    "            p = not p\n",
    "\n",
    "    return p"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 3,
   "metadata": {},
   "outputs": [],
   "source": [
    "@block\n",
    "def gray_counter(\n",
    "    clk : ClkSignal,\n",
    "    ce : Signal,\n",
    "    reset : ResetSignal,\n",
    "    rval : intbv,\n",
    "    direction : Signal,\n",
    "    val : Signal.Output\n",
    "):\n",
    "        \n",
    "    n = len(val)\n",
    "    p = parity(rval)\n",
    "    \n",
    "    z = not (p ^ direction) # Important to use `not` to get boolean result\n",
    "    \n",
    "    u = [ Signal(bool(z), name=\"u%d\" % (i)) for i in range(n+1) ]\n",
    "    u0 = u[0]\n",
    "\n",
    "    v = [ Signal(bool(), name='v%d' % i) for i in range(n+1) ]\n",
    "    s = Signal(bool())\n",
    "\n",
    "    tmp = list(reversed(u))[:-1]\n",
    "    out = concat(*tmp)\n",
    "    inst_gray = []\n",
    "\n",
    "    @always_seq(clk.posedge, reset)\n",
    "    def worker():\n",
    "        if ce == 1:\n",
    "            u0.next = ~u0\n",
    "\n",
    "    wires = [\n",
    "        val.wireup(out),\n",
    "        v[0].wireup(True)      \n",
    "    ]\n",
    "            \n",
    "    @always_comb\n",
    "    def assign():\n",
    "        if direction == True:\n",
    "            s.next = u[n-1] ^ u[n]\n",
    "        else:\n",
    "            s.next = u[n-1] | u[n]\n",
    "\n",
    "\n",
    "    for i in range(1, n):\n",
    "        inst_gray.append(gray_unit(clk, ce, reset, direction, u[i-1], v[i-1], u[i], v[i], INITVAL = rval[i-1]))\n",
    "\n",
    "    # and MSB:\n",
    "    inst_gray.append(    gray_unit(clk, ce, reset, direction, s,      v[n-1], u[n], v[n], INITVAL = rval[n-1]))\n",
    "\n",
    "    return instances()"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "## Simulation"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "For fun, we create a `Waveform` class from an Iterator"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 4,
   "metadata": {},
   "outputs": [],
   "source": [
    "from myirl.loops import Iterator\n",
    "\n",
    "class Waveform(Iterator):\n",
    "    def __init__(self, val, name = 'waveform'):\n",
    "        it = [ True if i == '1' else False for i in val]\n",
    "        super().__init__(it, name)\n",
    "    def convert(self, tgt, tsz = None):\n",
    "        return \"True\" if self.val else \"False\"\n",
    "    def resolve_type(self):\n",
    "        return bool"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 5,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      " DEBUG CREATE wrapper module for tb_gray (EmulationModule 'top_tb_gray') \n",
      "Creating process 'gray_counter/worker' with sensitivity (clk'rising, <reset>)\n",
      "Using default for NEW_STYLE: False\n",
      " NEW_STYLE: use default False \n",
      "Creating process 'gray_unit/worker' with sensitivity (clk'rising, <reset>)\n",
      "Using default for NEW_STYLE: False\n",
      " NEW_STYLE: use default False \n",
      "Using default for NEW_STYLE: False\n",
      " NEW_STYLE: use default False \n",
      "Using default for NEW_STYLE: False\n",
      " NEW_STYLE: use default False \n",
      "Creating sequential 'tb_gray/stim' \n",
      " Elaborating component gray_unit_s1_s1_s1_s1_s1_s1_s1_s1_0_0 \n",
      " Writing 'gray_unit' to file /tmp/myirl_top_tb_gray_3jljf_pm/gray_unit.vhdl \n",
      " Elaborating component gray_counter_s1_s1_s1__intbv_s1_s4 \n",
      " Writing 'gray_counter' to file /tmp/myirl_top_tb_gray_3jljf_pm/gray_counter.vhdl \n",
      " Elaborating component tb_gray_4 \n",
      " Writing 'tb_gray' to file /tmp/myirl_top_tb_gray_3jljf_pm/tb_gray.vhdl \n",
      " Creating library file /tmp/myirl_module_defs_1886ekfy/module_defs.vhdl \n",
      "==== COSIM stdout ====\n",
      "\n",
      "==== COSIM stderr ====\n",
      "\n",
      "==== COSIM stdout ====\n",
      "analyze /home/testing/.local/lib/python3.9/site-packages/myirl-0.0.0-py3.9-linux-x86_64.egg/myirl/targets/../test/vhdl/txt_util.vhdl\n",
      "analyze /home/testing/.local/lib/python3.9/site-packages/myirl-0.0.0-py3.9-linux-x86_64.egg/myirl/targets/libmyirl.vhdl\n",
      "analyze /tmp/myirl_top_tb_gray_3jljf_pm/gray_unit.vhdl\n",
      "analyze /tmp/myirl_top_tb_gray_3jljf_pm/gray_counter.vhdl\n",
      "analyze /tmp/myirl_top_tb_gray_3jljf_pm/tb_gray.vhdl\n",
      "elaborate tb_gray\n",
      "\n",
      "==== COSIM stderr ====\n",
      "\n",
      "==== COSIM stdout ====\n",
      "/tmp/myirl_top_tb_gray_3jljf_pm/tb_gray.vhdl:156:9:@256ns:(assertion failure): Stop Simulation\n",
      "/tmp/tb_gray:error: assertion failed\n",
      "in process .tb_gray(myirl).stim\n",
      "/tmp/tb_gray:error: simulation failed\n",
      "\n",
      "==== COSIM stderr ====\n",
      "\n"
     ]
    }
   ],
   "source": [
    "from myirl.test.common_test import gen_osc\n",
    "\n",
    "@block\n",
    "def tb_gray(SIZE):\n",
    "    clk = ClkSignal(name='clk')\n",
    "    ce = Signal(bool(), name='ce')\n",
    "    direction = Signal(bool(1))\n",
    "    direction.init = True\n",
    "\n",
    "    reset = ResetSignal(0, 1, isasync = False)\n",
    "    dout = Signal(intbv()[SIZE:], name='dout')\n",
    "\n",
    "    o = Signal(intbv()[SIZE:])    \n",
    "    rv = graycode(0, SIZE)\n",
    "    gc = gray_counter(clk, ce, reset, rv, direction, o, USE_ALIAS=True)\n",
    "    \n",
    "    osc = gen_osc(clk, 4)\n",
    "\n",
    "    @always_comb\n",
    "    def assign():\n",
    "        dout.next = o\n",
    "        \n",
    "    @instance\n",
    "    def stim():\n",
    "        ce.next = False\n",
    "        direction.next = False\n",
    "        reset.next = True\n",
    "        yield delay(10)\n",
    "        reset.next = False\n",
    "        for i in Waveform(\"0011111111100000\"):\n",
    "            ce.next = i       \n",
    "            yield clk.negedge\n",
    "        direction.next = True\n",
    "        for i in Waveform(\"001111000111110\"):\n",
    "            ce.next = i       \n",
    "            yield clk.negedge\n",
    "\n",
    "        raise StopSimulation\n",
    "\n",
    "\n",
    "    return instances()\n",
    "\n",
    "from myirl import targets\n",
    "from myirl.test.common_test import run_ghdl\n",
    "\n",
    "def run_testbench(SIZE):\n",
    "    tb = tb_gray(SIZE)\n",
    "    files = tb.elab(targets.VHDL, elab_all=True)\n",
    "    run_ghdl(files, tb, debug = True, vcdfile='tb_gray.vcd')\n",
    "    return files\n",
    "\n",
    "    \n",
    "GRAY_COUNTER_SIZE = 4\n",
    "f = run_testbench(GRAY_COUNTER_SIZE)"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "In the non-parametrized variant, two implementations of `gray_unit` are emitted. We dump the first:"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 6,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "     1\t-- File generated from source:\r\n",
      "     2\t--     /tmp/ipykernel_40759/2642985506.py\r\n",
      "     3\t-- (c) 2016-2021 section5.ch\r\n",
      "     4\t-- Modifications may be lost, edit the source file instead.\r\n",
      "     5\t\r\n",
      "     6\tlibrary IEEE;\r\n",
      "     7\tuse IEEE.std_logic_1164.all;\r\n",
      "     8\tuse IEEE.numeric_std.all;\r\n",
      "     9\t\r\n",
      "    10\tlibrary work;\r\n",
      "    11\t\r\n",
      "    12\tuse work.txt_util.all;\r\n",
      "    13\tuse work.myirl_conversion.all;\r\n",
      "    14\t\r\n",
      "    15\tentity gray_unit is\r\n",
      "    16\t    generic (\r\n",
      "    17\t        INITVAL: boolean := FALSE\r\n",
      "    18\t    );\r\n",
      "    19\t    port (\r\n",
      "    20\t        clk : in std_ulogic;\r\n",
      "    21\t        ce : in std_ulogic;\r\n",
      "    22\t        reset : in std_ulogic;\r\n",
      "    23\t        flavor : in std_ulogic;\r\n",
      "    24\t        ia : in std_ulogic;\r\n",
      "    25\t        ib : in std_ulogic;\r\n",
      "    26\t        oa : out std_ulogic;\r\n",
      "    27\t        ob : out std_ulogic\r\n",
      "    28\t    );\r\n",
      "    29\tend entity gray_unit;\r\n",
      "    30\t\r\n",
      "    31\tarchitecture MyIRL of gray_unit is\r\n",
      "    32\t    -- Local type declarations\r\n",
      "    33\t    -- Signal declarations\r\n",
      "    34\t    signal a : std_ulogic;\r\n",
      "    35\tbegin\r\n",
      "    36\t    \r\n",
      "    37\tworker:\r\n",
      "    38\t    process(clk, reset)\r\n",
      "    39\t    begin\r\n",
      "    40\t        if rising_edge(clk) then\r\n",
      "    41\t            if reset = '1' then\r\n",
      "    42\t                a <= '0';\r\n",
      "    43\t            else\r\n",
      "    44\t                if (ce = '1') then\r\n",
      "    45\t                    a <= (a xor ((ia xor flavor) and ib));\r\n",
      "    46\t                end if;\r\n",
      "    47\t            end if;\r\n",
      "    48\t        end if;\r\n",
      "    49\t    end process;\r\n",
      "    50\t    \r\n",
      "    51\tassign:\r\n",
      "    52\t    process(a, ib, ia, flavor)\r\n",
      "    53\t    begin\r\n",
      "    54\t        oa <= a;\r\n",
      "    55\t        ob <= (ib and (ia xor flavor));\r\n",
      "    56\t    end process;\r\n",
      "    57\t\r\n",
      "    58\tend architecture MyIRL;\r\n",
      "    59\t\r\n"
     ]
    }
   ],
   "source": [
    "! cat -n {f[0]}"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "## Waveform display"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 7,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "tb_gray.clk\n",
      "tb_gray.reset\n",
      "tb_gray.dout[3:0]\n",
      "tb_gray.ce\n",
      "tb_gray.inst_gray_counter_0.reset\n",
      "tb_gray.inst_gray_counter_0.u0\n",
      "tb_gray.inst_gray_counter_0.u1\n",
      "tb_gray.inst_gray_counter_0.u2\n",
      "tb_gray.inst_gray_counter_0.u3\n",
      "tb_gray.inst_gray_counter_0.u4\n"
     ]
    },
    {
     "data": {
      "text/html": [
       "<div><script type=\"WaveDrom\">{\"signal\": [{\"name\": \"tb_gray.clk\", \"wave\": \"0101010101010101010101010101010101010101010101010101010101010101\", \"data\": \"0101010101010101010101010101010101010101010101010101010101010101\"}, {\"name\": \"tb_gray.reset\", \"wave\": \"1..0............................................................\", \"data\": \"10\"}, {\"name\": \"tb_gray.dout[3:0]\", \"wave\": \"u=.......=...=...=...=...................=...=.........=...=....\", \"data\": \"00 01 02 03 04 03 02 01 00 \"}, {\"name\": \"tb_gray.ce\", \"wave\": \"0.....1.................0.............1.......0.....1.........0.\", \"data\": \"0101010\"}, {\"name\": \"tb_gray.inst_gray_counter_0.reset\", \"wave\": \"1..0............................................................\", \"data\": \"10\"}, {\"name\": \"tb_gray.inst_gray_counter_0.u0\", \"wave\": \"u0.....1.0.1.0.1.0.1.0.1...............0.1.0.1.......0.1.0.1.0..\", \"data\": \"0101010101010101010\"}, {\"name\": \"tb_gray.inst_gray_counter_0.u1\", \"wave\": \"u0.......1...0...1...0...................1...0.........1...0....\", \"data\": \"010101010\"}, {\"name\": \"tb_gray.inst_gray_counter_0.u2\", \"wave\": \"u0...........1.......0...................1.............0........\", \"data\": \"01010\"}, {\"name\": \"tb_gray.inst_gray_counter_0.u3\", \"wave\": \"u0...................1...................0......................\", \"data\": \"010\"}, {\"name\": \"tb_gray.inst_gray_counter_0.u4\", \"wave\": \"u0..............................................................\", \"data\": \"0\"}]}</script></div>"
      ]
     },
     "metadata": {},
     "output_type": "display_data"
    },
    {
     "data": {
      "application/javascript": [
       "new Promise(function(resolve, reject) {\n",
       "\tvar script = document.createElement(\"script\");\n",
       "\tscript.onload = resolve;\n",
       "\tscript.onerror = reject;\n",
       "\tscript.src = \"https://wavedrom.com/wavedrom.min.js\";\n",
       "\tdocument.head.appendChild(script);\n",
       "}).then(() => {\n",
       "new Promise(function(resolve, reject) {\n",
       "\tvar script = document.createElement(\"script\");\n",
       "\tscript.onload = resolve;\n",
       "\tscript.onerror = reject;\n",
       "\tscript.src = \"https://wavedrom.com/skins/narrow.js\";\n",
       "\tdocument.head.appendChild(script);\n",
       "}).then(() => {\n",
       "WaveDrom.ProcessAll();\n",
       "});\n",
       "});"
      ]
     },
     "metadata": {},
     "output_type": "display_data"
    }
   ],
   "source": [
    "import wavedraw\n",
    "import nbwavedrom\n",
    "\n",
    "TB = \"tb_gray\"\n",
    "\n",
    "# Configure waveform:\n",
    "cfg = wavedraw.config(TB, {\n",
    "    '.clk' : None,\n",
    "    '.reset' : None, '.dout[%d:0]' % (GRAY_COUNTER_SIZE-1) : None, '.ce' : None})\n",
    "\n",
    "cfg[TB + '.inst_gray_counter_0.reset'] = None\n",
    "\n",
    "u = [ TB + \".inst_gray_counter_0.u%d\" % i for i in range(GRAY_COUNTER_SIZE+1) ]\n",
    "\n",
    "for s in u:\n",
    "    cfg[s] = None\n",
    "\n",
    "waveform = wavedraw.vcd2wave(\"tb_gray.vcd\", TB + '.clk', cfg, delta = 10)\n",
    "    \n",
    "nbwavedrom.draw(waveform)"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "### Observations\n",
    "\n",
    "* The gray counter begins with a start value (`rval`) corresponding to an index\n",
    "* Whenever `ce` is active, it advances according to the `direction` parameter\n",
    "* Note that on every advance, only one bit flips in the counter output (`u[1..n]` bits)\n",
    "\n",
    "### Exercises\n",
    "\n",
    "* Change direction\n",
    "* Try another start value"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "## Alternative implementation\n",
    "\n",
    "For a more realistic, more compact implementation, we use only a bit of procedural connection generator syntax.\n",
    "We also skip direction (downcounting) and initializer support."
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 8,
   "metadata": {},
   "outputs": [],
   "source": [
    "@block\n",
    "def gray_counter1(clk : ClkSignal,\n",
    "                  enable : Signal,\n",
    "                  reset : ResetSignal,\n",
    "                  gray_count :Signal.Output):\n",
    "\n",
    "    n = len(gray_count)\n",
    "    gray_bits = [ Signal(bool(), name=\"u%d\" % i) for i in range(n) ]\n",
    "    code, work = [ Signal(modbv()[n:]) for _ in range(2) ]\n",
    "    flags = [ Signal(bool(), name=\"flags%d\" % i) for i in range(n + 1) ]\n",
    "    toggle = Signal(bool(1))\n",
    "\n",
    "    # This creates connection instances:\n",
    "    connections = [\n",
    "        flags[0].wireup(False),\n",
    "        code.wireup(concat(*reversed(gray_bits))),\n",
    "        work.wireup(concat(\"1\", code[n-2:], toggle))\n",
    "    ]  \n",
    "        \n",
    "    for i in range(n):\n",
    "        v = work[i] & ~flags[i]\n",
    "        connections += [\n",
    "            gray_bits[i].wireup(v ^ gray_count[i]),\n",
    "            flags[i + 1].wireup(flags[i] | v )\n",
    "        ]\n",
    "                \n",
    "    @always_seq(clk.posedge, reset)\n",
    "    def worker():\n",
    "        if enable == True:\n",
    "            gray_count.next = code\n",
    "            toggle.next = ~toggle\n",
    "\n",
    "    return instances()"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "Test bench:"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 9,
   "metadata": {},
   "outputs": [],
   "source": [
    "from myirl.test.common_test import gen_osc\n",
    "\n",
    "@block\n",
    "def tb_gray1(SIZE):\n",
    "    clk = ClkSignal(name='clk')\n",
    "    ce = Signal(bool(), name='ce')\n",
    "\n",
    "    reset = ResetSignal(0, 1, isasync = True)\n",
    "    dout = Signal(intbv()[SIZE:], name='dout')\n",
    "\n",
    "    o = Signal(intbv()[SIZE:])    \n",
    "    rv = graycode(0, SIZE)\n",
    "    gc = gray_counter1(clk, ce, reset, o)\n",
    "    \n",
    "    osc = gen_osc(clk, 2)\n",
    "\n",
    "    @always_comb\n",
    "    def assign():\n",
    "        dout.next = o\n",
    "        \n",
    "    @instance\n",
    "    def stim():\n",
    "        ce.next = False\n",
    "        reset.next = True\n",
    "        yield delay(6)\n",
    "        reset.next = False\n",
    "        for i in Waveform(\"0011111111111111111111111111111111000\"):\n",
    "            ce.next = i       \n",
    "            yield clk.negedge\n",
    "\n",
    "        raise StopSimulation\n",
    "\n",
    "    return instances()\n",
    "\n",
    "from myirl import targets\n",
    "from myirl.test.common_test import run_ghdl\n",
    "\n",
    "def run_testbench(SIZE):\n",
    "    tb = tb_gray1(SIZE)\n",
    "    tb.rename(\"tb_gray1\") # Rename explicitely so that we can rerun\n",
    "    # in interactive mode\n",
    "    files = tb.elab(targets.VHDL, elab_all=True)\n",
    "    run_ghdl(files, tb, vcdfile='tb_gray1.vcd')\n",
    "    return files\n",
    "    "
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 10,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      " DEBUG CREATE wrapper module for tb_gray1 (EmulationModule 'top_tb_gray1') \n",
      "Creating process 'gray_counter1/worker' with sensitivity (clk'rising, <reset>)\n",
      "Creating sequential 'tb_gray1/stim' \n",
      " Elaborating component gray_counter1_s1_s1_s1_s4 \n",
      " Writing 'gray_counter1' to file /tmp/myirl_top_tb_gray1_bnnr5vi7/gray_counter1.vhdl \n",
      " Elaborating component tb_gray1_4 \n",
      " Writing 'tb_gray1' to file /tmp/myirl_top_tb_gray1_bnnr5vi7/tb_gray1.vhdl \n",
      " Creating library file /tmp/myirl_module_defs_5dp7bn94/module_defs.vhdl \n"
     ]
    }
   ],
   "source": [
    "GRAY_COUNTER_SIZE = 4\n",
    "f = run_testbench(GRAY_COUNTER_SIZE)"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 11,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "tb_gray1.reset\n",
      "tb_gray1.dout[3:0]\n",
      "tb_gray1.ce\n",
      "tb_gray1.inst_gray_counter1_0.reset\n",
      "tb_gray1.inst_gray_counter1_0.u0\n",
      "tb_gray1.inst_gray_counter1_0.u1\n",
      "tb_gray1.inst_gray_counter1_0.u2\n",
      "tb_gray1.inst_gray_counter1_0.u3\n"
     ]
    },
    {
     "data": {
      "text/html": [
       "<div><script type=\"WaveDrom\">{\"signal\": [{\"name\": \"tb_gray1.reset\", \"wave\": \"1..0........................................................................\", \"data\": \"10\"}, {\"name\": \"tb_gray1.dout[3:0]\", \"wave\": \"=......=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=......\", \"data\": \"00 01 03 02 06 07 05 04 0c 0d 0f 0e 0a 0b 09 08 00 01 03 02 06 07 05 04 0c 0d 0f 0e 0a 0b 09 08 00 \"}, {\"name\": \"tb_gray1.ce\", \"wave\": \"0.....1...............................................................0.....\", \"data\": \"010\"}, {\"name\": \"tb_gray1.inst_gray_counter1_0.reset\", \"wave\": \"1..0........................................................................\", \"data\": \"10\"}, {\"name\": \"tb_gray1.inst_gray_counter1_0.u0\", \"wave\": \"1......1.0.0.1.1.0.0.1.1.0.0.1.1.0.0.1.1.0.0.1.1.0.0.1.1.0.0.1.1.0.0.1......\", \"data\": \"110011001100110011001100110011001\"}, {\"name\": \"tb_gray1.inst_gray_counter1_0.u1\", \"wave\": \"0......1.1.1...0.0.0...1.1.1...0.0.0...1.1.1...0.0.0...1.1.1...0.0.0........\", \"data\": \"0111000111000111000111000\"}, {\"name\": \"tb_gray1.inst_gray_counter1_0.u2\", \"wave\": \"0..........1.1.1...1.......0.0.0...0.......1.1.1...1.......0.0.0...0........\", \"data\": \"01111000011110000\"}, {\"name\": \"tb_gray1.inst_gray_counter1_0.u3\", \"wave\": \"0......0...0.......1.1.1...1.......0.0.0...0.......1.1.1...1.......0.0......\", \"data\": \"00011110000111100\"}]}</script></div>"
      ]
     },
     "metadata": {},
     "output_type": "display_data"
    },
    {
     "data": {
      "application/javascript": [
       "new Promise(function(resolve, reject) {\n",
       "\tvar script = document.createElement(\"script\");\n",
       "\tscript.onload = resolve;\n",
       "\tscript.onerror = reject;\n",
       "\tscript.src = \"https://wavedrom.com/wavedrom.min.js\";\n",
       "\tdocument.head.appendChild(script);\n",
       "}).then(() => {\n",
       "new Promise(function(resolve, reject) {\n",
       "\tvar script = document.createElement(\"script\");\n",
       "\tscript.onload = resolve;\n",
       "\tscript.onerror = reject;\n",
       "\tscript.src = \"https://wavedrom.com/skins/narrow.js\";\n",
       "\tdocument.head.appendChild(script);\n",
       "}).then(() => {\n",
       "WaveDrom.ProcessAll();\n",
       "});\n",
       "});"
      ]
     },
     "metadata": {},
     "output_type": "display_data"
    }
   ],
   "source": [
    "TB = \"tb_gray1\"\n",
    "\n",
    "# Configure waveform:\n",
    "cfg = wavedraw.config(TB, \n",
    "      { '.reset' : None, '.dout[%d:0]' % (GRAY_COUNTER_SIZE-1) : None, '.ce' : None\n",
    "      }\n",
    ")\n",
    "\n",
    "cfg[TB + '.inst_gray_counter1_0.reset'] = None\n",
    "\n",
    "u = [ TB + \".inst_gray_counter1_0.u%d\" % i for i in range(GRAY_COUNTER_SIZE) ]\n",
    "\n",
    "for s in u:\n",
    "    cfg[s] = None\n",
    "\n",
    "    \n",
    "waveform = wavedraw.vcd2wave(\"tb_gray1.vcd\", TB + '.clk', cfg, delta = 1)\n",
    "    \n",
    "nbwavedrom.draw(waveform)"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 12,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "-- File generated from source:\r\n",
      "--     /tmp/ipykernel_40759/3048462444.py\r\n",
      "-- (c) 2016-2021 section5.ch\r\n",
      "-- Modifications may be lost, edit the source file instead.\r\n",
      "\r\n",
      "library IEEE;\r\n",
      "use IEEE.std_logic_1164.all;\r\n",
      "use IEEE.numeric_std.all;\r\n",
      "\r\n",
      "library work;\r\n",
      "\r\n",
      "use work.txt_util.all;\r\n",
      "use work.myirl_conversion.all;\r\n",
      "\r\n",
      "entity gray_counter1 is\r\n",
      "    port (\r\n",
      "        clk : in std_ulogic;\r\n",
      "        enable : in std_ulogic;\r\n",
      "        reset : in std_ulogic;\r\n",
      "        gray_count : out unsigned(3 downto 0)\r\n",
      "    );\r\n",
      "end entity gray_counter1;\r\n",
      "\r\n",
      "architecture MyIRL of gray_counter1 is\r\n",
      "    -- Local type declarations\r\n",
      "    -- Signal declarations\r\n",
      "    signal toggle : std_ulogic;\r\n",
      "    signal code : unsigned(3 downto 0);\r\n",
      "    signal flags0 : std_ulogic;\r\n",
      "    signal u3 : std_ulogic;\r\n",
      "    signal u2 : std_ulogic;\r\n",
      "    signal u1 : std_ulogic;\r\n",
      "    signal u0 : std_ulogic;\r\n",
      "    signal work : unsigned(3 downto 0);\r\n",
      "    signal flags1 : std_ulogic;\r\n",
      "    signal flags2 : std_ulogic;\r\n",
      "    signal flags3 : std_ulogic;\r\n",
      "    signal flags4 : std_ulogic;\r\n",
      "begin\r\n",
      "    \r\n",
      "worker:\r\n",
      "    process(clk, reset)\r\n",
      "    begin\r\n",
      "        if reset = '1' then\r\n",
      "            gray_count <= x\"0\";\r\n",
      "            toggle <= '1';\r\n",
      "        elsif rising_edge(clk) then\r\n",
      "            if (enable = '1') then\r\n",
      "                gray_count <= code;\r\n",
      "                toggle <= not toggle;\r\n",
      "            end if;\r\n",
      "        end if;\r\n",
      "    end process;\r\n",
      "    flags0 <= '0';\r\n",
      "    code <= (u3 & u2 & u1 & u0);\r\n",
      "    work <= ('1' & code(2-1 downto 0) & toggle);\r\n",
      "    u0 <= ((work(0) and not flags0) xor gray_count(0));\r\n",
      "    flags1 <= (flags0 or (work(0) and not flags0));\r\n",
      "    u1 <= ((work(1) and not flags1) xor gray_count(1));\r\n",
      "    flags2 <= (flags1 or (work(1) and not flags1));\r\n",
      "    u2 <= ((work(2) and not flags2) xor gray_count(2));\r\n",
      "    flags3 <= (flags2 or (work(2) and not flags2));\r\n",
      "    u3 <= ((work(3) and not flags3) xor gray_count(3));\r\n",
      "    flags4 <= (flags3 or (work(3) and not flags3));\r\n",
      "end architecture MyIRL;\r\n",
      "\r\n"
     ]
    }
   ],
   "source": [
    "!cat {f[0]}"
   ]
  }
 ],
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