[discuss] I/O register access abstraction overhead

[errordeveloper]

The I/O registers are currently wrapped in macros that use a simple structure with VolatileCell. What I am wondering is how close is this currently to what one would get when doing the same thing in C? If it's pretty close, then it's certainly worse documenting, and otherwise communicating with Rust developers and see what can be done.

I suppose comparison should be on the basis of disassembly. Perhaps we could take basic mbed GPIO example to benchmark against.

[bgamari]

VolatileCell gets optimized away into just loads and stores. For instance, consider the program,

#![feature(phase)]
#![crate_type="staticlib"]
#![no_std]

extern crate core;
extern crate zinc;

use zinc::hal::k20::pin;

#[no_mangle]
#[no_split_stack]
#[allow(unused_variable)]
#[allow(dead_code)]
pub unsafe fn main() {
  pin::reg::PORTA.GPCLR.set(1);
  loop {
  }
}

This compiles down to,

000001bc <main>:
 1bc:   f249 0000   movw    r0, #36864  ; 0x9000
 1c0:   2101        movs    r1, #1
 1c2:   f2c4 0004   movt    r0, #16388  ; 0x4004
 1c6:   f8c0 1080   str.w   r1, [r0, #128]  ; 0x80
 1ca:   e7fe        b.n 1ca <main+0xe>

[farcaller]

Just as a reminder, we have https://groups.google.com/forum/#!forum/zinc-dev ML for discussions :-) Given that the question is answered, I'll close this one.

[errordeveloper]

@farcaller thanks for the reminder, didn't know there was a mailing list!