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xhci.cpp
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xhci.cpp
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/*
* Copyright 2006-2014, Haiku Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*
* Some code borrowed from the Haiku EHCI driver
*
* Authors:
* Michael Lotz <mmlr@mlotz.ch>
* Jian Chiang <j.jian.chiang@gmail.com>
* Jérôme Duval <jerome.duval@gmail.com>
* Akshay Jaggi <akshay1994.leo@gmail.com>
*/
#include <module.h>
#include <PCI.h>
#include <PCI_x86.h>
#include <USB3.h>
#include <KernelExport.h>
#include <util/AutoLock.h>
#include "xhci.h"
#define USB_MODULE_NAME "xhci"
pci_module_info *XHCI::sPCIModule = NULL;
pci_x86_module_info *XHCI::sPCIx86Module = NULL;
static int32
xhci_std_ops(int32 op, ...)
{
switch (op) {
case B_MODULE_INIT:
TRACE_MODULE("xhci init module\n");
return B_OK;
case B_MODULE_UNINIT:
TRACE_MODULE("xhci uninit module\n");
return B_OK;
}
return EINVAL;
}
static const char*
xhci_error_string(uint32 error)
{
switch (error) {
case COMP_INVALID: return "Invalid";
case COMP_SUCCESS: return "Success";
case COMP_DATA_BUFFER: return "Data buffer";
case COMP_BABBLE: return "Babble detected";
case COMP_USB_TRANSACTION: return "USB transaction";
case COMP_TRB: return "TRB";
case COMP_STALL: return "Stall";
case COMP_RESOURCE: return "Resource";
case COMP_BANDWIDTH: return "Bandwidth";
case COMP_NO_SLOTS: return "No slots";
case COMP_INVALID_STREAM: return "Invalid stream";
case COMP_SLOT_NOT_ENABLED: return "Slot not enabled";
case COMP_ENDPOINT_NOT_ENABLED: return "Endpoint not enabled";
case COMP_SHORT_PACKET: return "Short packet";
case COMP_RING_UNDERRUN: return "Ring underrun";
case COMP_RING_OVERRUN: return "Ring overrun";
case COMP_VF_RING_FULL: return "VF Event Ring Full";
case COMP_PARAMETER: return "Parameter";
case COMP_BANDWIDTH_OVERRUN: return "Bandwidth overrun";
case COMP_CONTEXT_STATE: return "Context state";
case COMP_NO_PING_RESPONSE: return "No ping response";
case COMP_EVENT_RING_FULL: return "Event ring full";
case COMP_INCOMPATIBLE_DEVICE: return "Incompatible device";
case COMP_MISSED_SERVICE: return "Missed service";
case COMP_COMMAND_RING_STOPPED: return "Command ring stopped";
case COMP_COMMAND_ABORTED: return "Command aborted";
case COMP_STOPPED: return "Stopped";
case COMP_LENGTH_INVALID: return "Length invalid";
case COMP_MAX_EXIT_LATENCY: return "Max exit latency too large";
case COMP_ISOC_OVERRUN: return "Isoch buffer overrun";
case COMP_EVENT_LOST: return "Event lost";
case COMP_UNDEFINED: return "Undefined";
case COMP_INVALID_STREAM_ID: return "Invalid stream ID";
case COMP_SECONDARY_BANDWIDTH: return "Secondary bandwidth";
case COMP_SPLIT_TRANSACTION: return "Split transaction";
default: return "Undefined";
}
}
usb_host_controller_info xhci_module = {
{
"busses/usb/xhci",
0,
xhci_std_ops
},
NULL,
XHCI::AddTo
};
module_info *modules[] = {
(module_info *)&xhci_module,
NULL
};
XHCI::XHCI(pci_info *info, Stack *stack)
: BusManager(stack),
fCapabilityRegisters(NULL),
fOperationalRegisters(NULL),
fRegisterArea(-1),
fPCIInfo(info),
fStack(stack),
fIRQ(0),
fUseMSI(false),
fErstArea(-1),
fDcbaArea(-1),
fCmdCompSem(-1),
fFinishTransfersSem(-1),
fFinishThread(-1),
fStopThreads(false),
fFinishedHead(NULL),
fRootHub(NULL),
fRootHubAddress(0),
fPortCount(0),
fSlotCount(0),
fScratchpadCount(0),
fEventSem(-1),
fEventThread(-1),
fEventIdx(0),
fCmdIdx(0),
fEventCcs(1),
fCmdCcs(1)
{
B_INITIALIZE_SPINLOCK(&fSpinlock);
if (BusManager::InitCheck() < B_OK) {
TRACE_ERROR("bus manager failed to init\n");
return;
}
TRACE("constructing new XHCI host controller driver\n");
fInitOK = false;
// enable busmaster and memory mapped access
uint16 command = sPCIModule->read_pci_config(fPCIInfo->bus,
fPCIInfo->device, fPCIInfo->function, PCI_command, 2);
command &= ~(PCI_command_io | PCI_command_int_disable);
command |= PCI_command_master | PCI_command_memory;
sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device,
fPCIInfo->function, PCI_command, 2, command);
// map the registers (low + high for 64-bit when requested)
phys_addr_t physicalAddress = fPCIInfo->u.h0.base_registers[0];
physicalAddress &= PCI_address_memory_32_mask;
if ((fPCIInfo->u.h0.base_register_flags[0] & 0xC) == PCI_address_type_64)
physicalAddress += (phys_addr_t)fPCIInfo->u.h0.base_registers[1] << 32;
uint32 offset = physicalAddress & (B_PAGE_SIZE - 1);
phys_addr_t physicalAddressAligned = physicalAddress - offset;
size_t mapSize = (fPCIInfo->u.h0.base_register_sizes[0]
+ offset + B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1);
TRACE("map physical memory 0x%08" B_PRIx32 " : 0x%08" B_PRIx32 " "
"(base: 0x%08" B_PRIxPHYSADDR "; offset: %" B_PRIx32 ");"
"size: %" B_PRId32 "\n", fPCIInfo->u.h0.base_registers[0],
fPCIInfo->u.h0.base_registers[1], physicalAddress, offset,
fPCIInfo->u.h0.base_register_sizes[0]);
fRegisterArea = map_physical_memory("XHCI memory mapped registers",
physicalAddressAligned, mapSize, B_ANY_KERNEL_BLOCK_ADDRESS,
B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA | B_READ_AREA | B_WRITE_AREA,
(void **)&fCapabilityRegisters);
if (fRegisterArea < B_OK) {
TRACE("failed to map register memory\n");
return;
}
uint32 hciCapLength = ReadCapReg32(XHCI_HCI_CAPLENGTH);
fCapabilityRegisters += offset;
fCapabilityLength = HCI_CAPLENGTH(hciCapLength);
TRACE("mapped capability length: 0x%" B_PRIx32 "\n", fCapabilityLength);
fOperationalRegisters = fCapabilityRegisters + fCapabilityLength;
fRuntimeRegisters = fCapabilityRegisters + ReadCapReg32(XHCI_RTSOFF);
fDoorbellRegisters = fCapabilityRegisters + ReadCapReg32(XHCI_DBOFF);
TRACE("mapped capability registers: 0x%p\n", fCapabilityRegisters);
TRACE("mapped operational registers: 0x%p\n", fOperationalRegisters);
TRACE("mapped runtime registers: 0x%p\n", fRuntimeRegisters);
TRACE("mapped doorbell registers: 0x%p\n", fDoorbellRegisters);
TRACE("interface version: 0x%04" B_PRIx32 "\n",
HCI_VERSION(ReadCapReg32(XHCI_HCI_VERSION)));
TRACE("structural parameters1: 0x%08" B_PRIx32 "\n",
ReadCapReg32(XHCI_HCSPARAMS1));
TRACE("structural parameters2: 0x%08" B_PRIx32 "\n",
ReadCapReg32(XHCI_HCSPARAMS2));
TRACE("structural parameters3: 0x%08" B_PRIx32 "\n",
ReadCapReg32(XHCI_HCSPARAMS3));
TRACE("capability parameters: 0x%08" B_PRIx32 "\n",
ReadCapReg32(XHCI_HCCPARAMS));
uint32 cparams = ReadCapReg32(XHCI_HCCPARAMS);
uint32 eec = 0xffffffff;
uint32 eecp = HCS0_XECP(cparams) << 2;
for (; eecp != 0 && XECP_NEXT(eec); eecp += XECP_NEXT(eec) << 2) {
TRACE("eecp register: 0x%08" B_PRIx32 "\n", eecp);
eec = ReadCapReg32(eecp);
if (XECP_ID(eec) != XHCI_LEGSUP_CAPID)
continue;
if (eec & XHCI_LEGSUP_BIOSOWNED) {
TRACE_ALWAYS("the host controller is bios owned, claiming"
" ownership\n");
WriteCapReg32(eecp, eec | XHCI_LEGSUP_OSOWNED);
for (int32 i = 0; i < 20; i++) {
eec = ReadCapReg32(eecp);
if ((eec & XHCI_LEGSUP_BIOSOWNED) == 0)
break;
TRACE_ALWAYS("controller is still bios owned, waiting\n");
snooze(50000);
}
if (eec & XHCI_LEGSUP_BIOSOWNED) {
TRACE_ERROR("bios won't give up control over the host "
"controller (ignoring)\n");
} else if (eec & XHCI_LEGSUP_OSOWNED) {
TRACE_ALWAYS("successfully took ownership of the host "
"controller\n");
}
// Force off the BIOS owned flag, and clear all SMIs. Some BIOSes
// do indicate a successful handover but do not remove their SMIs
// and then freeze the system when interrupts are generated.
WriteCapReg32(eecp, eec & ~XHCI_LEGSUP_BIOSOWNED);
}
break;
}
uint32 legctlsts = ReadCapReg32(eecp + XHCI_LEGCTLSTS);
legctlsts &= XHCI_LEGCTLSTS_DISABLE_SMI;
legctlsts |= XHCI_LEGCTLSTS_EVENTS_SMI;
WriteCapReg32(eecp + XHCI_LEGCTLSTS, legctlsts);
// On Intel's Panther Point and Lynx Point Chipset taking ownership
// of EHCI owned ports, is what we do here.
if (fPCIInfo->vendor_id == PCI_VENDOR_INTEL) {
switch (fPCIInfo->device_id) {
case PCI_DEVICE_INTEL_PANTHER_POINT_XHCI:
case PCI_DEVICE_INTEL_LYNX_POINT_XHCI:
case PCI_DEVICE_INTEL_LYNX_POINT_LP_XHCI:
case PCI_DEVICE_INTEL_BAYTRAIL_XHCI:
case PCI_DEVICE_INTEL_WILDCAT_POINT_XHCI:
case PCI_DEVICE_INTEL_WILDCAT_POINT_LP_XHCI:
_SwitchIntelPorts();
break;
}
}
// halt the host controller
if (ControllerHalt() < B_OK) {
return;
}
// reset the host controller
if (ControllerReset() < B_OK) {
TRACE_ERROR("host controller failed to reset\n");
return;
}
fCmdCompSem = create_sem(0, "XHCI Command Complete");
fFinishTransfersSem = create_sem(0, "XHCI Finish Transfers");
fEventSem = create_sem(0, "XHCI Event");
if (fFinishTransfersSem < B_OK || fCmdCompSem < B_OK || fEventSem < B_OK) {
TRACE_ERROR("failed to create semaphores\n");
return;
}
// create finisher service thread
fFinishThread = spawn_kernel_thread(FinishThread, "xhci finish thread",
B_NORMAL_PRIORITY, (void *)this);
resume_thread(fFinishThread);
// create finisher service thread
fEventThread = spawn_kernel_thread(EventThread, "xhci event thread",
B_NORMAL_PRIORITY, (void *)this);
resume_thread(fEventThread);
// Find the right interrupt vector, using MSIs if available.
fIRQ = fPCIInfo->u.h0.interrupt_line;
if (sPCIx86Module != NULL && sPCIx86Module->get_msi_count(fPCIInfo->bus,
fPCIInfo->device, fPCIInfo->function) >= 1) {
uint8 msiVector = 0;
if (sPCIx86Module->configure_msi(fPCIInfo->bus, fPCIInfo->device,
fPCIInfo->function, 1, &msiVector) == B_OK
&& sPCIx86Module->enable_msi(fPCIInfo->bus, fPCIInfo->device,
fPCIInfo->function) == B_OK) {
TRACE_ALWAYS("using message signaled interrupts\n");
fIRQ = msiVector;
fUseMSI = true;
}
}
// Install the interrupt handler
TRACE("installing interrupt handler\n");
install_io_interrupt_handler(fIRQ, InterruptHandler, (void *)this, 0);
memset(fPortSpeeds, 0, sizeof(fPortSpeeds));
memset(fPortSlots, 0, sizeof(fPortSlots));
memset(fDevices, 0, sizeof(fDevices));
fInitOK = true;
TRACE("XHCI host controller driver constructed\n");
}
XHCI::~XHCI()
{
TRACE("tear down XHCI host controller driver\n");
WriteOpReg(XHCI_CMD, 0);
int32 result = 0;
fStopThreads = true;
delete_sem(fCmdCompSem);
delete_sem(fFinishTransfersSem);
delete_sem(fEventSem);
wait_for_thread(fFinishThread, &result);
wait_for_thread(fEventThread, &result);
remove_io_interrupt_handler(fIRQ, InterruptHandler, (void *)this);
delete_area(fRegisterArea);
delete_area(fErstArea);
for (uint32 i = 0; i < fScratchpadCount; i++)
delete_area(fScratchpadArea[i]);
delete_area(fDcbaArea);
if (fUseMSI && sPCIx86Module != NULL) {
sPCIx86Module->disable_msi(fPCIInfo->bus,
fPCIInfo->device, fPCIInfo->function);
sPCIx86Module->unconfigure_msi(fPCIInfo->bus,
fPCIInfo->device, fPCIInfo->function);
}
put_module(B_PCI_MODULE_NAME);
if (sPCIx86Module != NULL) {
sPCIx86Module = NULL;
put_module(B_PCI_X86_MODULE_NAME);
}
}
void
XHCI::_SwitchIntelPorts()
{
TRACE("Intel xHC Controller\n");
TRACE("Looking for EHCI owned ports\n");
uint32 ports = sPCIModule->read_pci_config(fPCIInfo->bus,
fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB3PRM, 4);
TRACE("Superspeed Ports: 0x%" B_PRIx32 "\n", ports);
sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device,
fPCIInfo->function, XHCI_INTEL_USB3_PSSEN, 4, ports);
ports = sPCIModule->read_pci_config(fPCIInfo->bus,
fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB3_PSSEN, 4);
TRACE("Superspeed ports now under XHCI : 0x%" B_PRIx32 "\n", ports);
ports = sPCIModule->read_pci_config(fPCIInfo->bus,
fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_USB2PRM, 4);
TRACE("USB 2.0 Ports : 0x%" B_PRIx32 "\n", ports);
sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device,
fPCIInfo->function, XHCI_INTEL_XUSB2PR, 4, ports);
ports = sPCIModule->read_pci_config(fPCIInfo->bus,
fPCIInfo->device, fPCIInfo->function, XHCI_INTEL_XUSB2PR, 4);
TRACE("USB 2.0 ports now under XHCI: 0x%" B_PRIx32 "\n", ports);
}
status_t
XHCI::Start()
{
TRACE_ALWAYS("starting XHCI host controller\n");
TRACE("usbcmd: 0x%08" B_PRIx32 "; usbsts: 0x%08" B_PRIx32 "\n",
ReadOpReg(XHCI_CMD), ReadOpReg(XHCI_STS));
if ((ReadOpReg(XHCI_PAGESIZE) & (1 << 0)) == 0) {
TRACE_ERROR("Controller does not support 4K page size.\n");
return B_ERROR;
}
// read port count from capability register
uint32 capabilities = ReadCapReg32(XHCI_HCSPARAMS1);
fPortCount = HCS_MAX_PORTS(capabilities);
if (fPortCount == 0) {
TRACE_ERROR("Invalid number of ports: %u\n", fPortCount);
fPortCount = 0;
return B_ERROR;
}
fSlotCount = HCS_MAX_SLOTS(capabilities);
WriteOpReg(XHCI_CONFIG, fSlotCount);
// find out which protocol is used for each port
uint8 portFound = 0;
uint32 cparams = ReadCapReg32(XHCI_HCCPARAMS);
uint32 eec = 0xffffffff;
uint32 eecp = HCS0_XECP(cparams) << 2;
for (; eecp != 0 && XECP_NEXT(eec) && portFound < fPortCount;
eecp += XECP_NEXT(eec) << 2) {
eec = ReadCapReg32(eecp);
if (XECP_ID(eec) != XHCI_SUPPORTED_PROTOCOLS_CAPID)
continue;
if (XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(eec) > 3)
continue;
uint32 temp = ReadCapReg32(eecp + 8);
uint32 offset = XHCI_SUPPORTED_PROTOCOLS_1_OFFSET(temp);
uint32 count = XHCI_SUPPORTED_PROTOCOLS_1_COUNT(temp);
if (offset == 0 || count == 0)
continue;
offset--;
for (uint32 i = offset; i < offset + count; i++) {
if (XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(eec) == 0x3)
fPortSpeeds[i] = USB_SPEED_SUPER;
else
fPortSpeeds[i] = USB_SPEED_HIGHSPEED;
TRACE("speed for port %" B_PRId32 " is %s\n", i,
fPortSpeeds[i] == USB_SPEED_SUPER ? "super" : "high");
}
portFound += count;
}
uint32 params2 = ReadCapReg32(XHCI_HCSPARAMS2);
fScratchpadCount = HCS_MAX_SC_BUFFERS(params2);
if (fScratchpadCount > XHCI_MAX_SCRATCHPADS) {
TRACE_ERROR("Invalid number of scratchpads: %" B_PRIu32 "\n",
fScratchpadCount);
return B_ERROR;
}
uint32 params3 = ReadCapReg32(XHCI_HCSPARAMS3);
fExitLatMax = HCS_U1_DEVICE_LATENCY(params3)
+ HCS_U2_DEVICE_LATENCY(params3);
WriteOpReg(XHCI_DNCTRL, 0);
// allocate Device Context Base Address array
phys_addr_t dmaAddress;
fDcbaArea = fStack->AllocateArea((void **)&fDcba, &dmaAddress,
sizeof(*fDcba), "DCBA Area");
if (fDcbaArea < B_OK) {
TRACE_ERROR("unable to create the DCBA area\n");
return B_ERROR;
}
memset(fDcba, 0, sizeof(*fDcba));
memset(fScratchpadArea, 0, sizeof(fScratchpadArea));
memset(fScratchpad, 0, sizeof(fScratchpad));
// setting the first address to the scratchpad array address
fDcba->baseAddress[0] = dmaAddress
+ offsetof(struct xhci_device_context_array, scratchpad);
// fill up the scratchpad array with scratchpad pages
for (uint32 i = 0; i < fScratchpadCount; i++) {
phys_addr_t scratchDmaAddress;
fScratchpadArea[i] = fStack->AllocateArea((void **)&fScratchpad[i],
&scratchDmaAddress, B_PAGE_SIZE, "Scratchpad Area");
if (fScratchpadArea[i] < B_OK) {
TRACE_ERROR("unable to create the scratchpad area\n");
return B_ERROR;
}
fDcba->scratchpad[i] = scratchDmaAddress;
}
TRACE("setting DCBAAP %" B_PRIxPHYSADDR "\n", dmaAddress);
WriteOpReg(XHCI_DCBAAP_LO, (uint32)dmaAddress);
WriteOpReg(XHCI_DCBAAP_HI, /*(uint32)(dmaAddress >> 32)*/0);
// allocate Event Ring Segment Table
uint8 *addr;
fErstArea = fStack->AllocateArea((void **)&addr, &dmaAddress,
(XHCI_MAX_COMMANDS + XHCI_MAX_EVENTS) * sizeof(xhci_trb)
+ sizeof(xhci_erst_element),
"USB XHCI ERST CMD_RING and EVENT_RING Area");
if (fErstArea < B_OK) {
TRACE_ERROR("unable to create the ERST AND RING area\n");
delete_area(fDcbaArea);
return B_ERROR;
}
fErst = (xhci_erst_element *)addr;
memset(fErst, 0, (XHCI_MAX_COMMANDS + XHCI_MAX_EVENTS) * sizeof(xhci_trb)
+ sizeof(xhci_erst_element));
// fill with Event Ring Segment Base Address and Event Ring Segment Size
fErst->rs_addr = dmaAddress + sizeof(xhci_erst_element);
fErst->rs_size = XHCI_MAX_EVENTS;
fErst->rsvdz = 0;
addr += sizeof(xhci_erst_element);
fEventRing = (xhci_trb *)addr;
addr += XHCI_MAX_EVENTS * sizeof(xhci_trb);
fCmdRing = (xhci_trb *)addr;
TRACE("setting ERST size\n");
WriteRunReg32(XHCI_ERSTSZ(0), XHCI_ERSTS_SET(1));
TRACE("setting ERDP addr = 0x%" B_PRIx64 "\n", fErst->rs_addr);
WriteRunReg32(XHCI_ERDP_LO(0), (uint32)fErst->rs_addr);
WriteRunReg32(XHCI_ERDP_HI(0), /*(uint32)(fErst->rs_addr >> 32)*/0);
TRACE("setting ERST base addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress);
WriteRunReg32(XHCI_ERSTBA_LO(0), (uint32)dmaAddress);
WriteRunReg32(XHCI_ERSTBA_HI(0), /*(uint32)(dmaAddress >> 32)*/0);
dmaAddress += sizeof(xhci_erst_element) + XHCI_MAX_EVENTS
* sizeof(xhci_trb);
TRACE("setting CRCR addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress);
WriteOpReg(XHCI_CRCR_LO, (uint32)dmaAddress | CRCR_RCS);
WriteOpReg(XHCI_CRCR_HI, /*(uint32)(dmaAddress >> 32)*/0);
// link trb
fCmdRing[XHCI_MAX_COMMANDS - 1].qwtrb0 = dmaAddress;
TRACE("setting interrupt rate\n");
// Setting IMOD below 0x3F8 on Intel Lynx Point can cause IRQ lockups
if (fPCIInfo->vendor_id == PCI_VENDOR_INTEL
&& (fPCIInfo->device_id == PCI_DEVICE_INTEL_PANTHER_POINT_XHCI
|| fPCIInfo->device_id == PCI_DEVICE_INTEL_LYNX_POINT_XHCI
|| fPCIInfo->device_id == PCI_DEVICE_INTEL_LYNX_POINT_LP_XHCI
|| fPCIInfo->device_id == PCI_DEVICE_INTEL_BAYTRAIL_XHCI
|| fPCIInfo->device_id == PCI_DEVICE_INTEL_WILDCAT_POINT_XHCI)) {
WriteRunReg32(XHCI_IMOD(0), 0x000003f8); // 4000 irq/s
} else {
WriteRunReg32(XHCI_IMOD(0), 0x000001f4); // 8000 irq/s
}
TRACE("enabling interrupt\n");
WriteRunReg32(XHCI_IMAN(0), ReadRunReg32(XHCI_IMAN(0)) | IMAN_INTR_ENA);
WriteOpReg(XHCI_CMD, CMD_RUN | CMD_EIE | CMD_HSEIE);
// wait for start up state
int32 tries = 100;
while ((ReadOpReg(XHCI_STS) & STS_HCH) != 0) {
snooze(1000);
if (tries-- < 0) {
TRACE_ERROR("start up timeout\n");
break;
}
}
fRootHubAddress = AllocateAddress();
fRootHub = new(std::nothrow) XHCIRootHub(RootObject(), fRootHubAddress);
if (!fRootHub) {
TRACE_ERROR("no memory to allocate root hub\n");
return B_NO_MEMORY;
}
if (fRootHub->InitCheck() < B_OK) {
TRACE_ERROR("root hub failed init check\n");
return fRootHub->InitCheck();
}
SetRootHub(fRootHub);
TRACE_ALWAYS("successfully started the controller\n");
#ifdef TRACE_USB
TRACE("No-Op test\n");
Noop();
#endif
return BusManager::Start();
}
status_t
XHCI::SubmitTransfer(Transfer *transfer)
{
// short circuit the root hub
if (transfer->TransferPipe()->DeviceAddress() == fRootHubAddress)
return fRootHub->ProcessTransfer(this, transfer);
TRACE("SubmitTransfer()\n");
Pipe *pipe = transfer->TransferPipe();
if ((pipe->Type() & USB_OBJECT_ISO_PIPE) != 0)
return B_UNSUPPORTED;
if ((pipe->Type() & USB_OBJECT_CONTROL_PIPE) != 0)
return SubmitControlRequest(transfer);
return SubmitNormalRequest(transfer);
}
status_t
XHCI::SubmitControlRequest(Transfer *transfer)
{
Pipe *pipe = transfer->TransferPipe();
usb_request_data *requestData = transfer->RequestData();
bool directionIn = (requestData->RequestType & USB_REQTYPE_DEVICE_IN) != 0;
TRACE("SubmitControlRequest() length %d\n", requestData->Length);
xhci_td *setupDescriptor = CreateDescriptor(requestData->Length);
// set SetupStage
uint8 index = 0;
setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) | TRB_2_BYTES(8);
setupDescriptor->trbs[index].dwtrb3
= B_HOST_TO_LENDIAN_INT32(TRB_3_TYPE(TRB_TYPE_SETUP_STAGE)
| TRB_3_IDT_BIT | TRB_3_CYCLE_BIT);
if (requestData->Length > 0) {
setupDescriptor->trbs[index].dwtrb3 |= B_HOST_TO_LENDIAN_INT32(
directionIn ? TRB_3_TRT_IN : TRB_3_TRT_OUT);
}
memcpy(&setupDescriptor->trbs[index].qwtrb0, requestData,
sizeof(usb_request_data));
index++;
if (requestData->Length > 0) {
// set DataStage if any
setupDescriptor->trbs[index].qwtrb0 = setupDescriptor->buffer_phy[0];
setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0)
| TRB_2_BYTES(requestData->Length)
| TRB_2_TD_SIZE(transfer->VectorCount());
setupDescriptor->trbs[index].dwtrb3 = B_HOST_TO_LENDIAN_INT32(
TRB_3_TYPE(TRB_TYPE_DATA_STAGE)
| (directionIn ? (TRB_3_DIR_IN | TRB_3_ISP_BIT) : 0)
| TRB_3_CYCLE_BIT);
// TODO copy data for out transfers
index++;
}
// set StatusStage
setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0);
setupDescriptor->trbs[index].dwtrb3 = B_HOST_TO_LENDIAN_INT32(
TRB_3_TYPE(TRB_TYPE_STATUS_STAGE)
| ((directionIn && requestData->Length > 0) ? 0 : TRB_3_DIR_IN)
| TRB_3_IOC_BIT | TRB_3_CYCLE_BIT);
setupDescriptor->trb_count = index + 1;
xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie();
uint8 id = XHCI_ENDPOINT_ID(pipe);
if (id >= XHCI_MAX_ENDPOINTS) {
TRACE_ERROR("Invalid Endpoint");
return B_BAD_VALUE;
}
setupDescriptor->transfer = transfer;
transfer->InitKernelAccess();
_LinkDescriptorForPipe(setupDescriptor, endpoint);
TRACE("SubmitControlRequest() request linked\n");
TRACE("Endpoint status 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%016" B_PRIx64 "\n",
endpoint->device->device_ctx->endpoints[id-1].dwendpoint0,
endpoint->device->device_ctx->endpoints[id-1].dwendpoint1,
endpoint->device->device_ctx->endpoints[id-1].qwendpoint2);
Ring(endpoint->device->slot, id);
TRACE("Endpoint status 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%016" B_PRIx64 "\n",
endpoint->device->device_ctx->endpoints[id-1].dwendpoint0,
endpoint->device->device_ctx->endpoints[id-1].dwendpoint1,
endpoint->device->device_ctx->endpoints[id-1].qwendpoint2);
return B_OK;
}
status_t
XHCI::SubmitNormalRequest(Transfer *transfer)
{
TRACE("SubmitNormalRequest() length %ld\n", transfer->DataLength());
Pipe *pipe = transfer->TransferPipe();
uint8 id = XHCI_ENDPOINT_ID(pipe);
if (id >= XHCI_MAX_ENDPOINTS)
return B_BAD_VALUE;
bool directionIn = (pipe->Direction() == Pipe::In);
int32 trbCount = 0;
xhci_td *descriptor = CreateDescriptorChain(transfer->DataLength(), trbCount);
if (descriptor == NULL)
return B_NO_MEMORY;
xhci_td *td_chain = descriptor;
xhci_td *last = descriptor;
int32 rest = trbCount - 1;
// set NormalStage
while (td_chain != NULL) {
td_chain->trb_count = td_chain->buffer_count;
uint8 index;
for (index = 0; index < td_chain->buffer_count; index++) {
td_chain->trbs[index].qwtrb0 = descriptor->buffer_phy[index];
td_chain->trbs[index].dwtrb2 = TRB_2_IRQ(0)
| TRB_2_BYTES(descriptor->buffer_size[index])
| TRB_2_TD_SIZE(rest);
td_chain->trbs[index].dwtrb3 = B_HOST_TO_LENDIAN_INT32(
TRB_3_TYPE(TRB_TYPE_NORMAL) | TRB_3_CYCLE_BIT | TRB_3_CHAIN_BIT
| (directionIn ? TRB_3_ISP_BIT : 0));
rest--;
}
// link next td, if any
if (td_chain->next_chain != NULL) {
td_chain->trbs[td_chain->trb_count].qwtrb0 = td_chain->next_chain->this_phy;
td_chain->trbs[td_chain->trb_count].dwtrb2 = TRB_2_IRQ(0);
td_chain->trbs[td_chain->trb_count].dwtrb3
= B_HOST_TO_LENDIAN_INT32(TRB_3_TYPE(TRB_TYPE_LINK)
| TRB_3_CYCLE_BIT | TRB_3_CHAIN_BIT);
}
last = td_chain;
td_chain = td_chain->next_chain;
}
if (last->trb_count > 0) {
last->trbs[last->trb_count - 1].dwtrb3
|= B_HOST_TO_LENDIAN_INT32(TRB_3_IOC_BIT);
last->trbs[last->trb_count - 1].dwtrb3
&= B_HOST_TO_LENDIAN_INT32(~TRB_3_CHAIN_BIT);
}
if (!directionIn) {
TRACE("copying out iov count %ld\n", transfer->VectorCount());
WriteDescriptorChain(descriptor, transfer->Vector(),
transfer->VectorCount());
}
/* memcpy(descriptor->buffer_log[index],
(uint8 *)transfer->Vector()[index].iov_base, transfer->VectorLength());
}*/
xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie();
descriptor->transfer = transfer;
transfer->InitKernelAccess();
_LinkDescriptorForPipe(descriptor, endpoint);
TRACE("SubmitNormalRequest() request linked\n");
TRACE("Endpoint status 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%016" B_PRIx64 "\n",
endpoint->device->device_ctx->endpoints[id - 1].dwendpoint0,
endpoint->device->device_ctx->endpoints[id - 1].dwendpoint1,
endpoint->device->device_ctx->endpoints[id - 1].qwendpoint2);
Ring(endpoint->device->slot, id);
TRACE("Endpoint status 0x%08" B_PRIx32 " 0x%08" B_PRIx32 " 0x%016" B_PRIx64 "\n",
endpoint->device->device_ctx->endpoints[id - 1].dwendpoint0,
endpoint->device->device_ctx->endpoints[id - 1].dwendpoint1,
endpoint->device->device_ctx->endpoints[id - 1].qwendpoint2);
return B_OK;
}
status_t
XHCI::CancelQueuedTransfers(Pipe *pipe, bool force)
{
TRACE_ALWAYS("cancel queued transfers for pipe %p (%d)\n", pipe,
pipe->EndpointAddress());
return B_OK;
}
status_t
XHCI::NotifyPipeChange(Pipe *pipe, usb_change change)
{
TRACE("pipe change %d for pipe %p (%d)\n", change, pipe,
pipe->EndpointAddress());
switch (change) {
case USB_CHANGE_CREATED:
_InsertEndpointForPipe(pipe);
break;
case USB_CHANGE_DESTROYED:
_RemoveEndpointForPipe(pipe);
break;
case USB_CHANGE_PIPE_POLICY_CHANGED: {
// ToDo: for isochronous pipes we might need to adapt to new
// pipe policy settings here
break;
}
}
return B_OK;
}
status_t
XHCI::AddTo(Stack *stack)
{
#ifdef TRACE_USB
set_dprintf_enabled(true);
#endif
if (!sPCIModule) {
status_t status = get_module(B_PCI_MODULE_NAME,
(module_info **)&sPCIModule);
if (status < B_OK) {
TRACE_MODULE_ERROR("getting pci module failed! 0x%08" B_PRIx32
"\n", status);
return status;
}
}
TRACE_MODULE("searching devices\n");
bool found = false;
pci_info *item = new(std::nothrow) pci_info;
if (!item) {
sPCIModule = NULL;
put_module(B_PCI_MODULE_NAME);
return B_NO_MEMORY;
}
// Try to get the PCI x86 module as well so we can enable possible MSIs.
if (sPCIx86Module == NULL && get_module(B_PCI_X86_MODULE_NAME,
(module_info **)&sPCIx86Module) != B_OK) {
// If it isn't there, that's not critical though.
TRACE_MODULE_ERROR("failed to get pci x86 module\n");
sPCIx86Module = NULL;
}
for (int32 i = 0; sPCIModule->get_nth_pci_info(i, item) >= B_OK; i++) {
if (item->class_base == PCI_serial_bus && item->class_sub == PCI_usb
&& item->class_api == PCI_usb_xhci) {
if (item->u.h0.interrupt_line == 0
|| item->u.h0.interrupt_line == 0xFF) {
TRACE_MODULE_ERROR("found device with invalid IRQ - check IRQ "
"assignment\n");
continue;
}
TRACE_MODULE("found device at IRQ %u\n",
item->u.h0.interrupt_line);
XHCI *bus = new(std::nothrow) XHCI(item, stack);
if (!bus) {
delete item;
sPCIModule = NULL;
put_module(B_PCI_MODULE_NAME);
return B_NO_MEMORY;
}
if (bus->InitCheck() < B_OK) {
TRACE_MODULE_ERROR("bus failed init check\n");
delete bus;
continue;
}
// the bus took it away
item = new(std::nothrow) pci_info;
bus->Start();
stack->AddBusManager(bus);
found = true;
}
}
if (!found) {
TRACE_MODULE_ERROR("no devices found\n");
delete item;
sPCIModule = NULL;
put_module(B_PCI_MODULE_NAME);
return ENODEV;
}
delete item;
return B_OK;
}
xhci_td *
XHCI::CreateDescriptorChain(size_t bufferSize, int32 &trbCount)
{
size_t packetSize = B_PAGE_SIZE * 16;
trbCount = (bufferSize + packetSize - 1) / packetSize;
// keep one trb for linking
int32 tdCount = (trbCount + XHCI_MAX_TRBS_PER_TD - 2)
/ (XHCI_MAX_TRBS_PER_TD - 1);
xhci_td *first = NULL;
xhci_td *last = NULL;
for (int32 i = 0; i < tdCount; i++) {
xhci_td *descriptor = CreateDescriptor(0);
if (!descriptor) {
if (first != NULL)
FreeDescriptor(first);
return NULL;
} else if (first == NULL)
first = descriptor;
uint8 trbs = min_c(trbCount, XHCI_MAX_TRBS_PER_TD - 1);
TRACE("CreateDescriptorChain trbs %d for td %" B_PRId32 "\n", trbs, i);
for (int j = 0; j < trbs; j++) {
if (fStack->AllocateChunk(&descriptor->buffer_log[j],
&descriptor->buffer_phy[j],
min_c(packetSize, bufferSize)) < B_OK) {
TRACE_ERROR("unable to allocate space for the buffer (size %"
B_PRIuSIZE ")\n", bufferSize);
return NULL;
}
descriptor->buffer_size[j] = min_c(packetSize, bufferSize);
bufferSize -= descriptor->buffer_size[j];
TRACE("CreateDescriptorChain allocated %ld for trb %d\n",
descriptor->buffer_size[j], j);
}
descriptor->buffer_count = trbs;
trbCount -= trbs;
if (last != NULL)
last->next_chain = descriptor;
last = descriptor;
}
return first;
}
xhci_td *
XHCI::CreateDescriptor(size_t bufferSize)
{
xhci_td *result;
phys_addr_t physicalAddress;
if (fStack->AllocateChunk((void **)&result, &physicalAddress,
sizeof(xhci_td)) < B_OK) {
TRACE_ERROR("failed to allocate a transfer descriptor\n");
return NULL;
}
result->this_phy = physicalAddress;
result->buffer_size[0] = bufferSize;
result->trb_count = 0;
result->buffer_count = 1;
result->next = NULL;
result->next_chain = NULL;
if (bufferSize <= 0) {
result->buffer_log[0] = NULL;
result->buffer_phy[0] = 0;
return result;
}
if (fStack->AllocateChunk(&result->buffer_log[0],
&result->buffer_phy[0], bufferSize) < B_OK) {
TRACE_ERROR("unable to allocate space for the buffer (size %ld)\n",
bufferSize);
fStack->FreeChunk(result, result->this_phy, sizeof(xhci_td));
return NULL;
}
TRACE("CreateDescriptor allocated buffer_size %ld %p\n",
result->buffer_size[0], result->buffer_log[0]);
return result;
}
void
XHCI::FreeDescriptor(xhci_td *descriptor)
{
while (descriptor != NULL) {
for (int i = 0; i < descriptor->buffer_count; i++) {
if (descriptor->buffer_size[i] == 0)
continue;
TRACE("FreeDescriptor buffer %d buffer_size %ld %p\n", i,
descriptor->buffer_size[i], descriptor->buffer_log[i]);
fStack->FreeChunk(descriptor->buffer_log[i],
descriptor->buffer_phy[i], descriptor->buffer_size[i]);
}
xhci_td *next = descriptor->next_chain;
fStack->FreeChunk(descriptor, descriptor->this_phy,
sizeof(xhci_td));
descriptor = next;
}
}
size_t
XHCI::WriteDescriptorChain(xhci_td *descriptor, iovec *vector,
size_t vectorCount)
{
xhci_td *current = descriptor;
uint8 trbIndex = 0;
size_t actualLength = 0;
uint8 vectorIndex = 0;
size_t vectorOffset = 0;
size_t bufferOffset = 0;
while (current != NULL) {
if (current->buffer_log == NULL)
break;
while (true) {
size_t length = min_c(current->buffer_size[trbIndex] - bufferOffset,
vector[vectorIndex].iov_len - vectorOffset);
TRACE("copying %ld bytes to bufferOffset %ld from"
" vectorOffset %ld at index %d of %ld\n", length, bufferOffset,
vectorOffset, vectorIndex, vectorCount);
memcpy((uint8 *)current->buffer_log[trbIndex] + bufferOffset,
(uint8 *)vector[vectorIndex].iov_base + vectorOffset, length);