/
arch_cpu.cpp
1696 lines (1407 loc) · 50.6 KB
/
arch_cpu.cpp
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/*
* Copyright 2018, Jérôme Duval, jerome.duval@gmail.com.
* Copyright 2002-2010, Axel Dörfler, axeld@pinc-software.de.
* Copyright 2013, Paweł Dziepak, pdziepak@quarnos.org.
* Copyright 2012, Alex Smith, alex@alex-smith.me.uk.
* Distributed under the terms of the MIT License.
*
* Copyright 2001-2002, Travis Geiselbrecht. All rights reserved.
* Distributed under the terms of the NewOS License.
*/
#include <cpu.h>
#include <string.h>
#include <stdlib.h>
#include <stdio.h>
#include <algorithm>
#include <ACPI.h>
#include <boot_device.h>
#include <commpage.h>
#include <debug.h>
#include <elf.h>
#include <safemode.h>
#include <smp.h>
#include <util/BitUtils.h>
#include <vm/vm.h>
#include <vm/vm_types.h>
#include <vm/VMAddressSpace.h>
#include <arch_system_info.h>
#include <arch/x86/apic.h>
#include <boot/kernel_args.h>
#include "paging/X86PagingStructures.h"
#include "paging/X86VMTranslationMap.h"
#define DUMP_FEATURE_STRING 1
#define DUMP_CPU_TOPOLOGY 1
#define DUMP_CPU_PATCHLEVEL 1
/* cpu vendor info */
struct cpu_vendor_info {
const char *vendor;
const char *ident_string[2];
};
static const struct cpu_vendor_info vendor_info[VENDOR_NUM] = {
{ "Intel", { "GenuineIntel" } },
{ "AMD", { "AuthenticAMD" } },
{ "Cyrix", { "CyrixInstead" } },
{ "UMC", { "UMC UMC UMC" } },
{ "NexGen", { "NexGenDriven" } },
{ "Centaur", { "CentaurHauls" } },
{ "Rise", { "RiseRiseRise" } },
{ "Transmeta", { "GenuineTMx86", "TransmetaCPU" } },
{ "NSC", { "Geode by NSC" } },
{ "Hygon", { "HygonGenuine" } },
};
#define K8_SMIONCMPHALT (1ULL << 27)
#define K8_C1EONCMPHALT (1ULL << 28)
#define K8_CMPHALT (K8_SMIONCMPHALT | K8_C1EONCMPHALT)
struct set_mtrr_parameter {
int32 index;
uint64 base;
uint64 length;
uint8 type;
};
struct set_mtrrs_parameter {
const x86_mtrr_info* infos;
uint32 count;
uint8 defaultType;
};
#ifdef __x86_64__
extern addr_t _stac;
extern addr_t _clac;
extern addr_t _xsave;
extern addr_t _xsavec;
extern addr_t _xrstor;
uint64 gXsaveMask;
uint64 gFPUSaveLength = 512;
bool gHasXsave = false;
bool gHasXsavec = false;
#endif
extern "C" void x86_reboot(void);
// from arch.S
void (*gCpuIdleFunc)(void);
#ifndef __x86_64__
void (*gX86SwapFPUFunc)(void* oldState, const void* newState) = x86_noop_swap;
bool gHasSSE = false;
#endif
static uint32 sCpuRendezvous;
static uint32 sCpuRendezvous2;
static uint32 sCpuRendezvous3;
static vint32 sTSCSyncRendezvous;
/* Some specials for the double fault handler */
static uint8* sDoubleFaultStacks;
static const size_t kDoubleFaultStackSize = 4096; // size per CPU
static x86_cpu_module_info* sCpuModule;
/* CPU topology information */
static uint32 (*sGetCPUTopologyID)(int currentCPU);
static uint32 sHierarchyMask[CPU_TOPOLOGY_LEVELS];
static uint32 sHierarchyShift[CPU_TOPOLOGY_LEVELS];
/* Cache topology information */
static uint32 sCacheSharingMask[CPU_MAX_CACHE_LEVEL];
static void* sUcodeData = NULL;
static size_t sUcodeDataSize = 0;
static struct intel_microcode_header* sLoadedUcodeUpdate;
static spinlock sUcodeUpdateLock = B_SPINLOCK_INITIALIZER;
static status_t
acpi_shutdown(bool rebootSystem)
{
if (debug_debugger_running() || !are_interrupts_enabled())
return B_ERROR;
acpi_module_info* acpi;
if (get_module(B_ACPI_MODULE_NAME, (module_info**)&acpi) != B_OK)
return B_NOT_SUPPORTED;
status_t status;
if (rebootSystem) {
status = acpi->reboot();
} else {
status = acpi->prepare_sleep_state(ACPI_POWER_STATE_OFF, NULL, 0);
if (status == B_OK) {
//cpu_status state = disable_interrupts();
status = acpi->enter_sleep_state(ACPI_POWER_STATE_OFF);
//restore_interrupts(state);
}
}
put_module(B_ACPI_MODULE_NAME);
return status;
}
/*! Disable CPU caches, and invalidate them. */
static void
disable_caches()
{
x86_write_cr0((x86_read_cr0() | CR0_CACHE_DISABLE)
& ~CR0_NOT_WRITE_THROUGH);
wbinvd();
arch_cpu_global_TLB_invalidate();
}
/*! Invalidate CPU caches, and enable them. */
static void
enable_caches()
{
wbinvd();
arch_cpu_global_TLB_invalidate();
x86_write_cr0(x86_read_cr0()
& ~(CR0_CACHE_DISABLE | CR0_NOT_WRITE_THROUGH));
}
static void
set_mtrr(void* _parameter, int cpu)
{
struct set_mtrr_parameter* parameter
= (struct set_mtrr_parameter*)_parameter;
// wait until all CPUs have arrived here
smp_cpu_rendezvous(&sCpuRendezvous);
// One CPU has to reset sCpuRendezvous3 -- it is needed to prevent the CPU
// that initiated the call_all_cpus() from doing that again and clearing
// sCpuRendezvous2 before the last CPU has actually left the loop in
// smp_cpu_rendezvous();
if (cpu == 0)
atomic_set((int32*)&sCpuRendezvous3, 0);
disable_caches();
sCpuModule->set_mtrr(parameter->index, parameter->base, parameter->length,
parameter->type);
enable_caches();
// wait until all CPUs have arrived here
smp_cpu_rendezvous(&sCpuRendezvous2);
smp_cpu_rendezvous(&sCpuRendezvous3);
}
static void
set_mtrrs(void* _parameter, int cpu)
{
set_mtrrs_parameter* parameter = (set_mtrrs_parameter*)_parameter;
// wait until all CPUs have arrived here
smp_cpu_rendezvous(&sCpuRendezvous);
// One CPU has to reset sCpuRendezvous3 -- it is needed to prevent the CPU
// that initiated the call_all_cpus() from doing that again and clearing
// sCpuRendezvous2 before the last CPU has actually left the loop in
// smp_cpu_rendezvous();
if (cpu == 0)
atomic_set((int32*)&sCpuRendezvous3, 0);
disable_caches();
sCpuModule->set_mtrrs(parameter->defaultType, parameter->infos,
parameter->count);
enable_caches();
// wait until all CPUs have arrived here
smp_cpu_rendezvous(&sCpuRendezvous2);
smp_cpu_rendezvous(&sCpuRendezvous3);
}
static void
init_mtrrs(void* _unused, int cpu)
{
// wait until all CPUs have arrived here
smp_cpu_rendezvous(&sCpuRendezvous);
// One CPU has to reset sCpuRendezvous3 -- it is needed to prevent the CPU
// that initiated the call_all_cpus() from doing that again and clearing
// sCpuRendezvous2 before the last CPU has actually left the loop in
// smp_cpu_rendezvous();
if (cpu == 0)
atomic_set((int32*)&sCpuRendezvous3, 0);
disable_caches();
sCpuModule->init_mtrrs();
enable_caches();
// wait until all CPUs have arrived here
smp_cpu_rendezvous(&sCpuRendezvous2);
smp_cpu_rendezvous(&sCpuRendezvous3);
}
uint32
x86_count_mtrrs(void)
{
if (sCpuModule == NULL)
return 0;
return sCpuModule->count_mtrrs();
}
void
x86_set_mtrr(uint32 index, uint64 base, uint64 length, uint8 type)
{
struct set_mtrr_parameter parameter;
parameter.index = index;
parameter.base = base;
parameter.length = length;
parameter.type = type;
sCpuRendezvous = sCpuRendezvous2 = 0;
call_all_cpus(&set_mtrr, ¶meter);
}
status_t
x86_get_mtrr(uint32 index, uint64* _base, uint64* _length, uint8* _type)
{
// the MTRRs are identical on all CPUs, so it doesn't matter
// on which CPU this runs
return sCpuModule->get_mtrr(index, _base, _length, _type);
}
void
x86_set_mtrrs(uint8 defaultType, const x86_mtrr_info* infos, uint32 count)
{
if (sCpuModule == NULL)
return;
struct set_mtrrs_parameter parameter;
parameter.defaultType = defaultType;
parameter.infos = infos;
parameter.count = count;
sCpuRendezvous = sCpuRendezvous2 = 0;
call_all_cpus(&set_mtrrs, ¶meter);
}
void
x86_init_fpu(void)
{
// All x86_64 CPUs support SSE, don't need to bother checking for it.
#ifndef __x86_64__
if (!x86_check_feature(IA32_FEATURE_FPU, FEATURE_COMMON)) {
// No FPU... time to install one in your 386?
dprintf("%s: Warning: CPU has no reported FPU.\n", __func__);
gX86SwapFPUFunc = x86_noop_swap;
return;
}
if (!x86_check_feature(IA32_FEATURE_SSE, FEATURE_COMMON)
|| !x86_check_feature(IA32_FEATURE_FXSR, FEATURE_COMMON)) {
dprintf("%s: CPU has no SSE... just enabling FPU.\n", __func__);
// we don't have proper SSE support, just enable FPU
x86_write_cr0(x86_read_cr0() & ~(CR0_FPU_EMULATION | CR0_MONITOR_FPU));
gX86SwapFPUFunc = x86_fnsave_swap;
return;
}
#endif
dprintf("%s: CPU has SSE... enabling FXSR and XMM.\n", __func__);
#ifndef __x86_64__
// enable OS support for SSE
x86_write_cr4(x86_read_cr4() | CR4_OS_FXSR | CR4_OS_XMM_EXCEPTION);
x86_write_cr0(x86_read_cr0() & ~(CR0_FPU_EMULATION | CR0_MONITOR_FPU));
gX86SwapFPUFunc = x86_fxsave_swap;
gHasSSE = true;
#endif
}
#if DUMP_FEATURE_STRING
static void
dump_feature_string(int currentCPU, cpu_ent* cpu)
{
char features[512];
features[0] = 0;
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_FPU)
strlcat(features, "fpu ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_VME)
strlcat(features, "vme ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_DE)
strlcat(features, "de ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PSE)
strlcat(features, "pse ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_TSC)
strlcat(features, "tsc ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_MSR)
strlcat(features, "msr ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PAE)
strlcat(features, "pae ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_MCE)
strlcat(features, "mce ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_CX8)
strlcat(features, "cx8 ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_APIC)
strlcat(features, "apic ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_SEP)
strlcat(features, "sep ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_MTRR)
strlcat(features, "mtrr ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PGE)
strlcat(features, "pge ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_MCA)
strlcat(features, "mca ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_CMOV)
strlcat(features, "cmov ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PAT)
strlcat(features, "pat ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PSE36)
strlcat(features, "pse36 ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PSN)
strlcat(features, "psn ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_CLFSH)
strlcat(features, "clfsh ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_DS)
strlcat(features, "ds ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_ACPI)
strlcat(features, "acpi ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_MMX)
strlcat(features, "mmx ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_FXSR)
strlcat(features, "fxsr ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_SSE)
strlcat(features, "sse ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_SSE2)
strlcat(features, "sse2 ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_SS)
strlcat(features, "ss ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_HTT)
strlcat(features, "htt ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_TM)
strlcat(features, "tm ", sizeof(features));
if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_PBE)
strlcat(features, "pbe ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_SSE3)
strlcat(features, "sse3 ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_PCLMULQDQ)
strlcat(features, "pclmulqdq ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_DTES64)
strlcat(features, "dtes64 ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_MONITOR)
strlcat(features, "monitor ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_DSCPL)
strlcat(features, "dscpl ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_VMX)
strlcat(features, "vmx ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_SMX)
strlcat(features, "smx ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_EST)
strlcat(features, "est ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_TM2)
strlcat(features, "tm2 ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_SSSE3)
strlcat(features, "ssse3 ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_CNXTID)
strlcat(features, "cnxtid ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_FMA)
strlcat(features, "fma ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_CX16)
strlcat(features, "cx16 ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_XTPR)
strlcat(features, "xtpr ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_PDCM)
strlcat(features, "pdcm ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_PCID)
strlcat(features, "pcid ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_DCA)
strlcat(features, "dca ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_SSE4_1)
strlcat(features, "sse4_1 ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_SSE4_2)
strlcat(features, "sse4_2 ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_X2APIC)
strlcat(features, "x2apic ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_MOVBE)
strlcat(features, "movbe ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_POPCNT)
strlcat(features, "popcnt ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_TSCDEADLINE)
strlcat(features, "tscdeadline ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_AES)
strlcat(features, "aes ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_XSAVE)
strlcat(features, "xsave ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_OSXSAVE)
strlcat(features, "osxsave ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_AVX)
strlcat(features, "avx ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_F16C)
strlcat(features, "f16c ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_RDRND)
strlcat(features, "rdrnd ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_HYPERVISOR)
strlcat(features, "hypervisor ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_SYSCALL)
strlcat(features, "syscall ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_NX)
strlcat(features, "nx ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_MMXEXT)
strlcat(features, "mmxext ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_FFXSR)
strlcat(features, "ffxsr ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_PDPE1GB)
strlcat(features, "pdpe1gb ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_LONG)
strlcat(features, "long ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_3DNOWEXT)
strlcat(features, "3dnowext ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT_AMD] & IA32_FEATURE_AMD_EXT_3DNOW)
strlcat(features, "3dnow ", sizeof(features));
if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_DTS)
strlcat(features, "dts ", sizeof(features));
if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_ITB)
strlcat(features, "itb ", sizeof(features));
if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_ARAT)
strlcat(features, "arat ", sizeof(features));
if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_PLN)
strlcat(features, "pln ", sizeof(features));
if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_ECMD)
strlcat(features, "ecmd ", sizeof(features));
if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_PTM)
strlcat(features, "ptm ", sizeof(features));
if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP)
strlcat(features, "hwp ", sizeof(features));
if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_NOTIFY)
strlcat(features, "hwp_notify ", sizeof(features));
if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_ACTWIN)
strlcat(features, "hwp_actwin ", sizeof(features));
if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_EPP)
strlcat(features, "hwp_epp ", sizeof(features));
if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_PLR)
strlcat(features, "hwp_plr ", sizeof(features));
if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HDC)
strlcat(features, "hdc ", sizeof(features));
if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_TBMT3)
strlcat(features, "tbmt3 ", sizeof(features));
if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_CAP)
strlcat(features, "hwp_cap ", sizeof(features));
if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_PECI)
strlcat(features, "hwp_peci ", sizeof(features));
if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_FLEX)
strlcat(features, "hwp_flex ", sizeof(features));
if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_FAST)
strlcat(features, "hwp_fast ", sizeof(features));
if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HW_FEEDBACK)
strlcat(features, "hw_feedback ", sizeof(features));
if (cpu->arch.feature[FEATURE_6_EAX] & IA32_FEATURE_HWP_IGNIDL)
strlcat(features, "hwp_ignidl ", sizeof(features));
if (cpu->arch.feature[FEATURE_6_ECX] & IA32_FEATURE_APERFMPERF)
strlcat(features, "aperfmperf ", sizeof(features));
if (cpu->arch.feature[FEATURE_6_ECX] & IA32_FEATURE_EPB)
strlcat(features, "epb ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_TSC_ADJUST)
strlcat(features, "tsc_adjust ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_SGX)
strlcat(features, "sgx ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_BMI1)
strlcat(features, "bmi1 ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_HLE)
strlcat(features, "hle ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX2)
strlcat(features, "avx2 ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_SMEP)
strlcat(features, "smep ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_BMI2)
strlcat(features, "bmi2 ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_ERMS)
strlcat(features, "erms ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_INVPCID)
strlcat(features, "invpcid ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_RTM)
strlcat(features, "rtm ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_CQM)
strlcat(features, "cqm ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_MPX)
strlcat(features, "mpx ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_RDT_A)
strlcat(features, "rdt_a ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512F)
strlcat(features, "avx512f ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512DQ)
strlcat(features, "avx512dq ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_RDSEED)
strlcat(features, "rdseed ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_ADX)
strlcat(features, "adx ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_SMAP)
strlcat(features, "smap ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512IFMA)
strlcat(features, "avx512ifma ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_PCOMMIT)
strlcat(features, "pcommit ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_CLFLUSHOPT)
strlcat(features, "cflushopt ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_CLWB)
strlcat(features, "clwb ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_INTEL_PT)
strlcat(features, "intel_pt ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512PF)
strlcat(features, "avx512pf ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512ER)
strlcat(features, "avx512er ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512CD)
strlcat(features, "avx512cd ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_SHA_NI)
strlcat(features, "sha_ni ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512BW)
strlcat(features, "avx512bw ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EBX] & IA32_FEATURE_AVX512VI)
strlcat(features, "avx512vi ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_AVX512VMBI)
strlcat(features, "avx512vmbi ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_UMIP)
strlcat(features, "umip ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_PKU)
strlcat(features, "pku ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_OSPKE)
strlcat(features, "ospke ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_AVX512VMBI2)
strlcat(features, "avx512vmbi2 ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_GFNI)
strlcat(features, "gfni ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_VAES)
strlcat(features, "vaes ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_VPCLMULQDQ)
strlcat(features, "vpclmulqdq ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_AVX512_VNNI)
strlcat(features, "avx512vnni ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_AVX512_BITALG)
strlcat(features, "avx512bitalg ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_AVX512_VPOPCNTDQ)
strlcat(features, "avx512vpopcntdq ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_LA57)
strlcat(features, "la57 ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_RDPID)
strlcat(features, "rdpid ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_SGX_LC)
strlcat(features, "sgx_lc ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_IBRS)
strlcat(features, "ibrs ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_STIBP)
strlcat(features, "stibp ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_L1D_FLUSH)
strlcat(features, "l1d_flush ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_ARCH_CAPABILITIES)
strlcat(features, "msr_arch ", sizeof(features));
if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_SSBD)
strlcat(features, "ssbd ", sizeof(features));
if (cpu->arch.feature[FEATURE_D_1_EAX] & IA32_FEATURE_XSAVEOPT)
strlcat(features, "xsaveopt ", sizeof(features));
if (cpu->arch.feature[FEATURE_D_1_EAX] & IA32_FEATURE_XSAVEC)
strlcat(features, "xsavec ", sizeof(features));
if (cpu->arch.feature[FEATURE_D_1_EAX] & IA32_FEATURE_XGETBV1)
strlcat(features, "xgetbv1 ", sizeof(features));
if (cpu->arch.feature[FEATURE_D_1_EAX] & IA32_FEATURE_XSAVES)
strlcat(features, "xsaves ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT_8_EBX] & IA32_FEATURE_CLZERO)
strlcat(features, "clzero ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT_8_EBX] & IA32_FEATURE_IBPB)
strlcat(features, "ibpb ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT_8_EBX] & IA32_FEATURE_AMD_SSBD)
strlcat(features, "amd_ssbd ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT_8_EBX] & IA32_FEATURE_VIRT_SSBD)
strlcat(features, "virt_ssbd ", sizeof(features));
if (cpu->arch.feature[FEATURE_EXT_8_EBX] & IA32_FEATURE_AMD_SSB_NO)
strlcat(features, "amd_ssb_no ", sizeof(features));
dprintf("CPU %d: features: %s\n", currentCPU, features);
}
#endif // DUMP_FEATURE_STRING
static void
compute_cpu_hierarchy_masks(int maxLogicalID, int maxCoreID)
{
ASSERT(maxLogicalID >= maxCoreID);
const int kMaxSMTID = maxLogicalID / maxCoreID;
sHierarchyMask[CPU_TOPOLOGY_SMT] = kMaxSMTID - 1;
sHierarchyShift[CPU_TOPOLOGY_SMT] = 0;
sHierarchyMask[CPU_TOPOLOGY_CORE] = (maxCoreID - 1) * kMaxSMTID;
sHierarchyShift[CPU_TOPOLOGY_CORE]
= count_set_bits(sHierarchyMask[CPU_TOPOLOGY_SMT]);
const uint32 kSinglePackageMask = sHierarchyMask[CPU_TOPOLOGY_SMT]
| sHierarchyMask[CPU_TOPOLOGY_CORE];
sHierarchyMask[CPU_TOPOLOGY_PACKAGE] = ~kSinglePackageMask;
sHierarchyShift[CPU_TOPOLOGY_PACKAGE] = count_set_bits(kSinglePackageMask);
}
static uint32
get_cpu_legacy_initial_apic_id(int /* currentCPU */)
{
cpuid_info cpuid;
get_current_cpuid(&cpuid, 1, 0);
return cpuid.regs.ebx >> 24;
}
static inline status_t
detect_amd_cpu_topology(uint32 maxBasicLeaf, uint32 maxExtendedLeaf)
{
sGetCPUTopologyID = get_cpu_legacy_initial_apic_id;
cpuid_info cpuid;
get_current_cpuid(&cpuid, 1, 0);
int maxLogicalID = next_power_of_2((cpuid.regs.ebx >> 16) & 0xff);
int maxCoreID = 1;
if (maxExtendedLeaf >= 0x80000008) {
get_current_cpuid(&cpuid, 0x80000008, 0);
maxCoreID = (cpuid.regs.ecx >> 12) & 0xf;
if (maxCoreID != 0)
maxCoreID = 1 << maxCoreID;
else
maxCoreID = next_power_of_2((cpuid.regs.edx & 0xf) + 1);
}
if (maxExtendedLeaf >= 0x80000001) {
get_current_cpuid(&cpuid, 0x80000001, 0);
if (x86_check_feature(IA32_FEATURE_AMD_EXT_CMPLEGACY,
FEATURE_EXT_AMD_ECX))
maxCoreID = maxLogicalID;
}
compute_cpu_hierarchy_masks(maxLogicalID, maxCoreID);
return B_OK;
}
static void
detect_amd_cache_topology(uint32 maxExtendedLeaf)
{
if (!x86_check_feature(IA32_FEATURE_AMD_EXT_TOPOLOGY, FEATURE_EXT_AMD_ECX))
return;
if (maxExtendedLeaf < 0x8000001d)
return;
uint8 hierarchyLevels[CPU_MAX_CACHE_LEVEL];
int maxCacheLevel = 0;
int currentLevel = 0;
int cacheType;
do {
cpuid_info cpuid;
get_current_cpuid(&cpuid, 0x8000001d, currentLevel);
cacheType = cpuid.regs.eax & 0x1f;
if (cacheType == 0)
break;
int cacheLevel = (cpuid.regs.eax >> 5) & 0x7;
int coresCount = next_power_of_2(((cpuid.regs.eax >> 14) & 0x3f) + 1);
hierarchyLevels[cacheLevel - 1]
= coresCount * (sHierarchyMask[CPU_TOPOLOGY_SMT] + 1);
maxCacheLevel = std::max(maxCacheLevel, cacheLevel);
currentLevel++;
} while (true);
for (int i = 0; i < maxCacheLevel; i++)
sCacheSharingMask[i] = ~uint32(hierarchyLevels[i] - 1);
gCPUCacheLevelCount = maxCacheLevel;
}
static uint32
get_intel_cpu_initial_x2apic_id(int /* currentCPU */)
{
cpuid_info cpuid;
get_current_cpuid(&cpuid, 11, 0);
return cpuid.regs.edx;
}
static inline status_t
detect_intel_cpu_topology_x2apic(uint32 maxBasicLeaf)
{
if (maxBasicLeaf < 11)
return B_UNSUPPORTED;
uint8 hierarchyLevels[CPU_TOPOLOGY_LEVELS] = { 0 };
int currentLevel = 0;
int levelType;
unsigned int levelsSet = 0;
do {
cpuid_info cpuid;
get_current_cpuid(&cpuid, 11, currentLevel);
if (currentLevel == 0 && cpuid.regs.ebx == 0)
return B_UNSUPPORTED;
levelType = (cpuid.regs.ecx >> 8) & 0xff;
int levelValue = cpuid.regs.eax & 0x1f;
switch (levelType) {
case 1: // SMT
hierarchyLevels[CPU_TOPOLOGY_SMT] = levelValue;
levelsSet |= 1;
break;
case 2: // core
hierarchyLevels[CPU_TOPOLOGY_CORE] = levelValue;
levelsSet |= 2;
break;
}
currentLevel++;
} while (levelType != 0 && levelsSet != 3);
sGetCPUTopologyID = get_intel_cpu_initial_x2apic_id;
for (int i = 1; i < CPU_TOPOLOGY_LEVELS; i++) {
if ((levelsSet & (1u << i)) != 0)
continue;
hierarchyLevels[i] = hierarchyLevels[i - 1];
}
for (int i = 0; i < CPU_TOPOLOGY_LEVELS; i++) {
uint32 mask = ~uint32(0);
if (i < CPU_TOPOLOGY_LEVELS - 1)
mask = (1u << hierarchyLevels[i]) - 1;
if (i > 0)
mask &= ~sHierarchyMask[i - 1];
sHierarchyMask[i] = mask;
sHierarchyShift[i] = i > 0 ? hierarchyLevels[i - 1] : 0;
}
return B_OK;
}
static inline status_t
detect_intel_cpu_topology_legacy(uint32 maxBasicLeaf)
{
sGetCPUTopologyID = get_cpu_legacy_initial_apic_id;
cpuid_info cpuid;
get_current_cpuid(&cpuid, 1, 0);
int maxLogicalID = next_power_of_2((cpuid.regs.ebx >> 16) & 0xff);
int maxCoreID = 1;
if (maxBasicLeaf >= 4) {
get_current_cpuid(&cpuid, 4, 0);
maxCoreID = next_power_of_2((cpuid.regs.eax >> 26) + 1);
}
compute_cpu_hierarchy_masks(maxLogicalID, maxCoreID);
return B_OK;
}
static void
detect_intel_cache_topology(uint32 maxBasicLeaf)
{
if (maxBasicLeaf < 4)
return;
uint8 hierarchyLevels[CPU_MAX_CACHE_LEVEL];
int maxCacheLevel = 0;
int currentLevel = 0;
int cacheType;
do {
cpuid_info cpuid;
get_current_cpuid(&cpuid, 4, currentLevel);
cacheType = cpuid.regs.eax & 0x1f;
if (cacheType == 0)
break;
int cacheLevel = (cpuid.regs.eax >> 5) & 0x7;
hierarchyLevels[cacheLevel - 1]
= next_power_of_2(((cpuid.regs.eax >> 14) & 0x3f) + 1);
maxCacheLevel = std::max(maxCacheLevel, cacheLevel);
currentLevel++;
} while (true);
for (int i = 0; i < maxCacheLevel; i++)
sCacheSharingMask[i] = ~uint32(hierarchyLevels[i] - 1);
gCPUCacheLevelCount = maxCacheLevel;
}
static uint32
get_simple_cpu_topology_id(int currentCPU)
{
return currentCPU;
}
static inline int
get_topology_level_id(uint32 id, cpu_topology_level level)
{
ASSERT(level < CPU_TOPOLOGY_LEVELS);
return (id & sHierarchyMask[level]) >> sHierarchyShift[level];
}
static void
detect_cpu_topology(int currentCPU, cpu_ent* cpu, uint32 maxBasicLeaf,
uint32 maxExtendedLeaf)
{
if (currentCPU == 0) {
memset(sCacheSharingMask, 0xff, sizeof(sCacheSharingMask));
status_t result = B_UNSUPPORTED;
if (x86_check_feature(IA32_FEATURE_HTT, FEATURE_COMMON)) {
if (cpu->arch.vendor == VENDOR_AMD
|| cpu->arch.vendor == VENDOR_HYGON) {
result = detect_amd_cpu_topology(maxBasicLeaf, maxExtendedLeaf);
if (result == B_OK)
detect_amd_cache_topology(maxExtendedLeaf);
}
if (cpu->arch.vendor == VENDOR_INTEL) {
result = detect_intel_cpu_topology_x2apic(maxBasicLeaf);
if (result != B_OK)
result = detect_intel_cpu_topology_legacy(maxBasicLeaf);
if (result == B_OK)
detect_intel_cache_topology(maxBasicLeaf);
}
}
if (result != B_OK) {
dprintf("No CPU topology information available.\n");
sGetCPUTopologyID = get_simple_cpu_topology_id;
sHierarchyMask[CPU_TOPOLOGY_PACKAGE] = ~uint32(0);
}
}
ASSERT(sGetCPUTopologyID != NULL);
int topologyID = sGetCPUTopologyID(currentCPU);
cpu->topology_id[CPU_TOPOLOGY_SMT]
= get_topology_level_id(topologyID, CPU_TOPOLOGY_SMT);
cpu->topology_id[CPU_TOPOLOGY_CORE]
= get_topology_level_id(topologyID, CPU_TOPOLOGY_CORE);
cpu->topology_id[CPU_TOPOLOGY_PACKAGE]
= get_topology_level_id(topologyID, CPU_TOPOLOGY_PACKAGE);
unsigned int i;
for (i = 0; i < gCPUCacheLevelCount; i++)
cpu->cache_id[i] = topologyID & sCacheSharingMask[i];
for (; i < CPU_MAX_CACHE_LEVEL; i++)
cpu->cache_id[i] = -1;
#if DUMP_CPU_TOPOLOGY
dprintf("CPU %d: apic id %d, package %d, core %d, smt %d\n", currentCPU,
topologyID, cpu->topology_id[CPU_TOPOLOGY_PACKAGE],
cpu->topology_id[CPU_TOPOLOGY_CORE],
cpu->topology_id[CPU_TOPOLOGY_SMT]);
if (gCPUCacheLevelCount > 0) {
char cacheLevels[256];
unsigned int offset = 0;
for (i = 0; i < gCPUCacheLevelCount; i++) {
offset += snprintf(cacheLevels + offset,
sizeof(cacheLevels) - offset,
" L%d id %d%s", i + 1, cpu->cache_id[i],
i < gCPUCacheLevelCount - 1 ? "," : "");
if (offset >= sizeof(cacheLevels))
break;
}
dprintf("CPU %d: cache sharing:%s\n", currentCPU, cacheLevels);
}
#endif
}
static void
detect_intel_patch_level(cpu_ent* cpu)
{
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_HYPERVISOR) {
cpu->arch.patch_level = 0;
return;
}
x86_write_msr(IA32_MSR_UCODE_REV, 0);
cpuid_info cpuid;
get_current_cpuid(&cpuid, 1, 0);
uint64 value = x86_read_msr(IA32_MSR_UCODE_REV);
cpu->arch.patch_level = value >> 32;
}
static void
detect_amd_patch_level(cpu_ent* cpu)
{
if (cpu->arch.feature[FEATURE_EXT] & IA32_FEATURE_EXT_HYPERVISOR) {
cpu->arch.patch_level = 0;
return;
}
uint64 value = x86_read_msr(IA32_MSR_UCODE_REV);
cpu->arch.patch_level = value >> 32;
}
static struct intel_microcode_header*
find_microcode_intel(addr_t data, size_t size, uint32 patchLevel)
{
// 9.11.3 Processor Identification
cpuid_info cpuid;
get_current_cpuid(&cpuid, 1, 0);
uint32 signature = cpuid.regs.eax;
// 9.11.4 Platform Identification
uint64 platformBits = (x86_read_msr(IA32_MSR_PLATFORM_ID) >> 50) & 0x7;
uint64 mask = 1 << platformBits;
while (size > 0) {