-
Notifications
You must be signed in to change notification settings - Fork 1.1k
/
CodeGen_X86.cpp
684 lines (580 loc) · 23.6 KB
/
CodeGen_X86.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
#include <iostream>
#include "CodeGen_X86.h"
#include "JITModule.h"
#include "IROperator.h"
#include "IRMatch.h"
#include "Debug.h"
#include "Util.h"
#include "Var.h"
#include "Param.h"
#include "IntegerDivisionTable.h"
#include "LLVM_Headers.h"
#include "IRMutator.h"
namespace Halide {
namespace Internal {
using std::vector;
using std::string;
using namespace llvm;
CodeGen_X86::CodeGen_X86(Target t) : CodeGen_Posix(t) {
#if !(WITH_X86)
user_error << "x86 not enabled for this build of Halide.\n";
#endif
user_assert(llvm_X86_enabled) << "llvm build not configured with X86 target enabled.\n";
#if !(WITH_NATIVE_CLIENT)
user_assert(t.os != Target::NaCl) << "llvm build not configured with native client enabled.\n";
#endif
}
Expr _i64(Expr e) {
return cast(Int(64, e.type().width), e);
}
Expr _u64(Expr e) {
return cast(UInt(64, e.type().width), e);
}
Expr _i32(Expr e) {
return cast(Int(32, e.type().width), e);
}
Expr _u32(Expr e) {
return cast(UInt(32, e.type().width), e);
}
Expr _i16(Expr e) {
return cast(Int(16, e.type().width), e);
}
Expr _u16(Expr e) {
return cast(UInt(16, e.type().width), e);
}
Expr _i8(Expr e) {
return cast(Int(8, e.type().width), e);
}
Expr _u8(Expr e) {
return cast(UInt(8, e.type().width), e);
}
Expr _f32(Expr e) {
return cast(Float(32, e.type().width), e);
}
Expr _f64(Expr e) {
return cast(Float(64, e.type().width), e);
}
namespace {
// Attempt to cast an expression to a smaller type while provably not
// losing information. If it can't be done, return an undefined Expr.
Expr lossless_cast(Type t, Expr e) {
if (t == e.type()) {
return e;
} else if (t.can_represent(e.type())) {
return cast(t, e);
}
if (const Cast *c = e.as<Cast>()) {
if (t == c->value.type()) {
return c->value;
} else {
return lossless_cast(t, c->value);
}
}
if (const Broadcast *b = e.as<Broadcast>()) {
Expr v = lossless_cast(t.element_of(), b->value);
if (v.defined()) {
return Broadcast::make(v, b->width);
} else {
return Expr();
}
}
if (const IntImm *i = e.as<IntImm>()) {
int x = int_cast_constant(t, i->value);
if (x == i->value) {
return cast(t, e);
} else {
return Expr();
}
}
return Expr();
}
// i32(i16_a)*i32(i16_b) +/- i32(i16_c)*i32(i16_d) can be done by
// interleaving a, c, and b, d, and then using pmaddwd. We
// recognize it here, and implement it in the initial module.
bool should_use_pmaddwd(Expr a, Expr b, vector<Expr> &result) {
Type t = a.type();
internal_assert(b.type() == t);
const Mul *ma = a.as<Mul>();
const Mul *mb = b.as<Mul>();
if (!(ma && mb && t.is_int() && t.bits == 32 && (t.width >= 4))) {
return false;
}
Type narrow = t;
narrow.bits = 16;
vector<Expr> args = {lossless_cast(narrow, ma->a),
lossless_cast(narrow, ma->b),
lossless_cast(narrow, mb->a),
lossless_cast(narrow, mb->b)};
if (!args[0].defined() || !args[1].defined() ||
!args[2].defined() || !args[3].defined()) {
return false;
}
result.swap(args);
return true;
}
}
void CodeGen_X86::visit(const Add *op) {
vector<Expr> matches;
if (should_use_pmaddwd(op->a, op->b, matches)) {
codegen(Call::make(op->type, "pmaddwd", matches, Call::Extern));
} else {
CodeGen_Posix::visit(op);
}
}
void CodeGen_X86::visit(const Sub *op) {
vector<Expr> matches;
if (should_use_pmaddwd(op->a, op->b, matches)) {
// Negate one of the factors in the second expression
if (is_const(matches[2])) {
matches[2] = -matches[2];
} else {
matches[3] = -matches[3];
}
codegen(Call::make(op->type, "pmaddwd", matches, Call::Extern));
} else {
CodeGen_Posix::visit(op);
}
}
void CodeGen_X86::visit(const GT *op) {
Type t = op->a.type();
int bits = t.width * t.bits;
if (t.width == 1 || bits % 128 == 0) {
// LLVM is fine for native vector widths or scalars
CodeGen_Posix::visit(op);
} else {
// Non-native vector widths get legalized poorly by llvm. We
// split it up ourselves.
Value *a = codegen(op->a), *b = codegen(op->b);
int slice_size = 128 / t.bits;
if (target.has_feature(Target::AVX) && bits > 128) {
slice_size = 256 / t.bits;
}
vector<Value *> result;
for (int i = 0; i < op->type.width; i += slice_size) {
Value *sa = slice_vector(a, i, slice_size);
Value *sb = slice_vector(b, i, slice_size);
Value *slice_value;
if (t.is_float()) {
slice_value = builder->CreateFCmpOGT(sa, sb);
} else if (t.is_int()) {
slice_value = builder->CreateICmpSGT(sa, sb);
} else {
slice_value = builder->CreateICmpUGT(sa, sb);
}
result.push_back(slice_value);
}
value = concat_vectors(result);
value = slice_vector(value, 0, t.width);
}
}
void CodeGen_X86::visit(const EQ *op) {
Type t = op->a.type();
int bits = t.width * t.bits;
if (t.width == 1 || bits % 128 == 0) {
// LLVM is fine for native vector widths or scalars
CodeGen_Posix::visit(op);
} else {
// Non-native vector widths get legalized poorly by llvm. We
// split it up ourselves.
Value *a = codegen(op->a), *b = codegen(op->b);
int slice_size = 128 / t.bits;
if (target.has_feature(Target::AVX) && bits > 128) {
slice_size = 256 / t.bits;
}
vector<Value *> result;
for (int i = 0; i < op->type.width; i += slice_size) {
Value *sa = slice_vector(a, i, slice_size);
Value *sb = slice_vector(b, i, slice_size);
Value *slice_value;
if (t.is_float()) {
slice_value = builder->CreateFCmpOEQ(sa, sb);
} else {
slice_value = builder->CreateICmpEQ(sa, sb);
}
result.push_back(slice_value);
}
value = concat_vectors(result);
value = slice_vector(value, 0, t.width);
}
}
void CodeGen_X86::visit(const LT *op) {
codegen(op->b > op->a);
}
void CodeGen_X86::visit(const LE *op) {
codegen(!(op->a > op->b));
}
void CodeGen_X86::visit(const GE *op) {
codegen(!(op->b > op->a));
}
void CodeGen_X86::visit(const NE *op) {
codegen(!(op->a == op->b));
}
void CodeGen_X86::visit(const Select *op) {
// LLVM doesn't correctly use pblendvb for u8 vectors that aren't
// width 16, so we peephole optimize them to intrinsics.
struct Pattern {
string intrin;
Expr pattern;
};
static Pattern patterns[] = {
{"pblendvb_ult_i8x16", select(wild_u8x_ < wild_u8x_, wild_i8x_, wild_i8x_)},
{"pblendvb_ult_i8x16", select(wild_u8x_ < wild_u8x_, wild_u8x_, wild_u8x_)},
{"pblendvb_slt_i8x16", select(wild_i8x_ < wild_i8x_, wild_i8x_, wild_i8x_)},
{"pblendvb_slt_i8x16", select(wild_i8x_ < wild_i8x_, wild_u8x_, wild_u8x_)},
{"pblendvb_ule_i8x16", select(wild_u8x_ <= wild_u8x_, wild_i8x_, wild_i8x_)},
{"pblendvb_ule_i8x16", select(wild_u8x_ <= wild_u8x_, wild_u8x_, wild_u8x_)},
{"pblendvb_sle_i8x16", select(wild_i8x_ <= wild_i8x_, wild_i8x_, wild_i8x_)},
{"pblendvb_sle_i8x16", select(wild_i8x_ <= wild_i8x_, wild_u8x_, wild_u8x_)},
{"pblendvb_ne_i8x16", select(wild_u8x_ != wild_u8x_, wild_i8x_, wild_i8x_)},
{"pblendvb_ne_i8x16", select(wild_u8x_ != wild_u8x_, wild_u8x_, wild_u8x_)},
{"pblendvb_ne_i8x16", select(wild_i8x_ != wild_i8x_, wild_i8x_, wild_i8x_)},
{"pblendvb_ne_i8x16", select(wild_i8x_ != wild_i8x_, wild_i8x_, wild_i8x_)},
{"pblendvb_eq_i8x16", select(wild_u8x_ == wild_u8x_, wild_i8x_, wild_i8x_)},
{"pblendvb_eq_i8x16", select(wild_u8x_ == wild_u8x_, wild_u8x_, wild_u8x_)},
{"pblendvb_eq_i8x16", select(wild_i8x_ == wild_i8x_, wild_i8x_, wild_i8x_)},
{"pblendvb_eq_i8x16", select(wild_i8x_ == wild_i8x_, wild_i8x_, wild_i8x_)},
{"pblendvb_i8x16", select(wild_u1x_, wild_i8x_, wild_i8x_)},
{"pblendvb_i8x16", select(wild_u1x_, wild_u8x_, wild_u8x_)}
};
if (target.has_feature(Target::SSE41) &&
op->condition.type().is_vector() &&
op->type.bits == 8 &&
op->type.width != 16) {
vector<Expr> matches;
for (size_t i = 0; i < sizeof(patterns)/sizeof(patterns[0]); i++) {
if (expr_match(patterns[i].pattern, op, matches)) {
value = call_intrin(op->type, 16, patterns[i].intrin, matches);
return;
}
}
}
CodeGen_Posix::visit(op);
}
void CodeGen_X86::visit(const Cast *op) {
if (!op->type.is_vector()) {
// We only have peephole optimizations for vectors in here.
CodeGen_Posix::visit(op);
return;
}
vector<Expr> matches;
struct Pattern {
bool needs_sse_41;
bool wide_op;
Type type;
string intrin;
Expr pattern;
};
static Pattern patterns[] = {
{false, true, Int(8, 16), "llvm.x86.sse2.padds.b",
_i8(clamp(wild_i16x_ + wild_i16x_, -128, 127))},
{false, true, Int(8, 16), "llvm.x86.sse2.psubs.b",
_i8(clamp(wild_i16x_ - wild_i16x_, -128, 127))},
{false, true, UInt(8, 16), "llvm.x86.sse2.paddus.b",
_u8(min(wild_u16x_ + wild_u16x_, 255))},
{false, true, UInt(8, 16), "llvm.x86.sse2.psubus.b",
_u8(max(wild_i16x_ - wild_i16x_, 0))},
{false, true, Int(16, 8), "llvm.x86.sse2.padds.w",
_i16(clamp(wild_i32x_ + wild_i32x_, -32768, 32767))},
{false, true, Int(16, 8), "llvm.x86.sse2.psubs.w",
_i16(clamp(wild_i32x_ - wild_i32x_, -32768, 32767))},
{false, true, UInt(16, 8), "llvm.x86.sse2.paddus.w",
_u16(min(wild_u32x_ + wild_u32x_, 65535))},
{false, true, UInt(16, 8), "llvm.x86.sse2.psubus.w",
_u16(max(wild_i32x_ - wild_i32x_, 0))},
{false, true, Int(16, 8), "llvm.x86.sse2.pmulh.w",
_i16((wild_i32x_ * wild_i32x_) / 65536)},
{false, true, UInt(16, 8), "llvm.x86.sse2.pmulhu.w",
_u16((wild_u32x_ * wild_u32x_) / 65536)},
{false, true, UInt(8, 16), "llvm.x86.sse2.pavg.b",
_u8(((wild_u16x_ + wild_u16x_) + 1) / 2)},
{false, true, UInt(16, 8), "llvm.x86.sse2.pavg.w",
_u16(((wild_u32x_ + wild_u32x_) + 1) / 2)},
{false, false, Int(16, 8), "packssdwx8",
_i16(clamp(wild_i32x_, -32768, 32767))},
{false, false, Int(8, 16), "packsswbx16",
_i8(clamp(wild_i16x_, -128, 127))},
{false, false, UInt(8, 16), "packuswbx16",
_u8(clamp(wild_i16x_, 0, 255))},
{true, false, UInt(16, 8), "packusdwx8",
_u16(clamp(wild_i32x_, 0, 65535))}
};
for (size_t i = 0; i < sizeof(patterns)/sizeof(patterns[0]); i++) {
const Pattern &pattern = patterns[i];
if (!target.has_feature(Target::SSE41) && pattern.needs_sse_41) {
continue;
}
if (expr_match(pattern.pattern, op, matches)) {
bool match = true;
if (pattern.wide_op) {
// Try to narrow the matches to the target type.
for (size_t i = 0; i < matches.size(); i++) {
matches[i] = lossless_cast(op->type, matches[i]);
if (!matches[i].defined()) match = false;
}
}
if (match) {
value = call_intrin(op->type, pattern.type.width, pattern.intrin, matches);
return;
}
}
}
#if LLVM_VERSION >= 38
// Workaround for https://llvm.org/bugs/show_bug.cgi?id=24512
// LLVM uses a numerically unstable method for vector
// uint32->float conversion before AVX.
if (op->value.type().element_of() == UInt(32) &&
op->type.is_float() &&
op->type.is_vector() &&
!target.has_feature(Target::AVX)) {
Type signed_type = Int(32, op->type.width);
// Convert the top 31 bits to float using the signed version
Expr top_bits = cast(signed_type, op->value / 2);
top_bits = cast(op->type, top_bits);
// Convert the bottom bit
Expr bottom_bit = cast(signed_type, op->value % 2);
bottom_bit = cast(op->type, bottom_bit);
// Recombine as floats
codegen(top_bits + top_bits + bottom_bit);
return;
}
#endif
CodeGen_Posix::visit(op);
}
void CodeGen_X86::visit(const Div *op) {
user_assert(!is_zero(op->b)) << "Division by constant zero in expression: " << Expr(op) << "\n";
// Detect if it's a small int division
const Broadcast *broadcast = op->b.as<Broadcast>();
const Cast *cast_b = broadcast ? broadcast->value.as<Cast>() : NULL;
const IntImm *int_imm = cast_b ? cast_b->value.as<IntImm>() : NULL;
if (broadcast && !int_imm) int_imm = broadcast->value.as<IntImm>();
if (!int_imm) int_imm = op->b.as<IntImm>();
int const_divisor = int_imm ? int_imm->value : 0;
int shift_amount;
bool power_of_two = is_const_power_of_two_integer(op->b, &shift_amount);
vector<Expr> matches;
if (power_of_two && op->type.is_int()) {
Value *numerator = codegen(op->a);
Constant *shift = ConstantInt::get(llvm_type_of(op->type), shift_amount);
value = builder->CreateAShr(numerator, shift);
} else if (power_of_two && op->type.is_uint()) {
Value *numerator = codegen(op->a);
Constant *shift = ConstantInt::get(llvm_type_of(op->type), shift_amount);
value = builder->CreateLShr(numerator, shift);
} else if (op->type.is_int() &&
(op->type.bits == 8 || op->type.bits == 16 || op->type.bits == 32) &&
const_divisor > 1 &&
((op->type.bits > 8 && const_divisor < 256) || const_divisor < 128)) {
int64_t multiplier, shift;
if (op->type.bits == 32) {
multiplier = IntegerDivision::table_s32[const_divisor][2];
shift = IntegerDivision::table_s32[const_divisor][3];
} else if (op->type.bits == 16) {
multiplier = IntegerDivision::table_s16[const_divisor][2];
shift = IntegerDivision::table_s16[const_divisor][3];
} else {
// 8 bit
multiplier = IntegerDivision::table_s8[const_divisor][2];
shift = IntegerDivision::table_s8[const_divisor][3];
}
Value *val = codegen(op->a);
// Make an all-ones mask if the numerator is negative
Value *sign = builder->CreateAShr(val, codegen(make_const(op->type, op->type.bits-1)));
// Flip the numerator bits if the mask is high.
Value *flipped = builder->CreateXor(sign, val);
llvm::Type *narrower = llvm_type_of(op->type);
llvm::Type *wider = llvm_type_of(Int(op->type.bits*2, op->type.width));
// Grab the multiplier.
Value *mult = ConstantInt::get(narrower, multiplier);
// Widening multiply, keep high half, shift
if (op->type.element_of() == Int(16) && op->type.is_vector()) {
val = call_intrin(narrower, 8, "llvm.x86.sse2.pmulhu.w", {flipped, mult});
if (shift) {
Constant *shift_amount = ConstantInt::get(narrower, shift);
val = builder->CreateLShr(val, shift_amount);
}
} else {
// flipped's high bit is zero, so it's ok to zero-extend it
Value *flipped_wide = builder->CreateIntCast(flipped, wider, false);
Value *mult_wide = builder->CreateIntCast(mult, wider, false);
Value *wide_val = builder->CreateMul(flipped_wide, mult_wide);
// Do the shift (add 8 or 16 or 32 to narrow back down)
Constant *shift_amount = ConstantInt::get(wider, (shift + op->type.bits));
val = builder->CreateLShr(wide_val, shift_amount);
val = builder->CreateIntCast(val, narrower, true);
}
// Maybe flip the bits again
value = builder->CreateXor(val, sign);
} else if (op->type.is_uint() &&
(op->type.bits == 8 || op->type.bits == 16 || op->type.bits == 32) &&
const_divisor > 1 && const_divisor < 256) {
int64_t method, multiplier, shift;
if (op->type.bits == 32) {
method = IntegerDivision::table_u32[const_divisor][1];
multiplier = IntegerDivision::table_u32[const_divisor][2];
shift = IntegerDivision::table_u32[const_divisor][3];
} else if (op->type.bits == 16) {
method = IntegerDivision::table_u16[const_divisor][1];
multiplier = IntegerDivision::table_u16[const_divisor][2];
shift = IntegerDivision::table_u16[const_divisor][3];
} else {
method = IntegerDivision::table_u8[const_divisor][1];
multiplier = IntegerDivision::table_u8[const_divisor][2];
shift = IntegerDivision::table_u8[const_divisor][3];
}
internal_assert(method != 0)
<< "method 0 division is for powers of two and should have been handled elsewhere\n";
Value *num = codegen(op->a);
// Widen, multiply, narrow
llvm::Type *narrower = llvm_type_of(op->type);
llvm::Type *wider = llvm_type_of(UInt(op->type.bits*2, op->type.width));
Value *mult = ConstantInt::get(narrower, multiplier);
Value *val = num;
if (op->type.element_of() == UInt(16) && op->type.is_vector()) {
val = call_intrin(narrower, 8, "llvm.x86.sse2.pmulhu.w", {val, mult});
if (shift && method == 1) {
Constant *shift_amount = ConstantInt::get(narrower, shift);
val = builder->CreateLShr(val, shift_amount);
}
} else {
// Widen
mult = builder->CreateIntCast(mult, wider, false);
val = builder->CreateIntCast(val, wider, false);
// Multiply
val = builder->CreateMul(val, mult);
// Keep high half
int shift_bits = op->type.bits;
// For method 1, we can do the final shift here too
if (method == 1) {
shift_bits += (int)shift;
}
Constant *shift_amount = ConstantInt::get(wider, shift_bits);
val = builder->CreateLShr(val, shift_amount);
val = builder->CreateIntCast(val, narrower, false);
}
// Average with original numerator. Can't use sse rounding ops
// because they round up.
if (method == 2) {
// num > val, so the following works without widening:
// val += (num - val)/2
Value *diff = builder->CreateSub(num, val);
diff = builder->CreateLShr(diff, ConstantInt::get(diff->getType(), 1));
val = builder->CreateNSWAdd(val, diff);
// Do the final shift
if (shift) {
val = builder->CreateLShr(val, ConstantInt::get(narrower, shift));
}
}
value = val;
} else {
CodeGen_Posix::visit(op);
}
}
void CodeGen_X86::visit(const Min *op) {
if (!op->type.is_vector()) {
CodeGen_Posix::visit(op);
return;
}
bool use_sse_41 = target.has_feature(Target::SSE41);
if (op->type.element_of() == UInt(8)) {
value = call_intrin(op->type, 16, "llvm.x86.sse2.pminu.b", {op->a, op->b});
} else if (use_sse_41 && op->type.element_of() == Int(8)) {
value = call_intrin(op->type, 16, "llvm.x86.sse41.pminsb", {op->a, op->b});
} else if (op->type.element_of() == Int(16)) {
value = call_intrin(op->type, 8, "llvm.x86.sse2.pmins.w", {op->a, op->b});
} else if (use_sse_41 && op->type.element_of() == UInt(16)) {
value = call_intrin(op->type, 8, "llvm.x86.sse41.pminuw", {op->a, op->b});
} else if (use_sse_41 && op->type.element_of() == Int(32)) {
value = call_intrin(op->type, 4, "llvm.x86.sse41.pminsd", {op->a, op->b});
} else if (use_sse_41 && op->type.element_of() == UInt(32)) {
value = call_intrin(op->type, 4, "llvm.x86.sse41.pminud", {op->a, op->b});
} else if (op->type.element_of() == Float(32)) {
if (op->type.width % 8 == 0 && target.has_feature(Target::AVX)) {
// This condition should possibly be > 4, rather than a
// multiple of 8, but shuffling in undefs seems to work
// poorly with avx.
value = call_intrin(op->type, 8, "min_f32x8", {op->a, op->b});
} else {
value = call_intrin(op->type, 4, "min_f32x4", {op->a, op->b});
}
} else if (op->type.element_of() == Float(64)) {
if (op->type.width % 4 == 0 && target.has_feature(Target::AVX)) {
value = call_intrin(op->type, 4, "min_f64x4", {op->a, op->b});
} else {
value = call_intrin(op->type, 2, "min_f64x2", {op->a, op->b});
}
} else {
CodeGen_Posix::visit(op);
}
}
void CodeGen_X86::visit(const Max *op) {
if (!op->type.is_vector()) {
CodeGen_Posix::visit(op);
return;
}
bool use_sse_41 = target.has_feature(Target::SSE41);
if (op->type.element_of() == UInt(8)) {
value = call_intrin(op->type, 16, "llvm.x86.sse2.pmaxu.b", {op->a, op->b});
} else if (use_sse_41 && op->type.element_of() == Int(8)) {
value = call_intrin(op->type, 16, "llvm.x86.sse41.pmaxsb", {op->a, op->b});
} else if (op->type.element_of() == Int(16)) {
value = call_intrin(op->type, 8, "llvm.x86.sse2.pmaxs.w", {op->a, op->b});
} else if (use_sse_41 && op->type.element_of() == UInt(16)) {
value = call_intrin(op->type, 8, "llvm.x86.sse41.pmaxuw", {op->a, op->b});
} else if (use_sse_41 && op->type.element_of() == Int(32)) {
value = call_intrin(op->type, 4, "llvm.x86.sse41.pmaxsd", {op->a, op->b});
} else if (use_sse_41 && op->type.element_of() == UInt(32)) {
value = call_intrin(op->type, 4, "llvm.x86.sse41.pmaxud", {op->a, op->b});
} else if (op->type.element_of() == Float(32)) {
if (op->type.width % 8 == 0 && target.has_feature(Target::AVX)) {
value = call_intrin(op->type, 8, "max_f32x8", {op->a, op->b});
} else {
value = call_intrin(op->type, 4, "max_f32x4", {op->a, op->b});
}
} else if (op->type.element_of() == Float(64)) {
if (op->type.width % 4 == 0 && target.has_feature(Target::AVX)) {
value = call_intrin(op->type, 4, "max_f64x4", {op->a, op->b});
} else {
value = call_intrin(op->type, 2, "max_f64x2", {op->a, op->b});
}
} else {
CodeGen_Posix::visit(op);
}
}
string CodeGen_X86::mcpu() const {
if (target.has_feature(Target::AVX)) return "corei7-avx";
// We want SSE4.1 but not SSE4.2, hence "penryn" rather than "corei7"
if (target.has_feature(Target::SSE41)) return "penryn";
// Default should not include SSSE3, hence "k8" rather than "core2"
return "k8";
}
string CodeGen_X86::mattrs() const {
std::string features;
std::string separator;
#if LLVM_VERSION >= 35
// These attrs only exist in llvm 3.5+
if (target.has_feature(Target::FMA)) {
features += "+fma";
separator = ",";
}
if (target.has_feature(Target::FMA4)) {
features += separator + "+fma4";
separator = ",";
}
if (target.has_feature(Target::F16C)) {
features += separator + "+f16c";
separator = ",";
}
#endif
return features;
}
bool CodeGen_X86::use_soft_float_abi() const {
return false;
}
int CodeGen_X86::native_vector_bits() const {
if (target.has_feature(Target::AVX)) {
return 256;
} else {
return 128;
}
}
}}