final fixes

[nikitalita]

I added back the custom rules and changed them so that:

1. the custom rules that duplicated global rules were commented out
2. the minimum clearance rule for the inner layers has been changed so it doesn't apply to zones, so it won't have the same copper fill bug that it did before

The custom rules catch stuff that the global rules don't, but fortunately, we didn't have anything to fix here.

I also length matched the D- and D+ lines by making D- and D+ both use vias to cross each other; I also adjusted the spacking and width of the tracks of the main run based on this calculation from eeweb:

With this, I think we're finally finished with this revision 🥳

[hansfbaier]

Thanks, great 👍🏻 Will look at it soon. Do you want me to put your name or GitHub handle in the board?

[nikitalita]

Sure, "Nikita Lita" will be fine.

[hansfbaier]

@nikitalita The Diff Pair traces on the top and bottom PHY look different. Are you sure you adjusted them both?
Which ones are the one you adjusted, the bottom one, as it looks?

[hansfbaier]

Yes, the bottom one as it looks. I will adjust the top one too. Ok, did it. WIll commit soon 0.09mm gap is hard on the edge of JLCPCB manufacturing capability. Let's hope it turns out right.
The bottom PHY worked great with 0.3mm width and standard spacing, and I think for that short length it is not that critical.
But it never hurts to do things properly!

[nikitalita]

the spacing limit is technically 3.5mil, which is 0.0889mm, so that means we have a full 0.0011 mm to play with 😄
But if you think it may be an issue, 0.1mm spacing and a width of 0.38mm will also work:

[hansfbaier]

@nikitalita I am a bit surprised, though, that you didn't have to input the dielectric constant in this calculator.
This is a very crucial number, because it affects the whole geometry.

[nikitalita]

That's what Substrate Dielectric is:

[nikitalita]

Urgh, I did only apply it to the bottom one, and I forgot to length match the top one. I just fixed this and adjusted the values of the main run according to the new calc above, PR incoming.

[hansfbaier]

That's what Substrate Dielectric is:

Ah I overlooked this.

[hansfbaier]

@nikitalita please pull first, I already adjusted the top one.

[nikitalita]

I did, the top one had the main run adjusted but not the back part.