GPIO.Button.Special.ucf

## =============================================================================================================================================================
## Xilinx User Constraint File (UCF)
## =============================================================================================================================================================
##	Board:					Xilinx - Virtex 6 ML605
##	FPGA:						Xilinx Virtex 6
##		Device:				XC6VLX240T
##		Package:			FF1156
##		Speedgrade:		-1
## =============================================================================================================================================================
## General Purpose I/O
## =============================================================================================================================================================
##
## Special Buttons
## =============================================================================
##	Bank:						35
##		VCCO:					1.5V (VCC1V5_FPGA)
##	Location:				SW10
## -----------------------------------------------------------------------------
NET "ML605_GPIO_Button_CPU_Reset"		LOC = "H10"	| IOSTANDARD = LVCMOS15;			## {IN}			high-active; breaker / normally closed

## Ignore timings on async I/O pins
NET "ML605_GPIO_Button_CPU_Reset"		TIG;