add debug messages if interrupt is pending

Signed-off-by: Stefan Lankes <slankes@eonerc.rwth-aachen.de>
hermit-os · Nov 25, 2020 · f5ada5b · f5ada5b
1 parent 68f8d31
commit f5ada5b
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/src/arch/x86_64/kernel/apic.rs b/src/arch/x86_64/kernel/apic.rs
@@ -733,11 +733,11 @@ fn local_apic_write(x2apic_msr: u32, value: u64) {
 			// The ICR1 register in xAPIC mode also has a Delivery Status bit.
 			// Wait until previous interrupt was deliverd.
 			// This bit does not exist in x2APIC mode (cf. Intel Vol. 3A, 10.12.9).
-			while (unsafe { core::ptr::read_volatile(value_ref) }
-				& APIC_ICR_DELIVERY_STATUS_PENDING)
+			if (unsafe { core::ptr::read_volatile(value_ref) } & APIC_ICR_DELIVERY_STATUS_PENDING)
 				> 0
 			{
 				spin_loop_hint();
+				info!("Previous interrupt is missing");
 			}
 
 			// Instead of a single 64-bit ICR register, xAPIC has two 32-bit registers (ICR1 and ICR2).