rk3328-t9.dts

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2017 PINE64
 */

/dts-v1/;
#include "rk3328.dtsi"

/ {
	model = "T9";
	compatible = "t9,t9", "rockchip,rk3328";

	chosen {
		bootargs = "earlycon=uart8250,mmio32,0xff130000";
		stdout-path = "serial2:1500000n8";
	};

/* seems to be required to not touch the trust area - see:
   - https://forum.manjaro.org/t/rockpro64-kernel-panics-caused-by-firmware/117900
   - https://lore.kernel.org/linux-arm-kernel/006d3ee0-2711-1b4e-d8cf-6a226fcad0e4@arm.com/
   this section can be removed if a mainline u-boot without trustzone is used
*/
	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		tee@0x8400000 {
			reg = <0x0 0x8400000 0x0 0x2400000>;
			no-map;
		};
	};

/* the ddr_timing is only used with legacy atf - mainline atf does not yet support dmc */
	ddr_timing {
		compatible = "rockchip,ddr-timing";
		ddr3_speed_bin = <0x15>;
		ddr4_speed_bin = <0xc>;
		pd_idle = <0x0>;
		sr_idle = <0x0>;
		sr_mc_gate_idle = <0x0>;
		srpd_lite_idle = <0x0>;
		standby_idle = <0x0>;
		auto_pd_dis_freq = <0x42a>;
		auto_sr_dis_freq = <0x320>;
		ddr3_dll_dis_freq = <0x12c>;
		ddr4_dll_dis_freq = <0x271>;
		phy_dll_dis_freq = <0x190>;
		ddr3_odt_dis_freq = <0x64>;
		phy_ddr3_odt_dis_freq = <0x64>;
		ddr3_drv = <0x28>;
		ddr3_odt = <0x78>;
		phy_ddr3_ca_drv = <0x1b>;
		phy_ddr3_ck_drv = <0x15>;
		phy_ddr3_dq_drv = <0x15>;
		phy_ddr3_odt = <0x2>;
		lpddr3_odt_dis_freq = <0x29a>;
		phy_lpddr3_odt_dis_freq = <0x29a>;
		lpddr3_drv = <0x28>;
		lpddr3_odt = <0xf0>;
		phy_lpddr3_ca_drv = <0x16>;
		phy_lpddr3_ck_drv = <0x13>;
		phy_lpddr3_dq_drv = <0x16>;
		phy_lpddr3_odt = <0x2>;
		lpddr4_odt_dis_freq = <0x320>;
		phy_lpddr4_odt_dis_freq = <0x320>;
		lpddr4_drv = <0x3c>;
		lpddr4_dq_odt = <0x28>;
		lpddr4_ca_odt = <0x28>;
		phy_lpddr4_ca_drv = <0x14>;
		phy_lpddr4_ck_cs_drv = <0x6>;
		phy_lpddr4_dq_drv = <0x6>;
		phy_lpddr4_odt = <0x10>;
		ddr4_odt_dis_freq = <0x29a>;
		phy_ddr4_odt_dis_freq = <0x29a>;
		ddr4_drv = <0x22>;
		ddr4_odt = <0xf0>;
		phy_ddr4_ca_drv = <0x16>;
		phy_ddr4_ck_drv = <0x13>;
		phy_ddr4_dq_drv = <0x16>;
		phy_ddr4_odt = <0x2>;
		ddr3a1_ddr4a9_de-skew = <0x2>;
		ddr3a0_ddr4a10_de-skew = <0x3>;
		ddr3a3_ddr4a6_de-skew = <0x3>;
		ddr3a2_ddr4a4_de-skew = <0x2>;
		ddr3a5_ddr4a8_de-skew = <0x3>;
		ddr3a4_ddr4a5_de-skew = <0x2>;
		ddr3a7_ddr4a11_de-skew = <0x3>;
		ddr3a6_ddr4a7_de-skew = <0x2>;
		ddr3a9_ddr4a0_de-skew = <0x2>;
		ddr3a8_ddr4a13_de-skew = <0x1>;
		ddr3a11_ddr4a3_de-skew = <0x2>;
		ddr3a10_ddr4cs0_de-skew = <0x2>;
		ddr3a13_ddr4a2_de-skew = <0x1>;
		ddr3a12_ddr4ba1_de-skew = <0x2>;
		ddr3a15_ddr4odt0_de-skew = <0x3>;
		ddr3a14_ddr4a1_de-skew = <0x2>;
		ddr3ba1_ddr4a15_de-skew = <0x2>;
		ddr3ba0_ddr4bg0_de-skew = <0x4>;
		ddr3ras_ddr4cke_de-skew = <0x4>;
		ddr3ba2_ddr4ba0_de-skew = <0x3>;
		ddr3we_ddr4bg1_de-skew = <0x2>;
		ddr3cas_ddr4a12_de-skew = <0x2>;
		ddr3ckn_ddr4ckn_de-skew = <0xa>;
		ddr3ckp_ddr4ckp_de-skew = <0xa>;
		ddr3cke_ddr4a16_de-skew = <0x2>;
		ddr3odt0_ddr4a14_de-skew = <0x4>;
		ddr3cs0_ddr4act_de-skew = <0x4>;
		ddr3reset_ddr4reset_de-skew = <0x7>;
		ddr3cs1_ddr4cs1_de-skew = <0x7>;
		ddr3odt1_ddr4odt1_de-skew = <0x7>;
		cs0_dm0_rx_de-skew = <0xc>;
		cs0_dm0_tx_de-skew = <0xa>;
		cs0_dq0_rx_de-skew = <0xc>;
		cs0_dq0_tx_de-skew = <0xa>;
		cs0_dq1_rx_de-skew = <0xc>;
		cs0_dq1_tx_de-skew = <0xa>;
		cs0_dq2_rx_de-skew = <0xc>;
		cs0_dq2_tx_de-skew = <0xa>;
		cs0_dq3_rx_de-skew = <0xc>;
		cs0_dq3_tx_de-skew = <0xa>;
		cs0_dq4_rx_de-skew = <0xc>;
		cs0_dq4_tx_de-skew = <0xa>;
		cs0_dq5_rx_de-skew = <0xc>;
		cs0_dq5_tx_de-skew = <0xa>;
		cs0_dq6_rx_de-skew = <0xc>;
		cs0_dq6_tx_de-skew = <0xa>;
		cs0_dq7_rx_de-skew = <0xc>;
		cs0_dq7_tx_de-skew = <0xa>;
		cs0_dqs0_rx_de-skew = <0xa>;
		cs0_dqs0p_tx_de-skew = <0xb>;
		cs0_dqs0n_tx_de-skew = <0xb>;
		cs0_dm1_rx_de-skew = <0xa>;
		cs0_dm1_tx_de-skew = <0x8>;
		cs0_dq8_rx_de-skew = <0xa>;
		cs0_dq8_tx_de-skew = <0x8>;
		cs0_dq9_rx_de-skew = <0xa>;
		cs0_dq9_tx_de-skew = <0x8>;
		cs0_dq10_rx_de-skew = <0xa>;
		cs0_dq10_tx_de-skew = <0x8>;
		cs0_dq11_rx_de-skew = <0xa>;
		cs0_dq11_tx_de-skew = <0x8>;
		cs0_dq12_rx_de-skew = <0xa>;
		cs0_dq12_tx_de-skew = <0x8>;
		cs0_dq13_rx_de-skew = <0xa>;
		cs0_dq13_tx_de-skew = <0x8>;
		cs0_dq14_rx_de-skew = <0xa>;
		cs0_dq14_tx_de-skew = <0x8>;
		cs0_dq15_rx_de-skew = <0xa>;
		cs0_dq15_tx_de-skew = <0x8>;
		cs0_dqs1_rx_de-skew = <0x9>;
		cs0_dqs1p_tx_de-skew = <0x8>;
		cs0_dqs1n_tx_de-skew = <0x8>;
		cs0_dm2_rx_de-skew = <0xa>;
		cs0_dm2_tx_de-skew = <0x9>;
		cs0_dq16_rx_de-skew = <0xa>;
		cs0_dq16_tx_de-skew = <0x9>;
		cs0_dq17_rx_de-skew = <0xa>;
		cs0_dq17_tx_de-skew = <0x9>;
		cs0_dq18_rx_de-skew = <0xa>;
		cs0_dq18_tx_de-skew = <0x9>;
		cs0_dq19_rx_de-skew = <0xa>;
		cs0_dq19_tx_de-skew = <0x9>;
		cs0_dq20_rx_de-skew = <0xa>;
		cs0_dq20_tx_de-skew = <0x9>;
		cs0_dq21_rx_de-skew = <0xa>;
		cs0_dq21_tx_de-skew = <0x9>;
		cs0_dq22_rx_de-skew = <0xa>;
		cs0_dq22_tx_de-skew = <0x9>;
		cs0_dq23_rx_de-skew = <0xa>;
		cs0_dq23_tx_de-skew = <0x9>;
		cs0_dqs2_rx_de-skew = <0x9>;
		cs0_dqs2p_tx_de-skew = <0x9>;
		cs0_dqs2n_tx_de-skew = <0x9>;
		cs0_dm3_rx_de-skew = <0x7>;
		cs0_dm3_tx_de-skew = <0x7>;
		cs0_dq24_rx_de-skew = <0x7>;
		cs0_dq24_tx_de-skew = <0x7>;
		cs0_dq25_rx_de-skew = <0x7>;
		cs0_dq25_tx_de-skew = <0x7>;
		cs0_dq26_rx_de-skew = <0x7>;
		cs0_dq26_tx_de-skew = <0x7>;
		cs0_dq27_rx_de-skew = <0x7>;
		cs0_dq27_tx_de-skew = <0x7>;
		cs0_dq28_rx_de-skew = <0x7>;
		cs0_dq28_tx_de-skew = <0x7>;
		cs0_dq29_rx_de-skew = <0x7>;
		cs0_dq29_tx_de-skew = <0x7>;
		cs0_dq30_rx_de-skew = <0x7>;
		cs0_dq30_tx_de-skew = <0x7>;
		cs0_dq31_rx_de-skew = <0x7>;
		cs0_dq31_tx_de-skew = <0x7>;
		cs0_dqs3_rx_de-skew = <0x7>;
		cs0_dqs3p_tx_de-skew = <0x8>;
		cs0_dqs3n_tx_de-skew = <0x8>;
		cs1_dm0_rx_de-skew = <0x7>;
		cs1_dm0_tx_de-skew = <0x8>;
		cs1_dq0_rx_de-skew = <0x7>;
		cs1_dq0_tx_de-skew = <0x8>;
		cs1_dq1_rx_de-skew = <0x7>;
		cs1_dq1_tx_de-skew = <0x8>;
		cs1_dq2_rx_de-skew = <0x7>;
		cs1_dq2_tx_de-skew = <0x8>;
		cs1_dq3_rx_de-skew = <0x7>;
		cs1_dq3_tx_de-skew = <0x8>;
		cs1_dq4_rx_de-skew = <0x7>;
		cs1_dq4_tx_de-skew = <0x8>;
		cs1_dq5_rx_de-skew = <0x7>;
		cs1_dq5_tx_de-skew = <0x8>;
		cs1_dq6_rx_de-skew = <0x7>;
		cs1_dq6_tx_de-skew = <0x8>;
		cs1_dq7_rx_de-skew = <0x7>;
		cs1_dq7_tx_de-skew = <0x8>;
		cs1_dqs0_rx_de-skew = <0x6>;
		cs1_dqs0p_tx_de-skew = <0x9>;
		cs1_dqs0n_tx_de-skew = <0x9>;
		cs1_dm1_rx_de-skew = <0x7>;
		cs1_dm1_tx_de-skew = <0x7>;
		cs1_dq8_rx_de-skew = <0x7>;
		cs1_dq8_tx_de-skew = <0x8>;
		cs1_dq9_rx_de-skew = <0x7>;
		cs1_dq9_tx_de-skew = <0x7>;
		cs1_dq10_rx_de-skew = <0x7>;
		cs1_dq10_tx_de-skew = <0x8>;
		cs1_dq11_rx_de-skew = <0x7>;
		cs1_dq11_tx_de-skew = <0x7>;
		cs1_dq12_rx_de-skew = <0x7>;
		cs1_dq12_tx_de-skew = <0x8>;
		cs1_dq13_rx_de-skew = <0x7>;
		cs1_dq13_tx_de-skew = <0x7>;
		cs1_dq14_rx_de-skew = <0x7>;
		cs1_dq14_tx_de-skew = <0x8>;
		cs1_dq15_rx_de-skew = <0x7>;
		cs1_dq15_tx_de-skew = <0x7>;
		cs1_dqs1_rx_de-skew = <0x7>;
		cs1_dqs1p_tx_de-skew = <0x9>;
		cs1_dqs1n_tx_de-skew = <0x9>;
		cs1_dm2_rx_de-skew = <0x7>;
		cs1_dm2_tx_de-skew = <0x8>;
		cs1_dq16_rx_de-skew = <0x7>;
		cs1_dq16_tx_de-skew = <0x8>;
		cs1_dq17_rx_de-skew = <0x7>;
		cs1_dq17_tx_de-skew = <0x8>;
		cs1_dq18_rx_de-skew = <0x7>;
		cs1_dq18_tx_de-skew = <0x8>;
		cs1_dq19_rx_de-skew = <0x7>;
		cs1_dq19_tx_de-skew = <0x8>;
		cs1_dq20_rx_de-skew = <0x7>;
		cs1_dq20_tx_de-skew = <0x8>;
		cs1_dq21_rx_de-skew = <0x7>;
		cs1_dq21_tx_de-skew = <0x8>;
		cs1_dq22_rx_de-skew = <0x7>;
		cs1_dq22_tx_de-skew = <0x8>;
		cs1_dq23_rx_de-skew = <0x7>;
		cs1_dq23_tx_de-skew = <0x8>;
		cs1_dqs2_rx_de-skew = <0x6>;
		cs1_dqs2p_tx_de-skew = <0x9>;
		cs1_dqs2n_tx_de-skew = <0x9>;
		cs1_dm3_rx_de-skew = <0x7>;
		cs1_dm3_tx_de-skew = <0x7>;
		cs1_dq24_rx_de-skew = <0x7>;
		cs1_dq24_tx_de-skew = <0x8>;
		cs1_dq25_rx_de-skew = <0x7>;
		cs1_dq25_tx_de-skew = <0x7>;
		cs1_dq26_rx_de-skew = <0x7>;
		cs1_dq26_tx_de-skew = <0x7>;
		cs1_dq27_rx_de-skew = <0x7>;
		cs1_dq27_tx_de-skew = <0x7>;
		cs1_dq28_rx_de-skew = <0x7>;
		cs1_dq28_tx_de-skew = <0x7>;
		cs1_dq29_rx_de-skew = <0x7>;
		cs1_dq29_tx_de-skew = <0x7>;
		cs1_dq30_rx_de-skew = <0x7>;
		cs1_dq30_tx_de-skew = <0x7>;
		cs1_dq31_rx_de-skew = <0x7>;
		cs1_dq31_tx_de-skew = <0x7>;
		cs1_dqs3_rx_de-skew = <0x7>;
		cs1_dqs3p_tx_de-skew = <0x9>;
		cs1_dqs3n_tx_de-skew = <0x9>;
		linux,phandle = <0x7c>;
		phandle = <0x7c>;
	};

/*	leds {
		compatible = "gpio-leds";

		standby-led {
			linux,default-trigger = "disk-activity";
			gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
			default-state = "on";
		};

		power-led {
			gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
			default-state = "on";
		};
	};

	leds {
		compatible = "gpio-leds";

		usb-switch {
			linux,default-trigger = "none";
			gpios = <&gpio0 2 1>;
			mode = <0x23>;
			default-state = "on";
		};
	}; */

	gmac_clkin: external-gmac-clock {
		compatible = "fixed-clock";
		clock-frequency = <125000000>;
		clock-output-names = "gmac_clkin";
		#clock-cells = <0>;
	};

/*	vcc_sd: sdmmc-regulator {
		compatible = "regulator-fixed";
		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&sdmmc0m1_gpio>;
		regulator-name = "vcc_sd";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vcc_io>;
	}; */

	vcc_host_5v: vcc-host-5v-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&usb30_host_drv>;
		regulator-name = "vcc_host_5v";
		regulator-always-on;
		regulator-boot-on;
		vin-supply = <&vcc_sys>;
	};

	vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&usb20_host_drv>;
		regulator-name = "vcc_host1_5v";
		regulator-always-on;
		regulator-boot-on;
		vin-supply = <&vcc_sys>;
	};

	vcc_sys: vcc-sys {
		compatible = "regulator-fixed";
		regulator-name = "vcc_sys";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

/*	ir-receiver {
		compatible = "gpio-ir-receiver";
		gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
		pinctrl-0 = <&ir_int>;
		pinctrl-names = "default";
	};

	leds {
		compatible = "gpio-leds";

		power {
			gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "mmc0";
		};

		standby {
			gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "heartbeat";
		};
	}; */

	sound {
		compatible = "audio-graph-card";
		label = "rockchip,rk3328";
		dais = <&i2s0_p0
			&i2s1_p0
			&spdif_p0>;
	};

	spdif-dit {
		compatible = "linux,spdif-dit";
		#sound-dai-cells = <0>;

		port {
			dit_p0_0: endpoint {
				remote-endpoint = <&spdif_p0_0>;
			};
		};
	};

	vcc_phy: vcc-phy-regulator {
		compatible = "regulator-fixed";
		regulator-name = "vcc_phy";
		regulator-always-on;
		regulator-boot-on;
	};

/*	vdd_arm: vdd_arm {
		compatible = "regulator-fixed";
		regulator-name = "vdd_arm";
		regulator-min-microvolt = <1100000>;
		regulator-max-microvolt = <1100000>;
		regulator-always-on;
		regulator-boot-on;
	}; */

	vdd_arm: vdd_arm {
		compatible = "pwm-regulator";
		pwms = <&pwm0 0 5000 1>;
		regulator-name = "vcc_arm";
		regulator-min-microvolt = <900000>;
		regulator-max-microvolt = <1475000>;
		regulator-always-on;
		regulator-boot-on;
		status="okay";
	};

};

&codec {
	status = "okay";

	port@0 {
		codec_p0_0: endpoint {
			remote-endpoint = <&i2s1_p0_0>;
		};
	};
};

&cpu0 {
	cpu-supply = <&vdd_arm>;
};

&cpu1 {
	cpu-supply = <&vdd_arm>;
};

&cpu2 {
	cpu-supply = <&vdd_arm>;
};

&cpu3 {
	cpu-supply = <&vdd_arm>;
};

/* adjusted opp table to use slightly (50mv) higher voltages and disable the clocks higher than 1.3ghz */
&cpu0_opp_table {
	opp-408000000 {
		opp-microvolt = <975000>;
	};
	opp-600000000 {
		opp-microvolt = <975000>;
	};
	opp-816000000 {
		opp-microvolt = <1025000>;
	};
	opp-1008000000 {
		opp-microvolt = <1125000>;
	};
	opp-1200000000 {
		opp-microvolt = <1250000>;
	};
	opp-1296000000 {
		opp-microvolt = <1350000>;
		status = "okay";
	};
	opp-1392000000 {
		opp-hz = /bits/ 64 <1392000000>;
		opp-microvolt = <1400000>;
		clock-latency-ns = <40000>;
		status = "okay";
		turbo-mode;
	};
	opp-1416000000 {
		opp-hz = /bits/ 64 <1416000000>;
		opp-microvolt = <1475000>;
		clock-latency-ns = <40000>;
		status = "okay";
		turbo-mode;
	};
	opp-1488000000 {
		opp-hz = /bits/ 64 <1488000000>;
		opp-microvolt = <1475000>;
		clock-latency-ns = <40000>;
		status = "okay";
		turbo-mode;
	};
	opp-1512000000 {
		opp-hz = /bits/ 64 <1512000000>;
		opp-microvolt = <1475000>;
		clock-latency-ns = <40000>;
		status = "okay";
		turbo-mode;
	};
	opp-1608000000 {
		opp-hz = /bits/ 64 <1608000000>;
		opp-microvolt = <1475000>;
		clock-latency-ns = <40000>;
		status = "okay";
		turbo-mode;
	};
};

&emmc {
// 	max-frequency = <200000000>;
	bus-width = <8>;
	cap-mmc-highspeed;
//	mmc-hs200-1_8v;
	mmc-ddr-1_8v;
	disable-wp;
	non-removable;
	num-slots = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
	status = "okay";
	supports-emmc;
	clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
	         <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
	clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
};

&gmac2io {
	assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
	assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
	clock_in_out = "input";
	phy-supply = <&vcc_phy>;
	phy-mode = "rgmii";
	pinctrl-names = "default";
	pinctrl-0 = <&rgmiim1_pins>;
	rockchip,bugged_tx_coe;
	snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
	snps,reset-active-low;
	snps,reset-delays-us = <0 10000 50000>;
	tx_delay = <0x24>;
	rx_delay = <0x18>;
	status = "disabled";
};

&gpu {
	status = "okay";
};

&hdmi {
	status = "okay";

	port@0 {
		hdmi_p0_0: endpoint {
			remote-endpoint = <&i2s0_p0_0>;
		};
	};
};

&hdmiphy {
	status = "okay";
};

&gmac2phy {
	phy-supply = <&vcc_phy>;
	clock_in_out = "output";
	assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
	assigned-clock-rate = <50000000>;
	assigned-clocks = <&cru SCLK_MAC2PHY>;
	assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
	status = "okay";
};

&i2c1 {
	status = "disabled";

//	rk805: rk805@18 {
//		compatible = "rockchip,rk805";
//		reg = <0x18>;
//		interrupt-parent = <&gpio2>;
//		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
//		#clock-cells = <1>;
//		clock-output-names = "xin32k", "rk805-clkout2";
//		gpio-controller;
//		#gpio-cells = <2>;
//		pinctrl-names = "default";
//		pinctrl-0 = <&pmic_int_l>;
//		rockchip,system-power-controller;
//		wakeup-source;
//
//		vcc1-supply = <&vcc_sys>;
//		vcc2-supply = <&vcc_sys>;
//		vcc3-supply = <&vcc_sys>;
//		vcc4-supply = <&vcc_sys>;
//		vcc5-supply = <&vcc_io>;
//		vcc6-supply = <&vcc_sys>;
//
//		regulators {
//			vdd_logic: DCDC_REG1 {
//				regulator-name = "vdd_logic";
//				regulator-min-microvolt = <712500>;
//				regulator-max-microvolt = <1450000>;
//				regulator-initial-mode = <0x1>;
//				regulator-ramp-delay = <12500>;
//				regulator-always-on;
//				regulator-boot-on;
//				regulator-state-mem {
//					regulator-mode = <0x2>;
//					regulator-on-in-suspend;
//					regulator-suspend-microvolt = <1000000>;
//				};
//			};
//
//			vdd_arm: DCDC_REG2 {
//				regulator-name = "vdd_arm";
//				regulator-min-microvolt = <712500>;
//				regulator-max-microvolt = <1450000>;
//				regulator-initial-mode = <0x1>;
//				regulator-ramp-delay = <12500>;
//				regulator-always-on;
//				regulator-boot-on;
//				regulator-state-mem {
//					regulator-mode = <0x2>;
//					regulator-on-in-suspend;
//					regulator-suspend-microvolt = <950000>;
//				};
//			};
//
//			vcc_ddr: DCDC_REG3 {
//				regulator-name = "vcc_ddr";
//				regulator-initial-mode = <0x1>;
//				regulator-always-on;
//				regulator-boot-on;
//				regulator-state-mem {
//					regulator-mode = <0x2>;
//					regulator-on-in-suspend;
//				};
//			};
//
//			vcc_io: DCDC_REG4 {
//				regulator-name = "vcc_io";
//				regulator-min-microvolt = <3300000>;
//				regulator-max-microvolt = <3300000>;
//				regulator-initial-mode = <0x1>;
//				regulator-always-on;
//				regulator-boot-on;
//				regulator-state-mem {
//					regulator-mode = <0x2>;
//					regulator-on-in-suspend;
//					regulator-suspend-microvolt = <3300000>;
//				};
//			};
//
//			vcc_18: LDO_REG1 {
//				regulator-name = "vcc_18";
//				regulator-min-microvolt = <1800000>;
//				regulator-max-microvolt = <1800000>;
//				regulator-always-on;
//				regulator-boot-on;
//				regulator-state-mem {
//					regulator-on-in-suspend;
//					regulator-suspend-microvolt = <1800000>;
//				};
//			};
//
//			vcc18_emmc: LDO_REG2 {
//				regulator-name = "vcc18_emmc";
//				regulator-min-microvolt = <1800000>;
//				regulator-max-microvolt = <1800000>;
//				regulator-always-on;
//				regulator-boot-on;
//				regulator-state-mem {
//					regulator-on-in-suspend;
//					regulator-suspend-microvolt = <1800000>;
//				};
//			};
//
//			vdd_10: LDO_REG3 {
//				regulator-name = "vdd_10";
//				regulator-min-microvolt = <1000000>;
//				regulator-max-microvolt = <1000000>;
//				regulator-always-on;
//				regulator-boot-on;
//				regulator-state-mem {
//					regulator-on-in-suspend;
//					regulator-suspend-microvolt = <1000000>;
//				};
//			};
//		};
//	};
};

&i2s0 {
	status = "okay";

	i2s0_p0: port {
		i2s0_p0_0: endpoint {
			dai-format = "i2s";
			mclk-fs = <256>;
			remote-endpoint = <&hdmi_p0_0>;
		};
	};
};

&i2s1 {
	status = "okay";

	i2s1_p0: port {
		i2s1_p0_0: endpoint {
			dai-format = "i2s";
			mclk-fs = <256>;
			remote-endpoint = <&codec_p0_0>;
		};
	};
};

&io_domains {
	status = "okay";

/*	vccio1-supply = <&vcc_io>;
	vccio2-supply = <&vcc18_emmc>;
	vccio3-supply = <&vcc_io>;
	vccio4-supply = <&vcc_18>;
	vccio5-supply = <&vcc_io>;
	vccio6-supply = <&vcc_io>;
	pmuio-supply = <&vcc_io>; */
};

&pinctrl {
/*	ir {
		ir_int: ir-int {
			rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	}; */

/*	pmic {
		pmic_int_l: pmic-int-l {
			rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	}; */

	usb2 {
		usb20_host_drv: usb20-host-drv {
			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	usb3 {
		usb30_host_drv: usb30-host-drv {
			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};

&sdio {
	status = "okay";
};

&sdmmc {
	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	cd-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>;
	disable-wp;
	max-frequency = <100000000>;
	card-detect-delay = <800>;
	num-slots = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
	supports-sd;
/*	vmmc-supply = <&vcc_sd>;
	vqmmc-supply = <&vcc_sd>; */
	status = "okay";
};

&spdif {
	pinctrl-0 = <&spdifm0_tx>;
	status = "okay";

	spdif_p0: port {
		spdif_p0_0: endpoint {
			remote-endpoint = <&dit_p0_0>;
		};
	};
};

//&spi0 {
//	status = "okay";
//
//	spiflash@0 {
//		compatible = "gigadevice,gd25q128", "jedec,spi-nor";
//		reg = <0>;
//		m25p,fast-read;
//
//		/* maximum speed for Rockchip SPI */
//		spi-max-frequency = <50000000>;
//
//		partitions {
//			compatible = "fixed-partitions";
//			#address-cells = <1>;
//			#size-cells = <1>;
//
//			loader@8000 {
//				label = "loader";
//				reg = <0x8000 0x3F0000>;
//			};
//		};
//	};
//};

&pwm0 {
	status = "okay";
};

&tsadc {
	rockchip,hw-tshut-mode = <0>;
	rockchip,hw-tshut-polarity = <0>;
	status = "okay";
};

&uart2 {
	status = "okay";
};

&u2phy {
	status = "okay";
};

&u2phy_host {
	status = "okay";
};

&u2phy_otg {
	status = "okay";
};

&usb20_otg {
	dr_mode = "host";
	status = "okay";
};

&usb_host0_ehci {
	status = "okay";
};

&usb_host0_ohci {
	status = "okay";
};

&vop {
	status = "okay";
};

&vop_mmu {
	status = "okay";
};

&usbdrd3 {
	status = "okay";
};

//&usbdrd_dwc3 {
//	dr_mode = "host";
//	status = "okay";
//};

//&spi0 {
// 	status = "okay";
// 
// 	/* SPI DMA does not work currently */
// 	/delete-property/ dmas;
// 	/delete-property/ #dma-cells;
// 	/delete-property/ dma-names;
// 
// 	 spi-flash@0 {
// 		#address-cells = <0x1>;
// 		#size-cells = <1>;
// 		compatible = "jedec,spi-nor";
// 		reg = <0x0>;
// 		spi-max-frequency = <25000000>;
// 		status = "okay";
// 		m25p,fast-read;
// 
// 		partitions {
// 			compatible = "fixed-partitions";
// 			#address-cells = <1>;
// 			#size-cells = <1>;
// 
// 			loader@8000 {
// 				label = "loader";
// 				reg = <0x8000 0x3F0000>;
// 			};
// 		};
// 	};
//};