GitHub - hmdgharb/5-Staged-MIPS-Pipeline: this software is part of main project in Computer Architecture Laboratory which has been held in University of Tehran. for developing this project, i have used verilog Language in modelsim software. this project has been constructed, according to 5 staged MIPS pipeline (i.e. DesignSheet.jpg which included in the Design folder). the instruction set length of this project is 16 bit. the ALU of this Mips pipeline can do operation in Instruction Set of Type: R-Type Instruction set(register type: NOP, ADD, SUB, AND, OR, XOR, SL, SR, SRU, MUL) and I-Type Instruction set(Imediate Type: ADDI, LD, ST, BZ, JMP).

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this software is part of main project in Computer Architecture Laboratory which has been held in University of Tehran. for developing this project, i have used verilog Language in modelsim software. this project has been constructed, according to 5 staged MIPS pipeline (i.e. DesignSheet.jpg which included in the Design folder). the instruction s…

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Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
Design		Design
work		work
ALU.v		ALU.v
ALU.v.bak		ALU.v.bak
Add.v		Add.v
Add.v.bak		Add.v.bak
CONTROLLER.v		CONTROLLER.v
CONTROLLER.v.bak		CONTROLLER.v.bak
DM.v.bak		DM.v.bak
DataMemory.v		DataMemory.v
DataMemory.v.bak		DataMemory.v.bak
EX_MEM.v		EX_MEM.v
EX_MEM.v.bak		EX_MEM.v.bak
EX_STAGE.v		EX_STAGE.v
EX_STAGE.v.bak		EX_STAGE.v.bak
HAZARD.v		HAZARD.v
HAZARD.v.bak		HAZARD.v.bak
ID_EX.v		ID_EX.v
ID_EX.v.bak		ID_EX.v.bak
ID_STAGE.v		ID_STAGE.v
ID_STAGE.v.bak		ID_STAGE.v.bak
IF_ID.v		IF_ID.v
IF_ID.v.bak		IF_ID.v.bak
IF_STAGE.v		IF_STAGE.v
IF_STAGE.v.bak		IF_STAGE.v.bak
IR.v.bak		IR.v.bak
InstructionMemory.v		InstructionMemory.v
InstructionMemory.v.bak		InstructionMemory.v.bak
LICENSE		LICENSE
MEM_STAGE.v		MEM_STAGE.v
MEM_STAGE.v.bak		MEM_STAGE.v.bak
MEM_WB.v		MEM_WB.v
MEM_WB.v.bak		MEM_WB.v.bak
MUX2.v		MUX2.v
MUX2.v.bak		MUX2.v.bak
MUX4.v		MUX4.v
MUX4.v.bak		MUX4.v.bak
PASSPRJ.cr.mti		PASSPRJ.cr.mti
PASSPRJ.mpf		PASSPRJ.mpf
PC.v		PC.v
PC.v.bak		PC.v.bak
Project.v		Project.v
Project.v.bak		Project.v.bak
RegisterFile.v		RegisterFile.v
RegisterFile.v.bak		RegisterFile.v.bak
SixToEightExtend.v		SixToEightExtend.v
SixToEightExtend.v.bak		SixToEightExtend.v.bak
SixToSixteen.v		SixToSixteen.v
SixToSixteen.v.bak		SixToSixteen.v.bak
WB_STAGE.v		WB_STAGE.v
WB_STAGE.v.bak		WB_STAGE.v.bak
add.prog		add.prog
addi.prog		addi.prog
addi_2.prog		addi_2.prog
bench.v		bench.v
bench.v.bak		bench.v.bak
data.dat		data.dat
readme.txt		readme.txt
store_load.prog		store_load.prog
vsim.wlf		vsim.wlf

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this is free software for use or redistribute. for use this software, you need to have install modelsim software.
run modelsim.exe, in next step go to File->Open and then select Project File(*.ini, *.mpf) in the folder which contins these files. have fun :)