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08. memory management.md

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8์žฅ memory management

01 Logical vs Physical Address

Logical Address (Virtual Address)

  • ํ”„๋กœ์„ธ์Šค๋งˆ๋‹ค ๋…๋ฆฝ์ ์œผ๋กœ ๊ฐ€์ง€๋Š” ์ฃผ์†Œ ๊ณต๊ฐ„
  • ๊ฐ ํ”„๋กœ์„ธ์Šค๋งˆ๋‹ค 0๋ฒˆ์ง€๋ถ€ํ„ฐ ์‹œ์ž‘
  • CPU๊ฐ€ ๋ณด๋Š” ์ฃผ์†Œ๋Š” Logical Address

Physical Address

  • ๋ฉ”๋ชจ๋ฆฌ์— ์‹ค์ œ ์˜ฌ๋ผ๊ฐ€๋Š” ์œ„์น˜

02 ์ฃผ์†Œ ๋ฐ”์ธ๋”ฉ (Address Binding)

์ฃผ์†Œ ๋ฐ”์ธ๋”ฉ: ์ฃผ์†Œ๋ฅผ ๊ฒฐ์ •ํ•˜๋Š” ๊ฒƒ

  • Symbolic Address โ†’ Logical Address โ†’ Physical Address

image

์ปดํŒŒ์ผ ์‹œ: (์—„๋ฐ€ํ•˜๊ฒŒ ๋งํ•˜๋ฉด assembler์— ์˜ํ•ด) ๋…ผ๋ฆฌ์  ์ฃผ์†Œ๋ฅผ ๊ฐ–๋Š” ์‹คํ–‰ ํŒŒ์ผ์ด ์ƒ์„ฑ

์‹คํ–‰์‹œ์ž‘ ์‹œ: loader์— ์˜ํ•ด physical address๊ฐ€ ํ• ๋‹น๋จ

Compile time binding

  • ๋ฌผ๋ฆฌ์  ๋ฉ”๋ชจ๋ฆฌ ์ฃผ์†Œ๊ฐ€ ์ปดํŒŒ์ผ ์‹œ ์ด๋ฏธ ์•Œ๋ ค์ง
  • ์‹œ์ž‘ ์œ„์น˜ ๋ณ€๊ฒฝ์‹œ ์žฌ์ปดํŒŒ์ผ
  • ์ปดํŒŒ์ผ๋Ÿฌ๋Š” ์ ˆ๋Œ€ ์ฝ”๋“œ(absolute code) ์ƒ์„ฑ - ์ ˆ๋Œ€ ์•ˆ ์›€์ง์ด๋‹ˆ๊นŒ

Load time binding

  • loader์˜ ์ฑ…์ž„ํ•˜์— ๋ฌผ๋ฆฌ์  ๋ฉ”๋ชจ๋ฆฌ ์ฃผ์†Œ ๋ถ€์—ฌ
  • ์ปดํŒŒ์ผ๋Ÿฌ๊ฐ€ ์žฌ๋ฐฐ์น˜๊ฐ€๋Šฅ ์ฝ”๋“œ (relocatable code) ๋ฅผ ์ƒ์„ฑํ•œ ๊ฒฝ์šฐ ๊ฐ€๋Šฅ - ์ƒ๋Œ€ ์ฃผ์†Œ๋Š” ๊ณ ์ •๋˜๊ณ , ์ ˆ๋Œ€ ์ฃผ์†Œ๋Š” ๋ณ€๊ฒฝ ๊ฐ€๋Šฅ

Execution time binding (Run Time Binding)

  • ์ˆ˜ํ–‰์ด ์‹œ์ž‘๋œ ์ดํ›„์—๋„ ํ”„๋กœ์„ธ์Šค์˜ ๋ฉ”๋ชจ๋ฆฌ ์ƒ ์œ„์น˜๋ฅผ ์˜ฎ๊ธธ ์ˆ˜ ์žˆ์Œ

  • CPU๊ฐ€ ์ฃผ์†Œ๋ฅผ ์ฐธ์กฐํ•  ๋•Œ๋งˆ๋‹ค Binding์„ ์ ๊ฒ€ (Address Mapping Table - 300์˜€๋Š”๋ฐ ์ง€๊ธˆ ์•ˆ๋ฐ”๊ผˆ๋‹ˆ ์™€ ๊ฐ™์ด ๋ฌผ์–ด๋ด„)

  • ํ•˜๋“œ์›จ์–ด์ ์ธ ์ง€์›์ด ํ•„์š”

    (base limit registers, MMU)

03 Memory Management Unit (MMU)

Dynamic Relocation ์‹œ, Hardware Support for Address Translation

image

MMU (Memory Management Unit)

  • Logical address๋ฅผ Physical Address๋กœ ๋งคํ•‘ํ•ด ์ฃผ๋Š” Hardware device

MMU Scheme

  • ์‚ฌ์šฉ์ž ํ”„๋กœ์„ธ์Šค๊ฐ€ CPU์—์„œ ์ˆ˜ํ–‰๋˜๋ฉฐ ์ƒ์„ฑํ•ด์ฃผ๋Š” ๋ชจ๋“  ์ฃผ์†Œ๊ฐ’์— ๋Œ€ํ•ด (cpu๋Š” 0๋ฒˆ์ง€์—์„œ๋ถ€ํ„ฐ ์‹œ์ž‘ํ•˜๋Š” logical address๋งŒ ์•ˆ๋‹ค) Base Register (= Relocation Register)์˜ ๊ฐ’์„ ๋”ํ•œ๋‹ค.

User Program

  • Logical Address๋งŒ์„ ๋‹ค๋ฃฌ๋‹ค.
  • ์‹ค์ œ Physical Address๋ฅผ ๋ณผ ์ˆ˜ ์—†์œผ๋ฉฐ ์•Œ ํ•„์š”๊ฐ€ ์—†๋‹ค.

์šด์˜์ฒด์ œ ๋ฐ ์‚ฌ์šฉ์ž ํ”„๋กœ์„ธ์Šค ๊ฐ„์˜ ๋ฉ”๋ชจ๋ฆฌ ๋ณดํ˜ธ๋ฅผ ์œ„ํ•ด ์‚ฌ์šฉํ•˜๋Š” ๋ ˆ์ง€์Šคํ„ฐ

  • Relocation Register (Base Register): ์ ‘๊ทผํ•  ์ˆ˜ ์žˆ๋Š” ๋ฌผ๋ฆฌ์  ๋ฉ”๋ชจ๋ฆฌ ์ฃผ์†Œ์˜ ์ตœ์†Œ๊ฐ’

  • Limit Register: ๋…ผ๋ฆฌ์  ์ฃผ์†Œ์˜ ๋ฒ”์œ„

    • logical address < limit register๋ฅผ ๋งŒ์กฑํ•˜์ง€ ๋ชปํ•˜๋ฉด trap (software interrupt - exception ๋ฐœ์ƒ)

      kernal์ด ๋ณดํ†ต process๋ฅผ killํ•˜๊ณ  ์‚ฌ์šฉ์ž์—๊ฒŒ segmentation fault๊ฐ€ ๋‚˜์„œ ํ”„๋กœ๊ทธ๋žจ์ด ๋๋‚ฌ์Œ์„ ์•Œ๋ฆฐ๋‹ค.

04 ์šฉ์–ด ์ •๋ฆฌ

04-1 Dynamic Loading

  • ํ”„๋กœ์„ธ์Šค ์ „์ฒด๋ฅผ ๋ฉ”๋ชจ๋ฆฌ์— ๋ฏธ๋ฆฌ ๋‹ค ์˜ฌ๋ฆฌ๋Š” ๊ฒƒ์ด ์•„๋‹ˆ๋ผ ํ•ด๋‹น ๋ฃจํ‹ด์ด ๋ถˆ๋ ค์งˆ ๋•Œ ๋ฉ”๋ชจ๋ฆฌ์— loadํ•˜๋Š” ๊ฒƒ
  • Memory Utilization์˜ ํ–ฅ์ƒ
  • ๊ฐ€๋”์”ฉ ์‚ฌ์šฉ๋˜๋Š” ๋งŽ์€ ์–‘์˜ ์ฝ”๋“œ์˜ ๊ฒฝ์šฐ ์œ ์šฉ
    • ex) ์˜ค๋ฅ˜ ์ฒ˜๋ฆฌ ๋ฃจํ‹ด
  • ์šด์˜์ฒด์ œ์˜ ํŠน๋ณ„ํ•œ ์ง€์› ์—†์ด ํ”„๋กœ๊ทธ๋žจ ์ž์ฒด์—์„œ ๊ตฌํ˜„ ๊ฐ€๋Šฅ
    • OS๋Š” ๋ผ์ด๋ธŒ๋Ÿฌ๋ฆฌ๋ฅผ ํ†ตํ•ด ์ง€์› ๊ฐ€๋Šฅ. ์ฆ‰ OS ์ž์ฒด์˜ ๊ธฐ๋Šฅ์€ ์•„๋‹˜

* Loading: ๋ฉ”๋ชจ๋ฆฌ์— ๋ฐ์ดํ„ฐ๋ฅผ ์˜ฌ๋ฆฌ๋Š” ๊ฒƒ

์—ฌ๊ธฐ์„œ ๋งํ•˜๋Š” Dynamic Loading์€ ์šด์˜์ฒด์ œ๊ฐ€ ํ•˜๋Š” ๊ฒƒ์ด ์•„๋‹Œ ํ”„๋กœ๊ทธ๋ž˜๋จธ๊ฐ€ ์ง„ํ–‰ํ•˜๋Š” ๊ฒƒ์„ ๋งํ•จ.

04-2 Dynamic Linking

  • Linking์„ ์‹คํ–‰ ์‹œ๊ฐ„ (Execution Time)๊นŒ์ง€ ๋ฏธ๋ฃจ๋Š” ๊ธฐ๋ฒ•
  • Static Linking
    • ๋ผ์ด๋ธŒ๋Ÿฌ๋ฆฌ๊ฐ€ ํ”„๋กœ๊ทธ๋žจ์˜ ์‹คํ–‰ ํŒŒ์ผ ์ฝ”๋“œ์— ํฌํ•จ๋จ
    • ์‹คํ–‰ ํŒŒ์ผ์˜ ํฌ๊ธฐ๊ฐ€ ์ปค์ง
    • ๋™์ผํ•œ ๋ผ์ด๋ธŒ๋Ÿฌ๋ฆฌ๋ฅผ ๊ฐ๊ฐ์˜ ํ”„๋กœ์„ธ์Šค๊ฐ€ ๋ฉ”๋ชจ๋ฆฌ์— ์˜ฌ๋ฆฌ๋ฏ€๋กœ ๋ฉ”๋ชจ๋ฆฌ ๋‚ญ๋น„
    • ์˜ˆ) printf ํ•จ์ˆ˜์˜ ๋ผ์ด๋ธŒ๋Ÿฌ๋ฆฌ ์ฝ”๋“œ
  • Dynamic Linking
    • ๋ผ์ด๋ธŒ๋Ÿฌ๋ฆฌ๊ฐ€ ์‹คํ–‰์‹œ ์—ฐ๊ฒฐ๋จ
    • ๋ผ์ด๋ธŒ๋Ÿฌ๋ฆฌ ํ˜ธ์ถœ ๋ถ€๋ถ„์— ๋ผ์ด๋ธŒ๋Ÿฌ๋ฆฌ ๋ฃจํ‹ด์˜ ์œ„์น˜๋ฅผ ์ฐพ๊ธฐ ์œ„ํ•œ stub์ด๋ผ๋Š” ์ž‘์€ ์ฝ”๋“œ๋ฅผ ๋‘ 
    • ๋ผ์ด๋ธŒ๋Ÿฌ๋ฆฌ๊ฐ€ ์ด๋ฏธ ๋ฉ”๋ชจ๋ฆฌ์— ์žˆ์œผ๋ฉด ๊ทธ ๋ฃจํ‹ด์˜ ์ฃผ์†Œ๋กœ ๊ฐ€๊ณ  ์—†์œผ๋ฉด ๋””์Šคํฌ์—์„œ ์ฝ์–ด์˜ด
    • ์šด์˜์ฒด์ œ์˜ ๋„์›€์ด ํ•„์š”

04-3 Overlays

  • ๋ฉ”๋ชจ๋ฆฌ์— ํ”„๋กœ์„ธ์Šค์˜ ๋ถ€๋ถ„ ์ค‘ ์‹ค์ œ ํ•„์š”ํ•œ ์ •๋ณด๋งŒ์„ ์˜ฌ๋ฆผ
  • ํ”„๋กœ์„ธ์Šค์˜ ํฌ๊ธฐ๊ฐ€ ๋ฉ”๋ชจ๋ฆฌ๋ณด๋‹ค ํด ๋•Œ ์œ ์šฉ
  • ์šด์˜์ฒด์ œ์˜ ์ง€์›์—†์ด ์‚ฌ์šฉ์ž์— ์˜ํ•ด ๊ตฌํ˜„
  • ์ž‘์€ ๊ณต๊ฐ„์˜ ๋ฉ”๋ชจ๋ฆฌ๋ฅผ ์‚ฌ์šฉํ•˜๋˜ ์ดˆ์ฐฝ๊ธฐ ์‹œ์Šคํ…œ์—์„œ ์ˆ˜์ž‘์—…์œผ๋กœ ํ”„๋กœ๊ทธ๋ž˜๋จธ๊ฐ€ ๊ตฌํ˜„
    • Manual Overlay ๋ผ๊ณ ๋„ ๋ถ€๋ฆ„
    • ํ”„๋กœ๊ทธ๋ž˜๋ฐ์ด ๋งค์šฐ ๋ณต์žก

04-4 Swapping

image

  • Swapping

    • ํ”„๋กœ์„ธ์Šค๋ฅผ ์ผ์‹œ์ ์œผ๋กœ ๋ฉ”๋ชจ๋ฆฌ์—์„œ Backing Store๋กœ ์ซ“์•„๋‚ด๋Š” ๊ฒƒ
    • paging๊ณผ ๋‹ค๋ฅด๊ฒŒ ํ”„๋กœ์„ธ์Šค๊ฐ€ ํ†ต์งธ๋กœ ์›€์ง์ž„.
  • Backing Store (Swap area)

    • ๋””์Šคํฌ(disk): ๋งŽ์€ ์‚ฌ์šฉ์ž์˜ ํ”„๋กœ์„ธ์Šค ์ด๋ฏธ์ง€๋ฅผ ๋‹ด์„ ๋งŒํผ ์ถฉ๋ถ„ํžˆ ๋น ๋ฅด๊ณ  ํฐ ์ €์žฅ ๊ณต๊ฐ„
  • Swap in / Swap out

    • ์ผ๋ฐ˜์ ์œผ๋กœ ์ค‘๊ธฐ ์Šค์ผ€์ฅด๋Ÿฌ(swapper)์— ์˜ํ•ด swap out ์‹œํ‚ฌ ํ”„๋กœ์„ธ์Šค ์„ ์ •
    • priority-based CPU scheduling algorithm
      • ์šฐ์„ ์ˆœ์œ„๊ฐ€ ๋‚ฎ์€ ํ”„๋กœ์„ธ์Šค๋ฅผ swapped out ์‹œํ‚ด
      • ์šฐ์„ ์ˆœ์œ„๊ฐ€ ๋†’์€ ํ”„๋กœ์„ธ์Šค๋ฅผ ๋ฉ”๋ชจ๋ฆฌ์— ์˜ฌ๋ ค ๋†“์Œ
    • Compile Time ํ˜น์€ Load time binding์—์„œ๋Š” ์›๋ž˜ ๋ฉ”๋ชจ๋ฆฌ ์œ„์น˜๋กœ swap in ํ•ด์•ผ ํ•จ
    • Execution time binding์—์„œ๋Š” ์ถ”ํ›„ ๋นˆ ๋ฉ”๋ชจ๋ฆฌ ์˜์—ญ ์•„๋ฌด ๊ณณ์—๋‚˜ ์˜ฌ๋ฆด ์ˆ˜ ์žˆ์Œ
    • Swap Time์€ ๋Œ€๋ถ€๋ถ„ Transfer time (swap ๋˜๋Š” ์–‘์— ๋น„๋ก€ํ•˜๋Š” ์‹œ๊ฐ„)์ž„

05 Allocation of Physical Memory

image

  • ๋ฉ”๋ชจ๋ฆฌ๋Š” ์ผ๋ฐ˜์ ์œผ๋กœ ๋‘ ์˜์—ญ์œผ๋กœ ๋‚˜๋‰˜์–ด ์‚ฌ์šฉ

    • OS ์ƒ์ฃผ ์˜์—ญ: Interrupt Vector์™€ ํ•จ๊ป˜ ๋‚ฎ์€ ์ฃผ์†Œ ์˜์—ญ ์‚ฌ์šฉ
    • ์‚ฌ์šฉ์ž ํ”„๋กœ์„ธ์Šค ์˜์—ญ: ๋†’์€ ์ฃผ์†Œ ์˜์—ญ ์‚ฌ์šฉ
  • ์‚ฌ์šฉ์ž ํ”„๋กœ์„ธ์Šค ์˜์—ญ์˜ ํ• ๋‹น ๋ฐฉ๋ฒ•

    • Contiguous allocation
      • ๊ฐ๊ฐ์˜ ํ”„๋กœ์„ธ์Šค๊ฐ€ ๋ฉ”๋ชจ๋ฆฌ์˜ ์—ฐ์†์ ์ธ ๊ณต๊ฐ„์— ์ ์žฌ๋˜๋„๋ก ํ•˜๋Š” ๊ฒƒ
      • Fixed Partition Allocation - ๊ณ ์ • ๋ถ„ํ•  ๋ฐฉ์‹
      • Variable Partition Allocation - ๊ฐ€๋ณ€ ๋ถ„ํ•  ๋ฐฉ์‹
    • Noncontiguous allocation
      • ํ•˜๋‚˜์˜ ํ”„๋กœ์„ธ์Šค๊ฐ€ ๋ฉ”๋ชจ๋ฆฌ์˜ ์—ฌ๋Ÿฌ ์˜์—ญ์— ๋ถ„์‚ฐ๋˜์–ด ์˜ฌ๋ผ๊ฐˆ ์ˆ˜ ์žˆ์Œ
      • Paging
      • Segmentation
      • Paged Segmentation

06 Contiguous Allocation

06-1. ๊ณ ์ • ๋ถ„ํ• (Fixed Partition) ๋ฐฉ์‹๊ณผ ๊ฐ€๋ณ€ ๋ถ„ํ• (Variable Partition) ๋ฐฉ์‹

image

  • ๊ณ ์ • ๋ถ„ํ• (Fixed Partition) ๋ฐฉ์‹

    • ๋ฌผ๋ฆฌ์  ๋ฉ”๋ชจ๋ฆฌ๋ฅผ ๋ช‡ ๊ฐœ์˜ ์˜๊ตฌ์  ๋ถ„ํ• (partition)๋กœ ๋‚˜๋ˆ”
    • ๋ถ„ํ• ์˜ ํฌ๊ธฐ๊ฐ€ ๋ชจ๋‘ ๋™์ผํ•œ ๋ฐฉ์‹๊ณผ ์„œ๋กœ ๋‹ค๋ฅธ ๋ฐฉ์‹์ด ์กด์žฌ
    • ๋ถ„ํ• ๋‹น ํ•˜๋‚˜์˜ ํ”„๋กœ๊ทธ๋žจ ์ ์žฌ
    • ์œตํ†ต์„ฑ์ด ์—†์Œ
      • ๋™์‹œ์— ๋ฉ”๋ชจ๋ฆฌ์— load๋˜๋Š” ํ”„๋กœ๊ทธ๋žจ์˜ ์ˆ˜๊ฐ€ ๊ณ ์ •๋จ (4๊ฐœ์˜ ๋ถ„ํ•  โ†’ ๋™์‹œ์— ์ตœ๋Œ€ 4๊ฐœ ํ”„๋กœ๊ทธ๋žจ ๋กœ๋“œ)
      • ์ตœ๋Œ€ ์ˆ˜ํ–‰ ๊ฐ€๋Šฅ ํ”„๋กœ๊ทธ๋žจ ํฌ๊ธฐ ์ œํ•œ
    • Internal Fragmentation ๋ฐœ์ƒ (External Fragmentation๋„ ๋ฐœ์ƒ)
  • ๊ฐ€๋ณ€ ๋ถ„ํ• (Variable Partition) ๋ฐฉ์‹

    • ํ”„๋กœ๊ทธ๋žจ์˜ ํฌ๊ธฐ๋ฅผ ๊ณ ๋ คํ•ด์„œ ํ• ๋‹น
    • ๋ถ„ํ• ์˜ ํฌ๊ธฐ, ๊ฐœ์ˆ˜๊ฐ€ ๋™์ ์œผ๋กœ ํ• ๋‹น
    • ๊ธฐ์ˆ ์  ๊ด€๋ฆฌ ๊ธฐ๋ฒ• ํ•„์š”
    • External Fragmentation ๋ฐœ์ƒ

06-2. Fragmentation๊ณผ Hole

  • fragmentation

    • External fragmentation (์™ธ๋ถ€ ์กฐ๊ฐ)
      • ํ”„๋กœ๊ทธ๋žจ์˜ ํฌ๊ธฐ๋ณด๋‹ค ๋ถ„ํ• ์˜ ํฌ๊ธฐ๊ฐ€ ์ž‘์€ ๊ฒฝ์šฐ
      • ์•„๋ฌด ํ”„๋กœ๊ทธ๋žจ์—๋„ ๋ฐฐ์ •๋˜์ง€ ์•Š์€ ๋นˆ ๊ณณ์ธ๋ฐ๋„ ํ”„๋กœ๊ทธ๋žจ์ด ์˜ฌ๋ผ๊ฐˆ ์ˆ˜ ์—†๋Š” ์ž‘์€ ๋ถ„ํ• 
    • Internal fragmentation (๋‚ด๋ถ€ ์กฐ๊ฐ)
      • ํ”„๋กœ๊ทธ๋žจ ํฌ๊ธฐ๋ณด๋‹ค ๋ถ„ํ• ์˜ ํฌ๊ธฐ๊ฐ€ ํฐ ๊ฒฝ์šฐ
      • ํ•˜๋‚˜์˜ ๋ถ„ํ•  ๋‚ด๋ถ€์—์„œ ๋ฐœ์ƒํ•˜๋Š” ์‚ฌ์šฉ๋˜์ง€ ์•Š๋Š” ๋ฉ”๋ชจ๋ฆฌ ์กฐ๊ฐ
      • ํŠน์ • ํ”„๋กœ๊ทธ๋žจ์— ๋ฐฐ์ •๋˜์—ˆ์ง€๋งŒ ์‚ฌ์šฉ๋˜์ง€ ์•Š๋Š” ๊ณต๊ฐ„
  • Hole

    • ๊ฐ€์šฉ ๋ฉ”๋ชจ๋ฆฌ ๊ณต๊ฐ„
    • ๋‹ค์–‘ํ•œ ํฌ๊ธฐ์˜ hole๋“ค์ด ๋ฉ”๋ชจ๋ฆฌ ์—ฌ๋Ÿฌ ๊ณณ์— ํฉ์–ด์ ธ ์žˆ์Œ
    • ํ”„๋กœ์„ธ์Šค๊ฐ€ ๋„์ฐฉํ•˜๋ฉด ์ˆ˜์šฉ๊ฐ€๋Šฅํ•œ hole์„ ํ• ๋‹น
    • ์šด์˜์ฒด์ œ๋Š” ๋‹ค์Œ์˜ ์ •๋ณด๋ฅผ ์œ ์ง€
      • ํ• ๋‹น ๊ณต๊ฐ„
      • ๊ฐ€์šฉ ๊ณต๊ฐ„ (Hole)

๋‘˜์€ ๋น„์Šทํ•œ๋ฐ ๋‰˜์•™์Šค๊ฐ€ ๋‹ค๋ฆ„

fragmentation์€ ์“ฐ์ง€ ๋ชปํ•˜๋Š” ๊ณต๊ฐ„(๋ฉ”๋ชจ๋ฆฌ ๋‚ญ๋น„), hole๋Š” ์“ธ ์ˆ˜ ์žˆ๋Š” ๊ณต๊ฐ„

06-3. Dynamic Storage Allocation Problem

๊ฐ€๋ณ€ ๋ถ„ํ•  ๋ฐฉ์‹์—์„œ Size n์ธ ์š”์ฒญ์„ ๋งŒ์กฑํ•˜๋Š” ๊ฐ€์žฅ ์ ์ ˆํ•œ hole์„ ์ฐพ๋Š” ๋ฌธ์ œ

  • First-fit

    • Size๊ฐ€ n์ด์ƒ์ธ ๊ฒƒ ์ค‘ ์ตœ์ดˆ๋กœ ์ฐพ์•„์ง€๋Š” hole์— ํ• ๋‹น
  • Best-fit

    • Size๊ฐ€ n ์ด์ƒ์ธ ๊ฐ€์žฅ ์ž‘์€ hole์„ ์ฐพ์•„์„œ ํ• ๋‹น
    • Hole๋“ค์˜ ๋ฆฌ์ŠคํŠธ๊ฐ€ ํฌ๊ธฐ์ˆœ์œผ๋กœ ์ •๋ ฌ๋˜์ง€ ์•Š์€ ๊ฒฝ์šฐ ๋ชจ๋“  hole์˜ ๋ฆฌ์ŠคํŠธ๋ฅผ ํƒ์ƒ‰ํ•ด์•ผํ•จ
    • ๋งŽ์€ ์ˆ˜์˜ ์•„์ฃผ ์ž‘์€ hole๋“ค์ด ์ƒ์„ฑ๋จ
  • Worst-fit

    • ๊ฐ€์žฅ ํฐ hole์— ํ• ๋‹น
    • ์—ญ์‹œ ๋ชจ๋“  ๋ฆฌ์ŠคํŠธ๋ฅผ ํƒ์ƒ‰ํ•ด์•ผ ํ•จ
    • ์ƒ๋Œ€์ ์œผ๋กœ ์•„์ฃผ ํฐ hole๋“ค์ด ์ƒ์„ฑ๋จ

์‹คํ—˜์ ์œผ๋กœ first-fit์ด๋‚˜ best-fit์ด worst-fit๋ณด๋‹ค ์†๋„์™€ ๊ณต๊ฐ„ ์ด์šฉ์„ ์ธก๋ฉด์—์„œ ํšจ๊ณผ์ ์ธ ๊ฒƒ์œผ๋กœ ์•Œ๋ ค์ง

06-4. Compaction (๋ญ‰์นจ)

  • External Fragmentation ๋ฌธ์ œ๋ฅผ ํ•ด๊ฒฐํ•˜๋Š” ํ•œ๊ฐ€์ง€ ๋ฐฉ๋ฒ•
  • ์‚ฌ์šฉ ์ค‘์ธ ๋ฉ”๋ชจ๋ฆฌ ์˜์—ญ์„ ํ•œ๊ตฐ๋ฐ๋กœ ๋ชฐ๊ณ  hole๋“ค์„ ๋‹ค๋ฅธ ํ•œ ๊ณณ์œผ๋กœ ๋ชฐ์•„ ํฐ block์„ ๋งŒ๋“œ๋Š” ๊ฒƒ
  • Compaction์€ ํ”„๋กœ์„ธ์Šค์˜ ์ฃผ์†Œ๊ฐ€ ์‹คํ–‰ ์‹œ๊ฐ„์— ๋™์ ์œผ๋กœ ์žฌ๋ฐฐ์น˜ ๊ฐ€๋Šฅํ•œ ๊ฒฝ์šฐ์—๋งŒ ์‹ค์‹œํ•  ์ˆ˜ ์žˆ๋‹ค.
    • ์ฆ‰, Execution time binding (=run time binding)์—์„œ ์ ์šฉ ๊ฐ€๋Šฅ
  • ๋งค์šฐ ๋น„์šฉ์ด ๋งŽ์ด ๋“œ๋Š” ๋ฐฉ๋ฒ•์ž„
  • ์ตœ์†Œํ•œ์˜ ๋ฉ”๋ชจ๋ฆฌ ์ด๋™์œผ๋กœ compactionํ•˜๋Š” ๋ฐฉ๋ฒ•์€ ๋งค์šฐ ๋ณต์žกํ•œ ๋ฌธ์ œ

07 Paging

07-1. paging์˜ ๊ธฐ๋ณธ

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Paging

  • Process์˜ virtual memory (logical memory)๋ฅผ ๋™์ผํ•œ ์‚ฌ์ด์ฆˆ์˜ page ๋‹จ์œ„๋กœ ๋‚˜๋ˆ”
  • Virtual Memory์˜ ๋‚ด์šฉ์ด Page ๋‹จ์œ„๋กœ noncontiguousํ•˜๊ฒŒ ์ €์žฅ๋จ
  • ์ผ๋ถ€๋Š” backing storage์—, ์ผ๋ถ€๋Š” physical memory์— ์ €์žฅ

Basic Method

  • physical memory๋ฅผ ๋™์ผํ•œ ํฌ๊ธฐ์˜ frame์œผ๋กœ ๋‚˜๋ˆ”
  • logical memory๋ฅผ ๋™์ผ ํฌ๊ธฐ์˜ page๋กœ ๋‚˜๋ˆ”
  • ๋ชจ๋“  ๊ฐ€์šฉ ํ”„๋ ˆ์ž„๋“ค์„ ๊ด€๋ฆฌ
  • page table์„ ์‚ฌ์šฉํ•˜์—ฌ logical address๋ฅผ physical address๋กœ ๋ณ€ํ™˜
  • external fragmentation ๋ฐœ์ƒ ์•ˆํ•จ (page์™€ frame ์‚ฌ์ด์ฆˆ๊ฐ€ ๊ฐ™๊ธฐ์— ์–ด๋””๋“  ๋„ฃ์„ ์ˆ˜ ์žˆ์Œ)
  • internal fragmentation ๋ฐœ์ƒ ๊ฐ€๋Šฅ (๋งˆ์ง€๋ง‰์œผ๋กœ ์ž˜๋ฆฐ ํŽ˜์ด์ง€๋Š” ๋ชจ๋“  ๊ณต๊ฐ„์„ ์‚ฌ์šฉํ•˜์ง€ ์•Š์„ ์ˆ˜ ์žˆ์Œ)

07-2 Address Translation

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page number๋ฅผ frame number๋กœ ๋ณ€ํ™˜ํ•˜์—ฌ physical address ๊ณ„์‚ฐ์„ ํ•˜์—ฌ ์ ‘๊ทผํ•  ์ˆ˜ ์žˆ๋‹ค.

  • CPU <page number (p), page offset (d)> ์ด ๋‘ ๊ฐ€์ง€๋กœ ๊ตฌ์„ฑ๋œ virtual address๋ฅผ ์‚ฌ์šฉํ•œ๋‹ค.
    • page number (p)
      • page table์˜ index๋กœ ์‚ฌ์šฉ
      • ํ•ด๋‹น index์—๋Š” ๊ทธ ํŽ˜์ด์ง€์˜ ๋ฌผ๋ฆฌ์  ๋ฉ”๋ชจ๋ฆฌ ์ƒ์˜ base address๊ฐ€ ์ €์žฅ๋จ
    • page offset (d)
      • base address ์™€ ๋”ํ•ด์ ธ์„œ physical address ๊ฐ€ ๊ตฌํ•ด์ง

07-3 Implementation of Page Table

image

  • page table์€ main memory์— ์ƒ์ฃผ
  • Page-Table Base Register (PTBR)๊ฐ€ Page Table์„ ๊ฐ€๋ฆฌํ‚ด
  • Page-Table Length Register (PTLR)๊ฐ€ ํ…Œ์ด๋ธ” ํฌ๊ธฐ๋ฅผ ๋ณด๊ด€
  • ๋ชจ๋“  ๋ฉ”๋ชจ๋ฆฌ ์ ‘๊ทผ ์—ฐ์‚ฐ์—๋Š” 2๋ฒˆ์˜ memory access ํ•„์š”
    • Page Table ์ ‘๊ทผ 1๋ฒˆ + ์‹ค์ œ data/Instruction ์ ‘๊ทผ 1๋ฒˆ
  • ์†๋„ ํ–ฅ์ƒ์„ ์œ„ํ•ด associative register ํ˜น์€ translation lock-aside buffer(TLB)๋ผ ๋ถˆ๋ฆฌ๋Š” ๊ณ ์†์˜ lookup hardware cache ์‚ฌ์šฉ

Associative registers (TLB) : parallel search๊ฐ€ ๊ฐ€๋Šฅ

  • TLB์—๋Š” page Table ์ค‘ ์ผ๋ถ€๋งŒ ์กด์žฌ
  • TLB์˜ Address Translation
    • page table ์ค‘ ์ผ๋ถ€๊ฐ€ associative register์— ๋ณด๊ด€๋˜์–ด ์žˆ์Œ
    • ๋งŒ์•ฝ ํ•ด๋‹น page num๊ฐ€ associative register์— ์žˆ๋Š” ๊ฒฝ์šฐ ๊ณง๋ฐ”๋กœ frame # num์„ ์–ป์Œ
    • ๊ทธ๋ ‡์ง€ ์•Š์€ ๊ฒฝ์šฐ main memory์— ์žˆ๋Š” page table๋กœ ๋ถ€ํ„ฐ frame # num์„ ์–ป์Œ
    • TLB๋Š” context switch ๋•Œ flush (remove old entries)

07-4 Effective Access Time

Associative register lookup time = e

memory cycle time = 1

Hit ratio = a (associative register์—์„œ ์ฐพ์•„์ง€๋Š” ๋น„์œจ)

Effective Access Time = (1 + e)a + (2 + e)(1 - a)

---> 2 + e - a

07-5 2 Level page table

page table์„ ์œ„ํ•œ ๊ณต๊ฐ„์„ ์ค„์ด๊ธฐ ์œ„ํ•ด ์‚ฌ์šฉ image

ํ˜„๋Œ€์˜ ์ปดํ“จํ„ฐ๋Š” address space๊ฐ€ ๋งค์šฐ ํฐ ํ”„๋กœ๊ทธ๋žจ์„ ์ง€์›

  • 32 bit address ์‚ฌ์šฉ์‹œ โ†’ 2^32 (4GB)์˜ ์ฃผ์†Œ ๊ณต๊ฐ„
    • Page Size๊ฐ€ 4K (2^(2+10))์‹œ 1M (2^20)๊ฐœ์˜ page table entry๊ฐ€ ํ•„์š”
    • ๊ฐ page entry๊ฐ€ 4B ์‹œ ํ”„๋กœ์„ธ์Šค ๋‹น (page table entry ์ˆ˜ * page entry size) 4M ์˜ page table ํ•„์š”
    • ๊ทธ๋Ÿฌ๋‚˜ ๋Œ€๋ถ€๋ถ„์˜ ํ”„๋กœ๊ทธ๋žจ์€ 4G์˜ ์ฃผ์†Œ ๊ณต๊ฐ„ ์ค‘ ์ง€๊ทนํžˆ ์ผ๋ถ€๋ถ„๋งŒ ์‚ฌ์šฉํ•˜๊ธฐ ๋•Œ๋ฌธ์— page table ๊ณต๊ฐ„์ด ์‹ฌํ•˜๊ฒŒ ๋‚ญ๋น„๋จ

โ†’ ํŽ˜์ด์ง€ ํ…Œ์ด๋ธ” ์ž์ฒด๋ฅผ ํŽ˜์ด์ง€๋กœ ๊ตฌ์„ฑ

โ†’ ์‚ฌ์šฉ๋˜์ง€ ์•Š๋Š” ์ฃผ์†Œ ๊ณต๊ฐ„์— ๋Œ€ํ•œ outer page table์˜ ์—”ํŠธ๋ฆฌ ๊ฐ’์€ NULL (๋Œ€์‘ํ•˜๋Š” inner page table์ด ์—†์Œ)

์˜ˆ์‹œ image

  • p1์€ outer page table์˜ index(page number)์ด๊ณ 
  • p2๋Š” outer page table์˜ page์—์„œ์˜ ๋ณ€์œ„(displacement) (page offset)

Multilevel Paging and Performance

  • Address Space๊ฐ€ ๋” ์ปค์ง€๋ฉด ๋‹ค๋‹จ๊ณ„ ํŽ˜์ด์ง€ ํ…Œ์ด๋ธ” ํ•„์š”
  • ๊ฐ ๋‹จ๊ณ„์˜ ํŽ˜์ด์ง€ ํ…Œ์ด๋ธ”์ด ๋ฉ”๋ชจ๋ฆฌ์— ์กด์žฌํ•˜๋ฏ€๋กœ Logical address์˜ physical address ๋ณ€ํ™˜์— ๋” ๋งŽ์€ ๋ฉ”๋ชจ๋ฆฌ ์ ‘๊ทผ ํ•„์š”
  • TLB๋ฅผ ํ†ตํ•ด ๋ฉ”๋ชจ๋ฆฌ ์ ‘๊ทผ ์‹œ๊ฐ„์„ ์ค„์ผ ์ˆ˜ ์žˆ์Œ
  • 4๋‹จ๊ณ„ ํŽ˜์ด์ง€ ํ…Œ์ด๋ธ”์„ ์‚ฌ์šฉํ•˜๋Š” ๊ฒฝ์šฐ
    • ๋ฉ”๋ชจ๋ฆฌ ์ ‘๊ทผ ์‹œ๊ฐ„์ด 100ns, TLB ์ ‘๊ทผ ์‹œ๊ฐ„์ด 20ns, hit ratio๊ฐ€ 98%์ธ ๊ฒฝ์šฐ
      • effective memory access time = 0.98 _ 120 + 0.02 _ 520 --> 128ns
      • ๊ฒฐ๊ณผ์ ์œผ๋กœ ์ฃผ์†Œ๋ณ€ํ™˜์„ ์œ„ํ•ด 28ns๋งŒ ์†Œ์š”

07-7 Memory Protection

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Page Table์˜ ๊ฐ entry๋งˆ๋‹ค ์•„๋ž˜์˜ bit๋ฅผ ๋‘”๋‹ค.

  • Protection bit
    • Page์— ๋Œ€ํ•œ ์ ‘๊ทผ ๊ถŒํ•œ (read/write/read-only)
  • Valid-invalid bit
    • valid๋Š” ํ•ด๋‹น ์ฃผ์†Œ์˜ frame์— ๊ทธ ํ”„๋กœ์„ธ์Šค๋ฅผ ๊ตฌ์„ฑํ•˜๋Š” ์œ ํšจํ•œ ๋‚ด์šฉ์ด ์žˆ์Œ์„ ๋œปํ•จ (์ ‘๊ทผ ํ—ˆ์šฉ)
    • invalid๋Š” ํ•ด๋‹น ์ฃผ์†Œ์˜ frame์— ์œ ํšจํ•œ ๋‚ด์šฉ์ด ์—†์Œ์„ ๋œปํ•จ (์ ‘๊ทผ ๋ถˆํ—ˆ)
      • ํ”„๋กœ์„ธ์Šค๊ฐ€ ๊ทธ ์ฃผ์†Œ ๋ถ€๋ถ„์„ ์‚ฌ์šฉํ•˜์ง€ ์•Š๋Š” ๊ฒฝ์šฐ
      • ํ•ด๋‹น ํŽ˜์ด์ง€๊ฐ€ ๋ฉ”๋ชจ๋ฆฌ์— ์˜ฌ๋ผ์™€ ์žˆ์ง€ ์•Š๊ณ  swap area์— ์žˆ๋Š” ๊ฒฝ์šฐ

07-8 Inverted Page Table

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Page Table์ด ๋งค์šฐ ํฐ ์ด์œ 

  • ๋ชจ๋“  process ๋ณ„๋กœ ๊ทธ logical address์— ๋Œ€์‘ํ•˜๋Š” ๋ชจ๋“  page์— ๋Œ€ํ•ด page table entry๊ฐ€ ์กด๋Œ€
  • ๋Œ€์‘ํ•˜๋Š” page๊ฐ€ ๋ฉ”๋ชจ๋ฆฌ์— ์žˆ๋“  ์•„๋‹ˆ๋“  ๊ฐ„์— page table์—๋Š” entry๋กœ ์กด์žฌ

Inverted Page table

  • Page frame ํ•˜๋‚˜๋‹น page table์— ํ•˜๋‚˜์˜ entry๋ฅผ ๋‘” ๊ฒƒ ( system - wide )
  • ๊ฐ page table entry๋Š” ๊ฐ๊ฐ์˜ ๋ฌผ๋ฆฌ์  ๋ฉ”๋ชจ๋ฆฌ์˜ page frame์ด ๋‹ด๊ณ  ์žˆ๋Š” ๋‚ด์šฉ ํ‘œ์‹œ (process-id, process์˜ logiscal address)
  • ๋‹จ์  : ํ…Œ์ด๋ธ” ์ „์ฒด๋ฅผ ํƒ์ƒ‰ํ•ด์•ผํ•จ
  • ์กฐ์น˜ : associative register ์‚ฌ์šฉ (expensive)

07-9 Shared Page

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Shared code

  • Re-entrant Code (=Pure code) : ์•„๋ž˜์˜ ๋‘ ์กฐ๊ฑด์„ ๋งŒ์กฑํ•ด์•ผํ•จ
    • read only๋กœ ํ•˜์—ฌ ํ”„๋กœ์„ธ์Šค ๊ฐ„์— ํ•˜๋‚˜์˜ code๋งŒ ๋ฉ”๋ชจ๋ฆฌ์— ์˜ฌ๋ฆผ
    • Shared code๋Š” ๋ชจ๋“  ํ”„๋กœ์„ธ์Šค์˜ logical address space์—์„œ ๋™์ผํ•œ ์œ„์น˜์— ์žˆ์–ด์•ผ ํ•จ

Private Code and Data

  • ๊ฐ ํ”„๋กœ์„ธ์Šค๋“ค์€ ๋…์ž์ ์œผ๋กœ ๋ฉ”๋ชจ๋ฆฌ์— ์˜ฌ๋ฆผ
  • Private data๋Š” logical address space์˜ ์•„๋ฌด๊ณณ์— ์™€๋„ ๋ฌด๋ฐฉ

08 Segmentation

08-1. Segment

ํ”„๋กœ๊ทธ๋žจ์€ ์˜๋ฏธ ๋‹จ์œ„์ธ ์—ฌ๋Ÿฌ ๊ฐœ์˜ segment๋กœ ๊ตฌ์„ฑ (โ†” page๋Š” ๋™์ผํ•œ ํฌ๊ธฐ ๋‹จ์œ„)

  • ์ž‘๊ฒŒ๋Š” ํ”„๋กœ๊ทธ๋žจ์„ ๊ตฌ์„ฑํ•˜๋Š” ํ•จ์ˆ˜ ํ•˜๋‚˜ํ•˜๋‚˜๋ฅผ ์„ธ๊ทธ๋จผํŠธ๋กœ ์ •์˜
  • ํฌ๊ฒŒ๋Š” ํ”„๋กœ๊ทธ๋žจ ์ „์ฒด๋ฅผ ํ•˜๋‚˜์˜ ์„ธ๊ทธ๋จผํŠธ๋กœ ์ •์˜ ๊ฐ€๋Šฅ
  • ์ผ๋ฐ˜์ ์œผ๋กœ๋Š” code, data, stack ๋ถ€๋ถ„์ด ํ•˜๋‚˜์”ฉ์˜ ์„ธ๊ทธ๋จผํŠธ๋กœ ์ •์˜๋จ
    • ํ”„๋กœ์„ธ์Šค๋Š” ๋ฉ”๋ชจ๋ฆฌ ๊ณต๊ฐ„์ด code, data, stack์œผ๋กœ ๋‚˜๋ˆ„์–ด์ ธ ์žˆ์Œ.

segment๋Š” ๋‹ค์Œ๊ณผ ๊ฐ™์€ logical unit ๋“ค์ž„. ๋‹ค์–‘ํ•œ ํฌ๊ธฐ์™€ ๋ฌถ๋Š” ๋ฐฉ๋ฒ•์ด ์žˆ์„ ์ˆ˜ ์žˆ์Œ.

  • main(), function, global variables, stack, symbol table, arrays

08-2. Segmentation Architecture

image

  • ๐Ÿ’› ๋…ผ๋ฆฌ์  ์ฃผ์†Œ๋Š” segment-number (2๋ฒˆ segment), offset (100๋ฒˆ์ง€) ์œผ๋กœ ๊ตฌ์„ฑ๋จ

  • ๐Ÿ’› Segment table

    • each table entry has:
      • limit: length of the segment (2๋ฒˆ segment์˜ size)
      • base: starting physical address of the segment (2๋ฒˆ segment์˜ physical ์‹œ์ž‘ ๋ฒˆ์ง€)
  • ๐Ÿ’› segment table base register (STBR)

    • ๋ฌผ๋ฆฌ์  ๋ฉ”๋ชจ๋ฆฌ์—์„œ์˜ segment table์˜ ์œ„์น˜
  • ๐Ÿ’› segment table length register (STLR)

    • ํ”„๋กœ๊ทธ๋žจ์ด ์‚ฌ์šฉํ•˜๋Š” segment์˜ ์ˆ˜

    • segment number s is legal if s < STLR.

      ์™œ ๋™๋“ฑ์ด ์•„๋‹ˆ๋ƒ? segment ๊ฐœ์ˆ˜๊ฐ€ 5๊ฐœ (STLR = 5)์ผ ๋•Œ, s๋Š” 0~4 ๊ฐ’์ด ๊ฐ€๋Šฅ


*** segment์˜ ๊ธธ์ด๊ฐ€ ๋™์ผํ•˜์ง€ ์•Š์œผ๋ฏ€๋กœ ๊ฐ€๋ณ€๋ถ„ํ•  ๋ฐฉ์‹์—์„œ์™€ ๋™์ผํ•œ ๋ฌธ์ œ์ ๋“ค์ด ๋ฐœ์ƒํ•œ๋‹ค.

  • ๐Ÿ’› Allocation
    • first-fit / best fit
    • ๋‹จ์ : external fragementation ๋ฐœ์ƒ

*** segment๋Š” ์˜๋ฏธ ๋‹จ์œ„์ด๊ธฐ ๋•Œ๋ฌธ์— ๊ณต์œ ์™€ ๋ณด์•ˆ์— ์žˆ์–ด paging๋ณด๋‹ค ํ›จ์”ฌ ํšจ๊ณผ์ ์ด๋‹ค.

  • ๐Ÿ’› Protection

    • ๊ฐ ์„ธ๊ทธ๋จผํŠธ ๋ณ„๋กœ protection bit๊ฐ€ ์žˆ์Œ -
    • Each entry:
      • Valid bit = 0 โ†’ illegal segment
      • Read/Write/Execution ๊ถŒํ•œ bit
  • ๐Ÿ’› Sharing

    • shared segment
    • same segment number

08-3. Segmentation with Paging

ํฐ ํ‹€์€ segment๋กœ ๋‚˜๋ˆด๋Š”๋ฐ, segment ์•ˆ์„ page๋กœ ๋‚˜๋ˆˆ ๋ฐฉ์‹์ด๋‹ค.

pure segmentation ๊ณผ์˜ ์ฐจ์ด์ 

  • segment-table entry๊ฐ€

    segment์˜ base address๋ฅผ ๊ฐ€์ง€๊ณ  ์žˆ๋Š” ๊ฒƒ์ด ์•„๋‹ˆ๋ผ

    segment๋ฅผ ๊ตฌ์„ฑํ•˜๋Š” page table์˜ base address๋ฅผ ๊ฐ€์ง€๊ณ  ์žˆ์Œ

์žฅ์ 

  • segment๊ฐ€ 4K ๋ฐฐ์ˆ˜๋งŒํผ ์›€์ง์ด๊ธฐ ๋•Œ๋ฌธ์— fragmentation์ด ์ค„์–ด๋“ฆ.

๋‹จ์ 

  • ๋ณต์žกํ•œ ๊ตฌ์กฐ(logic) โ†’ bug ๊ฐ€๋Šฅ์„ฑ์ด ์ฆ๊ฐ€ํ•˜๊ณ  ๋ฉ”๋ชจ๋ฆฌ ํฌ๊ธฐ์— ์˜ํ–ฅ
  • fragmentation์ด ๋ฐœ์ƒํ•˜๊ธด ํ•จ

image

segment number๊ณผ offset(d)๋ฅผ cpu๊ฐ€ ์š”์ฒญํ•˜๋ฉด

STBR์˜ ๊ฐ’์„ ์ด์šฉํ•˜์—ฌ segment table์— ์ ‘๊ทผํ•ด์„œ ์š”์ฒญํ•œ segment number์˜ ์ œํ•œ(๊ธธ์ด)๊ณผ page-table์˜ base ๊ฐ’์„ ์•Œ์•„๋‚ธ๋‹ค.

(segment table์— STBR + segment number๋กœ ์ ‘๊ทผํ–ˆ๋“ฏ์ด page-table์˜ base ๊ฐ’์„ ์•Œ์•„๋‚ธ ๊ฒƒ์ด๋‹ค. ๊ทธ๋ฆฌ๊ณ  ๊ฐ segment๋Š” ๋‹ค๋ฅธ page table์„ ์ฐธ์กฐํ•œ๋‹ค๋Š” ๊ฒƒ์„ ์•Œ ์ˆ˜ ์žˆ๋‹ค.)

offset์€ ํ•ด๋‹น segment์˜ limit๊ณผ ๋น„๊ตํ•œ ํ›„ legalํ•˜๋‹ค๋ฉด (segment์˜) offset๋ฅผ ๋‹ค์‹œ page number์™€ sub-offset ๋ฒˆํ˜ธ๋กœ ๋‚˜๋ˆˆ๋‹ค.

page table์˜ base ๊ฐ’์— page number์„ ๋”ํ•ด ์ฐพ๊ฒŒ ๋œ frame๊ณผ sub-offset ์œผ๋กœ ์›ํ•˜๋Š” ๋ฉ”๋ชจ๋ฆฌ์— ์ ‘๊ทผํ•  ์ˆ˜ ์žˆ๊ฒŒ ๋œ๋‹ค.

์ •๋ฆฌํ•˜์ž๋ฉด, segment number๋กœ segment table์„ ํ†ตํ•ด ์›ํ•˜๋Š” ํŽ˜์ด์ง€ ํ…Œ์ด๋ธ”์„ ์ฐพ๋Š”๋‹ค.

offset์œผ๋กœ ๋ช‡ ๋ฒˆ์งธ page(frame), ์–ด๋””์— ์กด์žฌํ•˜๋Š”์ง€ ์•Œ์•„๋‚ธ๋‹ค.