- Vivado 2018.2 or 2018.3
- License for CMAC Ultrascale + See instructions below
Without license you cannot synthesize and implement this IP-Core
This repository wraps the 100GbE CMAC core from Xilinx. There are two pieces:
- The actual CMAC core wrapper, which includes the LBUS to AXI4-Stream adapter.
From Vivado 2019.1 the CMAC includes AXI4-Stream as an option. But we have not tested such functionality yet.
- The cmac_sync that run the bring up sequence. Refer to Core Bring Up Sequence
Before generating the IPs make sure that CONFIG.GT_REF_CLK_FREQ match the frequency of the Si5328. By default the frequency is 156.25 MHz, but here we are using 161.1328125 MHz. For more details refer to Clock Generation
The process is fully automated, doing make is enough.
The Makefile is create in such a way that avoids regenerating the IPs if the source code does not change.
The IP-Cores include the constraint files that defines the location of each pin as well as timing-related constraints.
xlconstant_0 is set to 0. Bare in mind that even though cmac_sync and cmac_wrapper_0 work in different clock domain, the cmac_sync logic synchronize the input signals and the constraints declare the asynchronous path. So, there is not need to declare any other constraint.
Click Get License on UltraScale+ Integrated 100G Ethernet Subsystem and follow the steps.
BSD 3-Clause License
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Naudit HPCN, Spain (naudit.es)
HPCN Group, UAM Spain (hpcn-uam.es)
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