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openocd.cfg
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openocd.cfg
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#
# Freescale Kinetis K60 devices
#
#
# K60 devices support both JTAG and SWD transports.
#
interface ft2232
ft2232_device_desc "USB<=>JTAG&RS232 A"
ft2232_layout jtagkey
ft2232_vid_pid 0x1457 0x5118
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME k60
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x4ba00477
}
# 复位时的延迟, 单位 ns
#delays on reset lines
adapter_nsrst_delay 100
jtag_ntrst_delay 100
reset_config srst_only
# reset_config trst_and_srst trst_pulls_srst
# gdb_memory_map enable
# gdb_flash_program enable
set _TARGETNAME $_CHIPNAME.cpu
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
#
# Bank definition for the 'program flash' (instructions and/or data)
#
flash bank $_CHIPNAME.pflash kinetis 0x00000000 0x80000 0 0 $_TARGETNAME
# jtag speed
jtag_rclk 200
# 初始化PLL的函数, 初始化后 cclk =100Mhz
# Enable the PLL
proc enable_pll {} {
# enable IO clock
mww 0x40048038 0x00043F80
# Select FLL as a clock source for various peripherals
mww 0x40048004 0x00001000
# External Reference Enable
mww 0x40065000 0x80
# SIM_SOPT2: MCGCLKSEL=0
mww 0x40048004 0x00001000
# Very high frequency range selected for the crystal oscillator
mww 0x40064001 0x20
# Select ext oscillator, reference divider and clear IREFS to start ext osc
# mww 0x40064000 0x9c
# MCG_C4: DMX32=0,DRST_DRS=0
mww 0x40064003 0x00
# PLL External Reference Divider(2~4M)
# mww 0x40064004 0x01
# LOLIE=0,PLLS=0,CME=0,VDIV=0
mww 0x40064005 0x00
sleep 100
# LOLIE=0,PLLS=1,CME=0,VDIV=0
mww 0x40064005 0x40
sleep 100
# PLL External Reference Divider(2M)
# mww 0x40064004 0x03
# Prefetching is disabled
# mww 0x4001F000 0x00FF003F
# divider value(0,1,1,3)
mww 0x40048044 0x01130000
sleep 10
# LOLIE=0, PLLS=1, CME=0, VDIV=26
# mww 0x40064005 0x5A
# wait for PLL and LOCK status bit to set
sleep 100
# CLKS=0, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0
# mww 0x40064000 0x18
# Wait until output of the PLL is selected
sleep 100
}
$_TARGETNAME configure -event reset-init {
# arm core_state thumb
cortex_m3 reset_config srst
cortex_m3 maskisr auto
cortex_m3 vector_catch all
# 初始化时钟,并调高JTAG时钟
# enable_pll
jtag_rclk 200
}
$_TARGETNAME configure -event gdb-attach {
echo "reset...."
reset init
halt
}