02. Fpga accelerator for stereo vision using semi-global matching through dependency relaxation.md

FPGA accelerator for stereo vision using semi-global matching through dependency relaxation

This work deals with an FPGA based accelerator desing for the stereo-vision image processing algorithm. The developed accelerator is used to detect the depths of 2 images.

Poster Video

Faculty Name

Shashwat Shrivastava
Ziaul Choudhury
Shashwat Khandelwal
Suresh Purini

Research Area

Image processing, Hardware Accelerator, FPGA.

Type of Work

Hardware System.

Current State of work

Technology designed and implemented.

Potential Applications

Robotics, Self-driving car, computer vision.