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hat_i86.c
5115 lines (4551 loc) · 129 KB
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hat_i86.c
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/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* or http://www.opensolaris.org/os/licensing.
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
*/
/*
* Copyright (c) 2010, Intel Corporation.
* All rights reserved.
*/
/*
* Copyright 2011 Nexenta Systems, Inc. All rights reserved.
* Copyright 2018 Joyent, Inc. All rights reserved.
* Copyright (c) 2014, 2015 by Delphix. All rights reserved.
*/
/*
* VM - Hardware Address Translation management for i386 and amd64
*
* Implementation of the interfaces described in <common/vm/hat.h>
*
* Nearly all the details of how the hardware is managed should not be
* visible outside this layer except for misc. machine specific functions
* that work in conjunction with this code.
*
* Routines used only inside of i86pc/vm start with hati_ for HAT Internal.
*/
/*
* amd64 HAT Design
*
* ----------
* Background
* ----------
*
* On x86, the address space is shared between a user process and the kernel.
* This is different from SPARC. Conventionally, the kernel lives at the top of
* the address space and the user process gets to enjoy the rest of it. If you
* look at the image of the address map in uts/i86pc/os/startup.c, you'll get a
* rough sense of how the address space is laid out and used.
*
* Every unique address space is represented by an instance of a HAT structure
* called a 'hat_t'. In addition to a hat_t structure for each process, there is
* also one that is used for the kernel (kas.a_hat), and each CPU ultimately
* also has a HAT.
*
* Each HAT contains a pointer to its root page table. This root page table is
* what we call an L3 page table in illumos and Intel calls the PML4. It is the
* physical address of the L3 table that we place in the %cr3 register which the
* processor uses.
*
* Each of the many layers of the page table is represented by a structure
* called an htable_t. The htable_t manages a set of 512 8-byte entries. The
* number of entries in a given page table is constant across all different
* level page tables. Note, this is only true on amd64. This has not always been
* the case on x86.
*
* Each entry in a page table, generally referred to as a PTE, may refer to
* another page table or a memory location, depending on the level of the page
* table and the use of large pages. Importantly, the top-level L3 page table
* (PML4) only supports linking to further page tables. This is also true on
* systems which support a 5th level page table (which we do not currently
* support).
*
* Historically, on x86, when a process was running on CPU, the root of the page
* table was inserted into %cr3 on each CPU on which it was currently running.
* When processes would switch (by calling hat_switch()), then the value in %cr3
* on that CPU would change to that of the new HAT. While this behavior is still
* maintained in the xpv kernel, this is not what is done today.
*
* -------------------
* Per-CPU Page Tables
* -------------------
*
* Throughout the system the 64-bit kernel has a notion of what it calls a
* per-CPU page table or PCP. The notion of a per-CPU page table was originally
* introduced as part of the original work to support x86 PAE. On the 64-bit
* kernel, it was originally used for 32-bit processes running on the 64-bit
* kernel. The rationale behind this was that each 32-bit process could have all
* of its memory represented in a single L2 page table as each L2 page table
* entry represents 1 GbE of memory.
*
* Following on from this, the idea was that given that all of the L3 page table
* entries for 32-bit processes are basically going to be identical with the
* exception of the first entry in the page table, why not share those page
* table entries. This gave rise to the idea of a per-CPU page table.
*
* The way this works is that we have a member in the machcpu_t called the
* mcpu_hat_info. That structure contains two different 4k pages: one that
* represents the L3 page table and one that represents an L2 page table. When
* the CPU starts up, the L3 page table entries are copied in from the kernel's
* page table. The L3 kernel entries do not change throughout the lifetime of
* the kernel. The kernel portion of these L3 pages for each CPU have the same
* records, meaning that they point to the same L2 page tables and thus see a
* consistent view of the world.
*
* When a 32-bit process is loaded into this world, we copy the 32-bit process's
* four top-level page table entries into the CPU's L2 page table and then set
* the CPU's first L3 page table entry to point to the CPU's L2 page.
* Specifically, in hat_pcp_update(), we're copying from the process's
* HAT_COPIED_32 HAT into the page tables specific to this CPU.
*
* As part of the implementation of kernel page table isolation, this was also
* extended to 64-bit processes. When a 64-bit process runs, we'll copy their L3
* PTEs across into the current CPU's L3 page table. (As we can't do the
* first-L3-entry trick for 64-bit processes, ->hci_pcp_l2ptes is unused in this
* case.)
*
* The use of per-CPU page tables has a lot of implementation ramifications. A
* HAT that runs a user process will be flagged with the HAT_COPIED flag to
* indicate that it is using the per-CPU page table functionality. In tandem
* with the HAT, the top-level htable_t will be flagged with the HTABLE_COPIED
* flag. If the HAT represents a 32-bit process, then we will also set the
* HAT_COPIED_32 flag on that hat_t.
*
* These two flags work together. The top-level htable_t when using per-CPU page
* tables is 'virtual'. We never allocate a ptable for this htable_t (i.e.
* ht->ht_pfn is PFN_INVALID). Instead, when we need to modify a PTE in an
* HTABLE_COPIED ptable, x86pte_access_pagetable() will redirect any accesses to
* ht_hat->hat_copied_ptes.
*
* Of course, such a modification won't actually modify the HAT_PCP page tables
* that were copied from the HAT_COPIED htable. When we change the top level
* page table entries (L2 PTEs for a 32-bit process and L3 PTEs for a 64-bit
* process), we need to make sure to trigger hat_pcp_update() on all CPUs that
* are currently tied to this HAT (including the current CPU).
*
* To do this, PCP piggy-backs on TLB invalidation, specifically via the
* hat_tlb_inval() path from link_ptp() and unlink_ptp().
*
* (Importantly, in all such cases, when this is in operation, the top-level
* entry should not be able to refer to an actual page table entry that can be
* changed and consolidated into a large page. If large page consolidation is
* required here, then there will be much that needs to be reconsidered.)
*
* -----------------------------------------------
* Kernel Page Table Isolation and the Per-CPU HAT
* -----------------------------------------------
*
* All Intel CPUs that support speculative execution and paging are subject to a
* series of bugs that have been termed 'Meltdown'. These exploits allow a user
* process to read kernel memory through cache side channels and speculative
* execution. To mitigate this on vulnerable CPUs, we need to use a technique
* called kernel page table isolation. What this requires is that we have two
* different page table roots. When executing in kernel mode, we will use a %cr3
* value that has both the user and kernel pages. However when executing in user
* mode, we will need to have a %cr3 that has all of the user pages; however,
* only a subset of the kernel pages required to operate.
*
* These kernel pages that we need mapped are:
*
* o Kernel Text that allows us to switch between the cr3 values.
* o The current global descriptor table (GDT)
* o The current interrupt descriptor table (IDT)
* o The current task switching state (TSS)
* o The current local descriptor table (LDT)
* o Stacks and scratch space used by the interrupt handlers
*
* For more information on the stack switching techniques, construction of the
* trampolines, and more, please see i86pc/ml/kpti_trampolines.s. The most
* important part of these mappings are the following two constraints:
*
* o The mappings are all per-CPU (except for read-only text)
* o The mappings are static. They are all established before the CPU is
* started (with the exception of the boot CPU).
*
* To facilitate the kernel page table isolation we employ our per-CPU
* page tables discussed in the previous section and add the notion of a per-CPU
* HAT. Fundamentally we have a second page table root. There is both a kernel
* page table (hci_pcp_l3ptes), and a user L3 page table (hci_user_l3ptes).
* Both will have the user page table entries copied into them, the same way
* that we discussed in the section 'Per-CPU Page Tables'.
*
* The complex part of this is how do we construct the set of kernel mappings
* that should be present when running with the user page table. To answer that,
* we add the notion of a per-CPU HAT. This HAT functions like a normal HAT,
* except that it's not really associated with an address space the same way
* that other HATs are.
*
* This HAT lives off of the 'struct hat_cpu_info' which is a member of the
* machcpu in the member hci_user_hat. We use this per-CPU HAT to create the set
* of kernel mappings that should be present on this CPU. The kernel mappings
* are added to the per-CPU HAT through the function hati_cpu_punchin(). Once a
* mapping has been punched in, it may not be punched out. The reason that we
* opt to leverage a HAT structure is that it knows how to allocate and manage
* all of the lower level page tables as required.
*
* Because all of the mappings are present at the beginning of time for this CPU
* and none of the mappings are in the kernel pageable segment, we don't have to
* worry about faulting on these HAT structures and thus the notion of the
* current HAT that we're using is always the appropriate HAT for the process
* (usually a user HAT or the kernel's HAT).
*
* A further constraint we place on the system with these per-CPU HATs is that
* they are not subject to htable_steal(). Because each CPU will have a rather
* fixed number of page tables, the same way that we don't steal from the
* kernel's HAT, it was determined that we should not steal from this HAT due to
* the complications involved and somewhat criminal nature of htable_steal().
*
* The per-CPU HAT is initialized in hat_pcp_setup() which is called as part of
* onlining the CPU, but before the CPU is actually started. The per-CPU HAT is
* removed in hat_pcp_teardown() which is called when a CPU is being offlined to
* be removed from the system (which is different from what psradm usually
* does).
*
* Finally, once the CPU has been onlined, the set of mappings in the per-CPU
* HAT must not change. The HAT related functions that we call are not meant to
* be called when we're switching between processes. For example, it is quite
* possible that if they were, they would try to grab an htable mutex which
* another thread might have. One needs to treat hat_switch() as though they
* were above LOCK_LEVEL and therefore _must not_ block under any circumstance.
*/
#include <sys/machparam.h>
#include <sys/machsystm.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <sys/systm.h>
#include <sys/cpuvar.h>
#include <sys/thread.h>
#include <sys/proc.h>
#include <sys/cpu.h>
#include <sys/kmem.h>
#include <sys/disp.h>
#include <sys/shm.h>
#include <sys/sysmacros.h>
#include <sys/machparam.h>
#include <sys/vmem.h>
#include <sys/vmsystm.h>
#include <sys/promif.h>
#include <sys/var.h>
#include <sys/x86_archext.h>
#include <sys/atomic.h>
#include <sys/bitmap.h>
#include <sys/controlregs.h>
#include <sys/bootconf.h>
#include <sys/bootsvcs.h>
#include <sys/bootinfo.h>
#include <sys/archsystm.h>
#include <vm/seg_kmem.h>
#include <vm/hat_i86.h>
#include <vm/as.h>
#include <vm/seg.h>
#include <vm/page.h>
#include <vm/seg_kp.h>
#include <vm/seg_kpm.h>
#include <vm/vm_dep.h>
#ifdef __xpv
#include <sys/hypervisor.h>
#endif
#include <vm/kboot_mmu.h>
#include <vm/seg_spt.h>
#include <sys/cmn_err.h>
/*
* Basic parameters for hat operation.
*/
struct hat_mmu_info mmu;
/*
* The page that is the kernel's top level pagetable.
*
* For 32 bit PAE support on i86pc, the kernel hat will use the 1st 4 entries
* on this 4K page for its top level page table. The remaining groups of
* 4 entries are used for per processor copies of user PCP pagetables for
* running threads. See hat_switch() and reload_pae32() for details.
*
* pcp_page[0..3] - level==2 PTEs for kernel HAT
* pcp_page[4..7] - level==2 PTEs for user thread on cpu 0
* pcp_page[8..11] - level==2 PTE for user thread on cpu 1
* etc...
*
* On the 64-bit kernel, this is the normal root of the page table and there is
* nothing special about it when used for other CPUs.
*/
static x86pte_t *pcp_page;
/*
* forward declaration of internal utility routines
*/
static x86pte_t hati_update_pte(htable_t *ht, uint_t entry, x86pte_t expected,
x86pte_t new);
/*
* The kernel address space exists in all non-HAT_COPIED HATs. To implement this
* the kernel reserves a fixed number of entries in the topmost level(s) of page
* tables. The values are setup during startup and then copied to every user hat
* created by hat_alloc(). This means that kernelbase must be:
*
* 4Meg aligned for 32 bit kernels
* 512Gig aligned for x86_64 64 bit kernel
*
* The hat_kernel_range_ts describe what needs to be copied from kernel hat
* to each user hat.
*/
typedef struct hat_kernel_range {
level_t hkr_level;
uintptr_t hkr_start_va;
uintptr_t hkr_end_va; /* zero means to end of memory */
} hat_kernel_range_t;
#define NUM_KERNEL_RANGE 2
static hat_kernel_range_t kernel_ranges[NUM_KERNEL_RANGE];
static int num_kernel_ranges;
uint_t use_boot_reserve = 1; /* cleared after early boot process */
uint_t can_steal_post_boot = 0; /* set late in boot to enable stealing */
/*
* enable_1gpg: controls 1g page support for user applications.
* By default, 1g pages are exported to user applications. enable_1gpg can
* be set to 0 to not export.
*/
int enable_1gpg = 1;
/*
* AMD shanghai processors provide better management of 1gb ptes in its tlb.
* By default, 1g page support will be disabled for pre-shanghai AMD
* processors that don't have optimal tlb support for the 1g page size.
* chk_optimal_1gtlb can be set to 0 to force 1g page support on sub-optimal
* processors.
*/
int chk_optimal_1gtlb = 1;
#ifdef DEBUG
uint_t map1gcnt;
#endif
/*
* A cpuset for all cpus. This is used for kernel address cross calls, since
* the kernel addresses apply to all cpus.
*/
cpuset_t khat_cpuset;
/*
* management stuff for hat structures
*/
kmutex_t hat_list_lock;
kcondvar_t hat_list_cv;
kmem_cache_t *hat_cache;
kmem_cache_t *hat_hash_cache;
kmem_cache_t *hat32_hash_cache;
/*
* Simple statistics
*/
struct hatstats hatstat;
/*
* Some earlier hypervisor versions do not emulate cmpxchg of PTEs
* correctly. For such hypervisors we must set PT_USER for kernel
* entries ourselves (normally the emulation would set PT_USER for
* kernel entries and PT_USER|PT_GLOBAL for user entries). pt_kern is
* thus set appropriately. Note that dboot/kbm is OK, as only the full
* HAT uses cmpxchg() and the other paths (hypercall etc.) were never
* incorrect.
*/
int pt_kern;
#ifndef __xpv
extern pfn_t memseg_get_start(struct memseg *);
#endif
#define PP_GETRM(pp, rmmask) (pp->p_nrm & rmmask)
#define PP_ISMOD(pp) PP_GETRM(pp, P_MOD)
#define PP_ISREF(pp) PP_GETRM(pp, P_REF)
#define PP_ISRO(pp) PP_GETRM(pp, P_RO)
#define PP_SETRM(pp, rm) atomic_orb(&(pp->p_nrm), rm)
#define PP_SETMOD(pp) PP_SETRM(pp, P_MOD)
#define PP_SETREF(pp) PP_SETRM(pp, P_REF)
#define PP_SETRO(pp) PP_SETRM(pp, P_RO)
#define PP_CLRRM(pp, rm) atomic_andb(&(pp->p_nrm), ~(rm))
#define PP_CLRMOD(pp) PP_CLRRM(pp, P_MOD)
#define PP_CLRREF(pp) PP_CLRRM(pp, P_REF)
#define PP_CLRRO(pp) PP_CLRRM(pp, P_RO)
#define PP_CLRALL(pp) PP_CLRRM(pp, P_MOD | P_REF | P_RO)
/*
* kmem cache constructor for struct hat
*/
/*ARGSUSED*/
static int
hati_constructor(void *buf, void *handle, int kmflags)
{
hat_t *hat = buf;
mutex_init(&hat->hat_mutex, NULL, MUTEX_DEFAULT, NULL);
bzero(hat->hat_pages_mapped,
sizeof (pgcnt_t) * (mmu.max_page_level + 1));
hat->hat_ism_pgcnt = 0;
hat->hat_stats = 0;
hat->hat_flags = 0;
CPUSET_ZERO(hat->hat_cpus);
hat->hat_htable = NULL;
hat->hat_ht_hash = NULL;
return (0);
}
/*
* Put it at the start of the global list of all hats (used by stealing)
*
* kas.a_hat is not in the list but is instead used to find the
* first and last items in the list.
*
* - kas.a_hat->hat_next points to the start of the user hats.
* The list ends where hat->hat_next == NULL
*
* - kas.a_hat->hat_prev points to the last of the user hats.
* The list begins where hat->hat_prev == NULL
*/
static void
hat_list_append(hat_t *hat)
{
mutex_enter(&hat_list_lock);
hat->hat_prev = NULL;
hat->hat_next = kas.a_hat->hat_next;
if (hat->hat_next)
hat->hat_next->hat_prev = hat;
else
kas.a_hat->hat_prev = hat;
kas.a_hat->hat_next = hat;
mutex_exit(&hat_list_lock);
}
/*
* Allocate a hat structure for as. We also create the top level
* htable and initialize it to contain the kernel hat entries.
*/
hat_t *
hat_alloc(struct as *as)
{
hat_t *hat;
htable_t *ht; /* top level htable */
uint_t use_copied;
uint_t r;
hat_kernel_range_t *rp;
uintptr_t va;
uintptr_t eva;
uint_t start;
uint_t cnt;
htable_t *src;
boolean_t use_hat32_cache;
/*
* Once we start creating user process HATs we can enable
* the htable_steal() code.
*/
if (can_steal_post_boot == 0)
can_steal_post_boot = 1;
ASSERT(AS_WRITE_HELD(as));
hat = kmem_cache_alloc(hat_cache, KM_SLEEP);
hat->hat_as = as;
mutex_init(&hat->hat_mutex, NULL, MUTEX_DEFAULT, NULL);
ASSERT(hat->hat_flags == 0);
#if defined(__xpv)
/*
* No PCP stuff on the hypervisor due to the 64-bit split top level
* page tables. On 32-bit it's not needed as the hypervisor takes
* care of copying the top level PTEs to a below 4Gig page.
*/
use_copied = 0;
use_hat32_cache = B_FALSE;
hat->hat_max_level = mmu.max_level;
hat->hat_num_copied = 0;
hat->hat_flags = 0;
#else /* __xpv */
/*
* All processes use HAT_COPIED on the 64-bit kernel if KPTI is
* turned on.
*/
if (ttoproc(curthread)->p_model == DATAMODEL_ILP32) {
use_copied = 1;
hat->hat_max_level = mmu.max_level32;
hat->hat_num_copied = mmu.num_copied_ents32;
use_hat32_cache = B_TRUE;
hat->hat_flags |= HAT_COPIED_32;
HATSTAT_INC(hs_hat_copied32);
} else if (kpti_enable == 1) {
use_copied = 1;
hat->hat_max_level = mmu.max_level;
hat->hat_num_copied = mmu.num_copied_ents;
use_hat32_cache = B_FALSE;
HATSTAT_INC(hs_hat_copied64);
} else {
use_copied = 0;
use_hat32_cache = B_FALSE;
hat->hat_max_level = mmu.max_level;
hat->hat_num_copied = 0;
hat->hat_flags = 0;
HATSTAT_INC(hs_hat_normal64);
}
#endif /* __xpv */
if (use_copied) {
hat->hat_flags |= HAT_COPIED;
bzero(hat->hat_copied_ptes, sizeof (hat->hat_copied_ptes));
}
/*
* Allocate the htable hash. For 32-bit PCP processes we use the
* hat32_hash_cache. However, for 64-bit PCP processes we do not as the
* number of entries that they have to handle is closer to
* hat_hash_cache in count (though there will be more wastage when we
* have more DRAM in the system and thus push down the user address
* range).
*/
if (use_hat32_cache) {
hat->hat_num_hash = mmu.hat32_hash_cnt;
hat->hat_ht_hash = kmem_cache_alloc(hat32_hash_cache, KM_SLEEP);
} else {
hat->hat_num_hash = mmu.hash_cnt;
hat->hat_ht_hash = kmem_cache_alloc(hat_hash_cache, KM_SLEEP);
}
bzero(hat->hat_ht_hash, hat->hat_num_hash * sizeof (htable_t *));
/*
* Initialize Kernel HAT entries at the top of the top level page
* tables for the new hat.
*/
hat->hat_htable = NULL;
hat->hat_ht_cached = NULL;
XPV_DISALLOW_MIGRATE();
ht = htable_create(hat, (uintptr_t)0, TOP_LEVEL(hat), NULL);
hat->hat_htable = ht;
#if defined(__amd64)
if (hat->hat_flags & HAT_COPIED)
goto init_done;
#endif
for (r = 0; r < num_kernel_ranges; ++r) {
rp = &kernel_ranges[r];
for (va = rp->hkr_start_va; va != rp->hkr_end_va;
va += cnt * LEVEL_SIZE(rp->hkr_level)) {
if (rp->hkr_level == TOP_LEVEL(hat))
ht = hat->hat_htable;
else
ht = htable_create(hat, va, rp->hkr_level,
NULL);
start = htable_va2entry(va, ht);
cnt = HTABLE_NUM_PTES(ht) - start;
eva = va +
((uintptr_t)cnt << LEVEL_SHIFT(rp->hkr_level));
if (rp->hkr_end_va != 0 &&
(eva > rp->hkr_end_va || eva == 0))
cnt = htable_va2entry(rp->hkr_end_va, ht) -
start;
#if defined(__i386) && !defined(__xpv)
if (ht->ht_flags & HTABLE_COPIED) {
bcopy(&pcp_page[start],
&hat->hat_copied_ptes[start],
cnt * sizeof (x86pte_t));
continue;
}
#endif
src = htable_lookup(kas.a_hat, va, rp->hkr_level);
ASSERT(src != NULL);
x86pte_copy(src, ht, start, cnt);
htable_release(src);
}
}
init_done:
#if defined(__xpv)
/*
* Pin top level page tables after initializing them
*/
xen_pin(hat->hat_htable->ht_pfn, mmu.max_level);
#if defined(__amd64)
xen_pin(hat->hat_user_ptable, mmu.max_level);
#endif
#endif
XPV_ALLOW_MIGRATE();
hat_list_append(hat);
return (hat);
}
#if !defined(__xpv)
/*
* Cons up a HAT for a CPU. This represents the user mappings. This will have
* various kernel pages punched into it manually. Importantly, this hat is
* ineligible for stealing. We really don't want to deal with this ever
* faulting and figuring out that this is happening, much like we don't with
* kas.
*/
static hat_t *
hat_cpu_alloc(cpu_t *cpu)
{
hat_t *hat;
htable_t *ht;
hat = kmem_cache_alloc(hat_cache, KM_SLEEP);
hat->hat_as = NULL;
mutex_init(&hat->hat_mutex, NULL, MUTEX_DEFAULT, NULL);
hat->hat_max_level = mmu.max_level;
hat->hat_num_copied = 0;
hat->hat_flags = HAT_PCP;
hat->hat_num_hash = mmu.hash_cnt;
hat->hat_ht_hash = kmem_cache_alloc(hat_hash_cache, KM_SLEEP);
bzero(hat->hat_ht_hash, hat->hat_num_hash * sizeof (htable_t *));
hat->hat_next = hat->hat_prev = NULL;
/*
* Because this HAT will only ever be used by the current CPU, we'll go
* ahead and set the CPUSET up to only point to the CPU in question.
*/
CPUSET_ADD(hat->hat_cpus, cpu->cpu_id);
hat->hat_htable = NULL;
hat->hat_ht_cached = NULL;
ht = htable_create(hat, (uintptr_t)0, TOP_LEVEL(hat), NULL);
hat->hat_htable = ht;
hat_list_append(hat);
return (hat);
}
#endif /* !__xpv */
/*
* process has finished executing but as has not been cleaned up yet.
*/
/*ARGSUSED*/
void
hat_free_start(hat_t *hat)
{
ASSERT(AS_WRITE_HELD(hat->hat_as));
/*
* If the hat is currently a stealing victim, wait for the stealing
* to finish. Once we mark it as HAT_FREEING, htable_steal()
* won't look at its pagetables anymore.
*/
mutex_enter(&hat_list_lock);
while (hat->hat_flags & HAT_VICTIM)
cv_wait(&hat_list_cv, &hat_list_lock);
hat->hat_flags |= HAT_FREEING;
mutex_exit(&hat_list_lock);
}
/*
* An address space is being destroyed, so we destroy the associated hat.
*/
void
hat_free_end(hat_t *hat)
{
kmem_cache_t *cache;
ASSERT(hat->hat_flags & HAT_FREEING);
/*
* must not be running on the given hat
*/
ASSERT(CPU->cpu_current_hat != hat);
/*
* Remove it from the list of HATs
*/
mutex_enter(&hat_list_lock);
if (hat->hat_prev)
hat->hat_prev->hat_next = hat->hat_next;
else
kas.a_hat->hat_next = hat->hat_next;
if (hat->hat_next)
hat->hat_next->hat_prev = hat->hat_prev;
else
kas.a_hat->hat_prev = hat->hat_prev;
mutex_exit(&hat_list_lock);
hat->hat_next = hat->hat_prev = NULL;
#if defined(__xpv)
/*
* On the hypervisor, unpin top level page table(s)
*/
VERIFY3U(hat->hat_flags & HAT_PCP, ==, 0);
xen_unpin(hat->hat_htable->ht_pfn);
#if defined(__amd64)
xen_unpin(hat->hat_user_ptable);
#endif
#endif
/*
* Make a pass through the htables freeing them all up.
*/
htable_purge_hat(hat);
/*
* Decide which kmem cache the hash table came from, then free it.
*/
if (hat->hat_flags & HAT_COPIED) {
#if defined(__amd64)
if (hat->hat_flags & HAT_COPIED_32) {
cache = hat32_hash_cache;
} else {
cache = hat_hash_cache;
}
#else
cache = hat32_hash_cache;
#endif
} else {
cache = hat_hash_cache;
}
kmem_cache_free(cache, hat->hat_ht_hash);
hat->hat_ht_hash = NULL;
hat->hat_flags = 0;
hat->hat_max_level = 0;
hat->hat_num_copied = 0;
kmem_cache_free(hat_cache, hat);
}
/*
* round kernelbase down to a supported value to use for _userlimit
*
* userlimit must be aligned down to an entry in the top level htable.
* The one exception is for 32 bit HAT's running PAE.
*/
uintptr_t
hat_kernelbase(uintptr_t va)
{
#if defined(__i386)
va &= LEVEL_MASK(1);
#endif
if (IN_VA_HOLE(va))
panic("_userlimit %p will fall in VA hole\n", (void *)va);
return (va);
}
/*
*
*/
static void
set_max_page_level()
{
level_t lvl;
if (!kbm_largepage_support) {
lvl = 0;
} else {
if (is_x86_feature(x86_featureset, X86FSET_1GPG)) {
lvl = 2;
if (chk_optimal_1gtlb &&
cpuid_opteron_erratum(CPU, 6671130)) {
lvl = 1;
}
if (plat_mnode_xcheck(LEVEL_SIZE(2) >>
LEVEL_SHIFT(0))) {
lvl = 1;
}
} else {
lvl = 1;
}
}
mmu.max_page_level = lvl;
if ((lvl == 2) && (enable_1gpg == 0))
mmu.umax_page_level = 1;
else
mmu.umax_page_level = lvl;
}
/*
* Determine the number of slots that are in used in the top-most level page
* table for user memory. This is based on _userlimit. In effect this is similar
* to htable_va2entry, but without the convenience of having an htable.
*/
void
mmu_calc_user_slots(void)
{
uint_t ent, nptes;
uintptr_t shift;
nptes = mmu.top_level_count;
shift = _userlimit >> mmu.level_shift[mmu.max_level];
ent = shift & (nptes - 1);
/*
* Ent tells us the slot that the page for _userlimit would fit in. We
* need to add one to this to cover the total number of entries.
*/
mmu.top_level_uslots = ent + 1;
/*
* When running 32-bit compatability processes on a 64-bit kernel, we
* will only need to use one slot.
*/
mmu.top_level_uslots32 = 1;
/*
* Record the number of PCP page table entries that we'll need to copy
* around. For 64-bit processes this is the number of user slots. For
* 32-bit proceses, this is 4 1 GiB pages.
*/
mmu.num_copied_ents = mmu.top_level_uslots;
mmu.num_copied_ents32 = 4;
}
/*
* Initialize hat data structures based on processor MMU information.
*/
void
mmu_init(void)
{
uint_t max_htables;
uint_t pa_bits;
uint_t va_bits;
int i;
/*
* If CPU enabled the page table global bit, use it for the kernel
* This is bit 7 in CR4 (PGE - Page Global Enable).
*/
if (is_x86_feature(x86_featureset, X86FSET_PGE) &&
(getcr4() & CR4_PGE) != 0)
mmu.pt_global = PT_GLOBAL;
#if !defined(__xpv)
/*
* The 64-bit x86 kernel has split user/kernel page tables. As such we
* cannot have the global bit set. The simplest way for us to deal with
* this is to just say that pt_global is zero, so the global bit isn't
* present.
*/
if (kpti_enable == 1)
mmu.pt_global = 0;
#endif
/*
* Detect NX and PAE usage.
*/
mmu.pae_hat = kbm_pae_support;
if (kbm_nx_support)
mmu.pt_nx = PT_NX;
else
mmu.pt_nx = 0;
/*
* Use CPU info to set various MMU parameters
*/
cpuid_get_addrsize(CPU, &pa_bits, &va_bits);
if (va_bits < sizeof (void *) * NBBY) {
mmu.hole_start = (1ul << (va_bits - 1));
mmu.hole_end = 0ul - mmu.hole_start - 1;
} else {
mmu.hole_end = 0;
mmu.hole_start = mmu.hole_end - 1;
}
#if defined(OPTERON_ERRATUM_121)
/*
* If erratum 121 has already been detected at this time, hole_start
* contains the value to be subtracted from mmu.hole_start.
*/
ASSERT(hole_start == 0 || opteron_erratum_121 != 0);
hole_start = mmu.hole_start - hole_start;
#else
hole_start = mmu.hole_start;
#endif
hole_end = mmu.hole_end;
mmu.highest_pfn = mmu_btop((1ull << pa_bits) - 1);
if (mmu.pae_hat == 0 && pa_bits > 32)
mmu.highest_pfn = PFN_4G - 1;
if (mmu.pae_hat) {
mmu.pte_size = 8; /* 8 byte PTEs */
mmu.pte_size_shift = 3;
} else {
mmu.pte_size = 4; /* 4 byte PTEs */
mmu.pte_size_shift = 2;
}
if (mmu.pae_hat && !is_x86_feature(x86_featureset, X86FSET_PAE))
panic("Processor does not support PAE");
if (!is_x86_feature(x86_featureset, X86FSET_CX8))
panic("Processor does not support cmpxchg8b instruction");
#if defined(__amd64)
mmu.num_level = 4;
mmu.max_level = 3;
mmu.ptes_per_table = 512;
mmu.top_level_count = 512;
/*
* 32-bit processes only use 1 GB ptes.
*/
mmu.max_level32 = 2;
mmu.level_shift[0] = 12;
mmu.level_shift[1] = 21;
mmu.level_shift[2] = 30;
mmu.level_shift[3] = 39;
#elif defined(__i386)
if (mmu.pae_hat) {
mmu.num_level = 3;
mmu.max_level = 2;
mmu.ptes_per_table = 512;
mmu.top_level_count = 4;
mmu.level_shift[0] = 12;
mmu.level_shift[1] = 21;
mmu.level_shift[2] = 30;
} else {
mmu.num_level = 2;
mmu.max_level = 1;
mmu.ptes_per_table = 1024;
mmu.top_level_count = 1024;
mmu.level_shift[0] = 12;
mmu.level_shift[1] = 22;
}
#endif /* __i386 */
for (i = 0; i < mmu.num_level; ++i) {
mmu.level_size[i] = 1UL << mmu.level_shift[i];
mmu.level_offset[i] = mmu.level_size[i] - 1;
mmu.level_mask[i] = ~mmu.level_offset[i];
}
set_max_page_level();
mmu_calc_user_slots();
mmu_page_sizes = mmu.max_page_level + 1;
mmu_exported_page_sizes = mmu.umax_page_level + 1;
/* restrict legacy applications from using pagesizes 1g and above */
mmu_legacy_page_sizes =
(mmu_exported_page_sizes > 2) ? 2 : mmu_exported_page_sizes;
for (i = 0; i <= mmu.max_page_level; ++i) {
mmu.pte_bits[i] = PT_VALID | pt_kern;
if (i > 0)
mmu.pte_bits[i] |= PT_PAGESIZE;
}
/*
* NOTE Legacy 32 bit PAE mode only has the P_VALID bit at top level.
*/
for (i = 1; i < mmu.num_level; ++i)
mmu.ptp_bits[i] = PT_PTPBITS;
#if defined(__i386)
mmu.ptp_bits[2] = PT_VALID;
#endif
/*
* Compute how many hash table entries to have per process for htables.
* We start with 1 page's worth of entries.
*
* If physical memory is small, reduce the amount need to cover it.
*/
max_htables = physmax / mmu.ptes_per_table;
mmu.hash_cnt = MMU_PAGESIZE / sizeof (htable_t *);
while (mmu.hash_cnt > 16 && mmu.hash_cnt >= max_htables)
mmu.hash_cnt >>= 1;
mmu.hat32_hash_cnt = mmu.hash_cnt;
#if defined(__amd64)
/*
* If running in 64 bits and physical memory is large,
* increase the size of the cache to cover all of memory for