forked from torvalds/linux
/
dpaa2-eth.c
5062 lines (4245 loc) · 131 KB
/
dpaa2-eth.c
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/* Copyright 2014-2016 Freescale Semiconductor Inc.
* Copyright 2016-2022 NXP
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/etherdevice.h>
#include <linux/of_net.h>
#include <linux/interrupt.h>
#include <linux/msi.h>
#include <linux/kthread.h>
#include <linux/iommu.h>
#include <linux/fsl/mc.h>
#include <linux/bpf.h>
#include <linux/bpf_trace.h>
#include <linux/fsl/ptp_qoriq.h>
#include <linux/ptp_classify.h>
#include <net/pkt_cls.h>
#include <net/sock.h>
#include <net/tso.h>
#include <net/xdp_sock_drv.h>
#include "dpaa2-eth.h"
/* CREATE_TRACE_POINTS only needs to be defined once. Other dpa files
* using trace events only need to #include <trace/events/sched.h>
*/
#define CREATE_TRACE_POINTS
#include "dpaa2-eth-trace.h"
MODULE_LICENSE("Dual BSD/GPL");
MODULE_AUTHOR("Freescale Semiconductor, Inc");
MODULE_DESCRIPTION("Freescale DPAA2 Ethernet Driver");
struct ptp_qoriq *dpaa2_ptp;
EXPORT_SYMBOL(dpaa2_ptp);
static void dpaa2_eth_detect_features(struct dpaa2_eth_priv *priv)
{
priv->features = 0;
if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_PTP_ONESTEP_VER_MAJOR,
DPNI_PTP_ONESTEP_VER_MINOR) >= 0)
priv->features |= DPAA2_ETH_FEATURE_ONESTEP_CFG_DIRECT;
}
static void dpaa2_update_ptp_onestep_indirect(struct dpaa2_eth_priv *priv,
u32 offset, u8 udp)
{
struct dpni_single_step_cfg cfg;
cfg.en = 1;
cfg.ch_update = udp;
cfg.offset = offset;
cfg.peer_delay = 0;
if (dpni_set_single_step_cfg(priv->mc_io, 0, priv->mc_token, &cfg))
WARN_ONCE(1, "Failed to set single step register");
}
static void dpaa2_update_ptp_onestep_direct(struct dpaa2_eth_priv *priv,
u32 offset, u8 udp)
{
u32 val = 0;
val = DPAA2_PTP_SINGLE_STEP_ENABLE |
DPAA2_PTP_SINGLE_CORRECTION_OFF(offset);
if (udp)
val |= DPAA2_PTP_SINGLE_STEP_CH;
if (priv->onestep_reg_base)
writel(val, priv->onestep_reg_base);
}
static void dpaa2_ptp_onestep_reg_update_method(struct dpaa2_eth_priv *priv)
{
struct device *dev = priv->net_dev->dev.parent;
struct dpni_single_step_cfg ptp_cfg;
priv->dpaa2_set_onestep_params_cb = dpaa2_update_ptp_onestep_indirect;
if (!(priv->features & DPAA2_ETH_FEATURE_ONESTEP_CFG_DIRECT))
return;
if (dpni_get_single_step_cfg(priv->mc_io, 0,
priv->mc_token, &ptp_cfg)) {
dev_err(dev, "dpni_get_single_step_cfg cannot retrieve onestep reg, falling back to indirect update\n");
return;
}
if (!ptp_cfg.ptp_onestep_reg_base) {
dev_err(dev, "1588 onestep reg not available, falling back to indirect update\n");
return;
}
priv->onestep_reg_base = ioremap(ptp_cfg.ptp_onestep_reg_base,
sizeof(u32));
if (!priv->onestep_reg_base) {
dev_err(dev, "1588 onestep reg cannot be mapped, falling back to indirect update\n");
return;
}
priv->dpaa2_set_onestep_params_cb = dpaa2_update_ptp_onestep_direct;
}
void *dpaa2_iova_to_virt(struct iommu_domain *domain,
dma_addr_t iova_addr)
{
phys_addr_t phys_addr;
phys_addr = domain ? iommu_iova_to_phys(domain, iova_addr) : iova_addr;
return phys_to_virt(phys_addr);
}
static void dpaa2_eth_validate_rx_csum(struct dpaa2_eth_priv *priv,
u32 fd_status,
struct sk_buff *skb)
{
skb_checksum_none_assert(skb);
/* HW checksum validation is disabled, nothing to do here */
if (!(priv->net_dev->features & NETIF_F_RXCSUM))
return;
/* Read checksum validation bits */
if (!((fd_status & DPAA2_FAS_L3CV) &&
(fd_status & DPAA2_FAS_L4CV)))
return;
/* Inform the stack there's no need to compute L3/L4 csum anymore */
skb->ip_summed = CHECKSUM_UNNECESSARY;
}
/* Free a received FD.
* Not to be used for Tx conf FDs or on any other paths.
*/
static void dpaa2_eth_free_rx_fd(struct dpaa2_eth_priv *priv,
const struct dpaa2_fd *fd,
void *vaddr)
{
struct device *dev = priv->net_dev->dev.parent;
dma_addr_t addr = dpaa2_fd_get_addr(fd);
u8 fd_format = dpaa2_fd_get_format(fd);
struct dpaa2_sg_entry *sgt;
void *sg_vaddr;
int i;
/* If single buffer frame, just free the data buffer */
if (fd_format == dpaa2_fd_single)
goto free_buf;
else if (fd_format != dpaa2_fd_sg)
/* We don't support any other format */
return;
/* For S/G frames, we first need to free all SG entries
* except the first one, which was taken care of already
*/
sgt = vaddr + dpaa2_fd_get_offset(fd);
for (i = 1; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) {
addr = dpaa2_sg_get_addr(&sgt[i]);
sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
dma_unmap_page(dev, addr, priv->rx_buf_size,
DMA_BIDIRECTIONAL);
free_pages((unsigned long)sg_vaddr, 0);
if (dpaa2_sg_is_final(&sgt[i]))
break;
}
free_buf:
free_pages((unsigned long)vaddr, 0);
}
/* Build a linear skb based on a single-buffer frame descriptor */
static struct sk_buff *dpaa2_eth_build_linear_skb(struct dpaa2_eth_channel *ch,
const struct dpaa2_fd *fd,
void *fd_vaddr)
{
struct sk_buff *skb = NULL;
u16 fd_offset = dpaa2_fd_get_offset(fd);
u32 fd_length = dpaa2_fd_get_len(fd);
ch->buf_count--;
skb = build_skb(fd_vaddr, DPAA2_ETH_RX_BUF_RAW_SIZE);
if (unlikely(!skb))
return NULL;
skb_reserve(skb, fd_offset);
skb_put(skb, fd_length);
return skb;
}
/* Build a non linear (fragmented) skb based on a S/G table */
static struct sk_buff *dpaa2_eth_build_frag_skb(struct dpaa2_eth_priv *priv,
struct dpaa2_eth_channel *ch,
struct dpaa2_sg_entry *sgt)
{
struct sk_buff *skb = NULL;
struct device *dev = priv->net_dev->dev.parent;
void *sg_vaddr;
dma_addr_t sg_addr;
u16 sg_offset;
u32 sg_length;
struct page *page, *head_page;
int page_offset;
int i;
for (i = 0; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) {
struct dpaa2_sg_entry *sge = &sgt[i];
/* NOTE: We only support SG entries in dpaa2_sg_single format,
* but this is the only format we may receive from HW anyway
*/
/* Get the address and length from the S/G entry */
sg_addr = dpaa2_sg_get_addr(sge);
sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, sg_addr);
dma_unmap_page(dev, sg_addr, priv->rx_buf_size,
DMA_BIDIRECTIONAL);
sg_length = dpaa2_sg_get_len(sge);
if (i == 0) {
/* We build the skb around the first data buffer */
skb = build_skb(sg_vaddr, DPAA2_ETH_RX_BUF_RAW_SIZE);
if (unlikely(!skb)) {
/* Free the first SG entry now, since we already
* unmapped it and obtained the virtual address
*/
free_pages((unsigned long)sg_vaddr, 0);
/* We still need to subtract the buffers used
* by this FD from our software counter
*/
while (!dpaa2_sg_is_final(&sgt[i]) &&
i < DPAA2_ETH_MAX_SG_ENTRIES)
i++;
break;
}
sg_offset = dpaa2_sg_get_offset(sge);
skb_reserve(skb, sg_offset);
skb_put(skb, sg_length);
} else {
/* Rest of the data buffers are stored as skb frags */
page = virt_to_page(sg_vaddr);
head_page = virt_to_head_page(sg_vaddr);
/* Offset in page (which may be compound).
* Data in subsequent SG entries is stored from the
* beginning of the buffer, so we don't need to add the
* sg_offset.
*/
page_offset = ((unsigned long)sg_vaddr &
(PAGE_SIZE - 1)) +
(page_address(page) - page_address(head_page));
skb_add_rx_frag(skb, i - 1, head_page, page_offset,
sg_length, priv->rx_buf_size);
}
if (dpaa2_sg_is_final(sge))
break;
}
WARN_ONCE(i == DPAA2_ETH_MAX_SG_ENTRIES, "Final bit not set in SGT");
/* Count all data buffers + SG table buffer */
ch->buf_count -= i + 2;
return skb;
}
/* Free buffers acquired from the buffer pool or which were meant to
* be released in the pool
*/
static void dpaa2_eth_free_bufs(struct dpaa2_eth_priv *priv, u64 *buf_array,
int count, bool xsk_zc)
{
struct device *dev = priv->net_dev->dev.parent;
struct dpaa2_eth_swa *swa;
struct xdp_buff *xdp_buff;
void *vaddr;
int i;
for (i = 0; i < count; i++) {
vaddr = dpaa2_iova_to_virt(priv->iommu_domain, buf_array[i]);
if (!xsk_zc) {
dma_unmap_page(dev, buf_array[i], priv->rx_buf_size,
DMA_BIDIRECTIONAL);
free_pages((unsigned long)vaddr, 0);
} else {
swa = (struct dpaa2_eth_swa *)
(vaddr + DPAA2_ETH_RX_HWA_SIZE);
xdp_buff = swa->xsk.xdp_buff;
xsk_buff_free(xdp_buff);
}
}
}
void dpaa2_eth_recycle_buf(struct dpaa2_eth_priv *priv,
struct dpaa2_eth_channel *ch,
dma_addr_t addr)
{
int retries = 0;
int err;
ch->recycled_bufs[ch->recycled_bufs_cnt++] = addr;
if (ch->recycled_bufs_cnt < DPAA2_ETH_BUFS_PER_CMD)
return;
while ((err = dpaa2_io_service_release(ch->dpio, ch->bp->bpid,
ch->recycled_bufs,
ch->recycled_bufs_cnt)) == -EBUSY) {
if (retries++ >= DPAA2_ETH_SWP_BUSY_RETRIES)
break;
cpu_relax();
}
if (err) {
dpaa2_eth_free_bufs(priv, ch->recycled_bufs,
ch->recycled_bufs_cnt, ch->xsk_zc);
ch->buf_count -= ch->recycled_bufs_cnt;
}
ch->recycled_bufs_cnt = 0;
}
static int dpaa2_eth_xdp_flush(struct dpaa2_eth_priv *priv,
struct dpaa2_eth_fq *fq,
struct dpaa2_eth_xdp_fds *xdp_fds)
{
int total_enqueued = 0, retries = 0, enqueued;
struct dpaa2_eth_drv_stats *percpu_extras;
int num_fds, err, max_retries;
struct dpaa2_fd *fds;
percpu_extras = this_cpu_ptr(priv->percpu_extras);
/* try to enqueue all the FDs until the max number of retries is hit */
fds = xdp_fds->fds;
num_fds = xdp_fds->num;
max_retries = num_fds * DPAA2_ETH_ENQUEUE_RETRIES;
while (total_enqueued < num_fds && retries < max_retries) {
err = priv->enqueue(priv, fq, &fds[total_enqueued],
0, num_fds - total_enqueued, &enqueued);
if (err == -EBUSY) {
percpu_extras->tx_portal_busy += ++retries;
continue;
}
total_enqueued += enqueued;
}
xdp_fds->num = 0;
return total_enqueued;
}
static void dpaa2_eth_xdp_tx_flush(struct dpaa2_eth_priv *priv,
struct dpaa2_eth_channel *ch,
struct dpaa2_eth_fq *fq)
{
struct rtnl_link_stats64 *percpu_stats;
struct dpaa2_fd *fds;
int enqueued, i;
percpu_stats = this_cpu_ptr(priv->percpu_stats);
// enqueue the array of XDP_TX frames
enqueued = dpaa2_eth_xdp_flush(priv, fq, &fq->xdp_tx_fds);
/* update statistics */
percpu_stats->tx_packets += enqueued;
fds = fq->xdp_tx_fds.fds;
for (i = 0; i < enqueued; i++) {
percpu_stats->tx_bytes += dpaa2_fd_get_len(&fds[i]);
ch->stats.xdp_tx++;
}
for (i = enqueued; i < fq->xdp_tx_fds.num; i++) {
dpaa2_eth_recycle_buf(priv, ch, dpaa2_fd_get_addr(&fds[i]));
percpu_stats->tx_errors++;
ch->stats.xdp_tx_err++;
}
fq->xdp_tx_fds.num = 0;
}
void dpaa2_eth_xdp_enqueue(struct dpaa2_eth_priv *priv,
struct dpaa2_eth_channel *ch,
struct dpaa2_fd *fd,
void *buf_start, u16 queue_id)
{
struct dpaa2_faead *faead;
struct dpaa2_fd *dest_fd;
struct dpaa2_eth_fq *fq;
u32 ctrl, frc;
/* Mark the egress frame hardware annotation area as valid */
frc = dpaa2_fd_get_frc(fd);
dpaa2_fd_set_frc(fd, frc | DPAA2_FD_FRC_FAEADV);
dpaa2_fd_set_ctrl(fd, DPAA2_FD_CTRL_ASAL);
/* Instruct hardware to release the FD buffer directly into
* the buffer pool once transmission is completed, instead of
* sending a Tx confirmation frame to us
*/
ctrl = DPAA2_FAEAD_A4V | DPAA2_FAEAD_A2V | DPAA2_FAEAD_EBDDV;
faead = dpaa2_get_faead(buf_start, false);
faead->ctrl = cpu_to_le32(ctrl);
faead->conf_fqid = 0;
fq = &priv->fq[queue_id];
dest_fd = &fq->xdp_tx_fds.fds[fq->xdp_tx_fds.num++];
memcpy(dest_fd, fd, sizeof(*dest_fd));
if (fq->xdp_tx_fds.num < DEV_MAP_BULK_SIZE)
return;
dpaa2_eth_xdp_tx_flush(priv, ch, fq);
}
static u32 dpaa2_eth_run_xdp(struct dpaa2_eth_priv *priv,
struct dpaa2_eth_channel *ch,
struct dpaa2_eth_fq *rx_fq,
struct dpaa2_fd *fd, void *vaddr)
{
dma_addr_t addr = dpaa2_fd_get_addr(fd);
struct bpf_prog *xdp_prog;
struct xdp_buff xdp;
u32 xdp_act = XDP_PASS;
int err, offset;
xdp_prog = READ_ONCE(ch->xdp.prog);
if (!xdp_prog)
goto out;
offset = dpaa2_fd_get_offset(fd) - XDP_PACKET_HEADROOM;
xdp_init_buff(&xdp, DPAA2_ETH_RX_BUF_RAW_SIZE - offset, &ch->xdp_rxq);
xdp_prepare_buff(&xdp, vaddr + offset, XDP_PACKET_HEADROOM,
dpaa2_fd_get_len(fd), false);
xdp_act = bpf_prog_run_xdp(xdp_prog, &xdp);
/* xdp.data pointer may have changed */
dpaa2_fd_set_offset(fd, xdp.data - vaddr);
dpaa2_fd_set_len(fd, xdp.data_end - xdp.data);
switch (xdp_act) {
case XDP_PASS:
break;
case XDP_TX:
dpaa2_eth_xdp_enqueue(priv, ch, fd, vaddr, rx_fq->flowid);
break;
default:
bpf_warn_invalid_xdp_action(priv->net_dev, xdp_prog, xdp_act);
fallthrough;
case XDP_ABORTED:
trace_xdp_exception(priv->net_dev, xdp_prog, xdp_act);
fallthrough;
case XDP_DROP:
dpaa2_eth_recycle_buf(priv, ch, addr);
ch->stats.xdp_drop++;
break;
case XDP_REDIRECT:
dma_unmap_page(priv->net_dev->dev.parent, addr,
priv->rx_buf_size, DMA_BIDIRECTIONAL);
ch->buf_count--;
/* Allow redirect use of full headroom */
xdp.data_hard_start = vaddr;
xdp.frame_sz = DPAA2_ETH_RX_BUF_RAW_SIZE;
err = xdp_do_redirect(priv->net_dev, &xdp, xdp_prog);
if (unlikely(err)) {
addr = dma_map_page(priv->net_dev->dev.parent,
virt_to_page(vaddr), 0,
priv->rx_buf_size, DMA_BIDIRECTIONAL);
if (unlikely(dma_mapping_error(priv->net_dev->dev.parent, addr))) {
free_pages((unsigned long)vaddr, 0);
} else {
ch->buf_count++;
dpaa2_eth_recycle_buf(priv, ch, addr);
}
ch->stats.xdp_drop++;
} else {
ch->stats.xdp_redirect++;
}
break;
}
ch->xdp.res |= xdp_act;
out:
return xdp_act;
}
struct sk_buff *dpaa2_eth_alloc_skb(struct dpaa2_eth_priv *priv,
struct dpaa2_eth_channel *ch,
const struct dpaa2_fd *fd, u32 fd_length,
void *fd_vaddr)
{
u16 fd_offset = dpaa2_fd_get_offset(fd);
struct sk_buff *skb = NULL;
unsigned int skb_len;
skb_len = fd_length + dpaa2_eth_needed_headroom(NULL);
skb = napi_alloc_skb(&ch->napi, skb_len);
if (!skb)
return NULL;
skb_reserve(skb, dpaa2_eth_needed_headroom(NULL));
skb_put(skb, fd_length);
memcpy(skb->data, fd_vaddr + fd_offset, fd_length);
dpaa2_eth_recycle_buf(priv, ch, dpaa2_fd_get_addr(fd));
return skb;
}
static struct sk_buff *dpaa2_eth_copybreak(struct dpaa2_eth_channel *ch,
const struct dpaa2_fd *fd,
void *fd_vaddr)
{
struct dpaa2_eth_priv *priv = ch->priv;
u32 fd_length = dpaa2_fd_get_len(fd);
if (fd_length > priv->rx_copybreak)
return NULL;
return dpaa2_eth_alloc_skb(priv, ch, fd, fd_length, fd_vaddr);
}
void dpaa2_eth_receive_skb(struct dpaa2_eth_priv *priv, struct dpaa2_eth_channel *ch,
const struct dpaa2_fd *fd, void *vaddr,
struct dpaa2_eth_fq *fq,
struct rtnl_link_stats64 *percpu_stats,
struct sk_buff *skb)
{
struct dpaa2_fas *fas;
u32 status = 0;
fas = dpaa2_get_fas(vaddr, false);
prefetch(fas);
prefetch(skb->data);
/* Get the timestamp value */
if (priv->rx_tstamp) {
struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
__le64 *ts = dpaa2_get_ts(vaddr, false);
u64 ns;
memset(shhwtstamps, 0, sizeof(*shhwtstamps));
ns = DPAA2_PTP_CLK_PERIOD_NS * le64_to_cpup(ts);
shhwtstamps->hwtstamp = ns_to_ktime(ns);
}
/* Check if we need to validate the L4 csum */
if (likely(dpaa2_fd_get_frc(fd) & DPAA2_FD_FRC_FASV)) {
status = le32_to_cpu(fas->status);
dpaa2_eth_validate_rx_csum(priv, status, skb);
}
skb->protocol = eth_type_trans(skb, priv->net_dev);
skb_record_rx_queue(skb, fq->flowid);
percpu_stats->rx_packets++;
percpu_stats->rx_bytes += dpaa2_fd_get_len(fd);
ch->stats.bytes_per_cdan += dpaa2_fd_get_len(fd);
list_add_tail(&skb->list, ch->rx_list);
}
/* Main Rx frame processing routine */
void dpaa2_eth_rx(struct dpaa2_eth_priv *priv,
struct dpaa2_eth_channel *ch,
const struct dpaa2_fd *fd,
struct dpaa2_eth_fq *fq)
{
dma_addr_t addr = dpaa2_fd_get_addr(fd);
u8 fd_format = dpaa2_fd_get_format(fd);
void *vaddr;
struct sk_buff *skb;
struct rtnl_link_stats64 *percpu_stats;
struct dpaa2_eth_drv_stats *percpu_extras;
struct device *dev = priv->net_dev->dev.parent;
void *buf_data;
u32 xdp_act;
/* Tracing point */
trace_dpaa2_rx_fd(priv->net_dev, fd);
vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
dma_sync_single_for_cpu(dev, addr, priv->rx_buf_size,
DMA_BIDIRECTIONAL);
buf_data = vaddr + dpaa2_fd_get_offset(fd);
prefetch(buf_data);
percpu_stats = this_cpu_ptr(priv->percpu_stats);
percpu_extras = this_cpu_ptr(priv->percpu_extras);
if (fd_format == dpaa2_fd_single) {
xdp_act = dpaa2_eth_run_xdp(priv, ch, fq, (struct dpaa2_fd *)fd, vaddr);
if (xdp_act != XDP_PASS) {
percpu_stats->rx_packets++;
percpu_stats->rx_bytes += dpaa2_fd_get_len(fd);
return;
}
skb = dpaa2_eth_copybreak(ch, fd, vaddr);
if (!skb) {
dma_unmap_page(dev, addr, priv->rx_buf_size,
DMA_BIDIRECTIONAL);
skb = dpaa2_eth_build_linear_skb(ch, fd, vaddr);
}
} else if (fd_format == dpaa2_fd_sg) {
WARN_ON(priv->xdp_prog);
dma_unmap_page(dev, addr, priv->rx_buf_size,
DMA_BIDIRECTIONAL);
skb = dpaa2_eth_build_frag_skb(priv, ch, buf_data);
free_pages((unsigned long)vaddr, 0);
percpu_extras->rx_sg_frames++;
percpu_extras->rx_sg_bytes += dpaa2_fd_get_len(fd);
} else {
/* We don't support any other format */
goto err_frame_format;
}
if (unlikely(!skb))
goto err_build_skb;
dpaa2_eth_receive_skb(priv, ch, fd, vaddr, fq, percpu_stats, skb);
return;
err_build_skb:
dpaa2_eth_free_rx_fd(priv, fd, vaddr);
err_frame_format:
percpu_stats->rx_dropped++;
}
/* Processing of Rx frames received on the error FQ
* We check and print the error bits and then free the frame
*/
static void dpaa2_eth_rx_err(struct dpaa2_eth_priv *priv,
struct dpaa2_eth_channel *ch,
const struct dpaa2_fd *fd,
struct dpaa2_eth_fq *fq __always_unused)
{
struct device *dev = priv->net_dev->dev.parent;
dma_addr_t addr = dpaa2_fd_get_addr(fd);
u8 fd_format = dpaa2_fd_get_format(fd);
struct rtnl_link_stats64 *percpu_stats;
struct dpaa2_eth_trap_item *trap_item;
struct dpaa2_fapr *fapr;
struct sk_buff *skb;
void *buf_data;
void *vaddr;
vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
dma_sync_single_for_cpu(dev, addr, priv->rx_buf_size,
DMA_BIDIRECTIONAL);
buf_data = vaddr + dpaa2_fd_get_offset(fd);
if (fd_format == dpaa2_fd_single) {
dma_unmap_page(dev, addr, priv->rx_buf_size,
DMA_BIDIRECTIONAL);
skb = dpaa2_eth_build_linear_skb(ch, fd, vaddr);
} else if (fd_format == dpaa2_fd_sg) {
dma_unmap_page(dev, addr, priv->rx_buf_size,
DMA_BIDIRECTIONAL);
skb = dpaa2_eth_build_frag_skb(priv, ch, buf_data);
free_pages((unsigned long)vaddr, 0);
} else {
/* We don't support any other format */
dpaa2_eth_free_rx_fd(priv, fd, vaddr);
goto err_frame_format;
}
fapr = dpaa2_get_fapr(vaddr, false);
trap_item = dpaa2_eth_dl_get_trap(priv, fapr);
if (trap_item)
devlink_trap_report(priv->devlink, skb, trap_item->trap_ctx,
&priv->devlink_port, NULL);
consume_skb(skb);
err_frame_format:
percpu_stats = this_cpu_ptr(priv->percpu_stats);
percpu_stats->rx_errors++;
ch->buf_count--;
}
/* Consume all frames pull-dequeued into the store. This is the simplest way to
* make sure we don't accidentally issue another volatile dequeue which would
* overwrite (leak) frames already in the store.
*
* Observance of NAPI budget is not our concern, leaving that to the caller.
*/
static int dpaa2_eth_consume_frames(struct dpaa2_eth_channel *ch,
struct dpaa2_eth_fq **src)
{
struct dpaa2_eth_priv *priv = ch->priv;
struct dpaa2_eth_fq *fq = NULL;
struct dpaa2_dq *dq;
const struct dpaa2_fd *fd;
int cleaned = 0, retries = 0;
int is_last;
do {
dq = dpaa2_io_store_next(ch->store, &is_last);
if (unlikely(!dq)) {
/* If we're here, we *must* have placed a
* volatile dequeue comnmand, so keep reading through
* the store until we get some sort of valid response
* token (either a valid frame or an "empty dequeue")
*/
if (retries++ >= DPAA2_ETH_SWP_BUSY_RETRIES) {
netdev_err_once(priv->net_dev,
"Unable to read a valid dequeue response\n");
return -ETIMEDOUT;
}
continue;
}
fd = dpaa2_dq_fd(dq);
fq = (struct dpaa2_eth_fq *)(uintptr_t)dpaa2_dq_fqd_ctx(dq);
fq->consume(priv, ch, fd, fq);
cleaned++;
retries = 0;
} while (!is_last);
if (!cleaned)
return 0;
fq->stats.frames += cleaned;
ch->stats.frames += cleaned;
ch->stats.frames_per_cdan += cleaned;
/* A dequeue operation only pulls frames from a single queue
* into the store. Return the frame queue as an out param.
*/
if (src)
*src = fq;
return cleaned;
}
static int dpaa2_eth_ptp_parse(struct sk_buff *skb,
u8 *msgtype, u8 *twostep, u8 *udp,
u16 *correction_offset,
u16 *origintimestamp_offset)
{
unsigned int ptp_class;
struct ptp_header *hdr;
unsigned int type;
u8 *base;
ptp_class = ptp_classify_raw(skb);
if (ptp_class == PTP_CLASS_NONE)
return -EINVAL;
hdr = ptp_parse_header(skb, ptp_class);
if (!hdr)
return -EINVAL;
*msgtype = ptp_get_msgtype(hdr, ptp_class);
*twostep = hdr->flag_field[0] & 0x2;
type = ptp_class & PTP_CLASS_PMASK;
if (type == PTP_CLASS_IPV4 ||
type == PTP_CLASS_IPV6)
*udp = 1;
else
*udp = 0;
base = skb_mac_header(skb);
*correction_offset = (u8 *)&hdr->correction - base;
*origintimestamp_offset = (u8 *)hdr + sizeof(struct ptp_header) - base;
return 0;
}
/* Configure the egress frame annotation for timestamp update */
static void dpaa2_eth_enable_tx_tstamp(struct dpaa2_eth_priv *priv,
struct dpaa2_fd *fd,
void *buf_start,
struct sk_buff *skb)
{
struct ptp_tstamp origin_timestamp;
u8 msgtype, twostep, udp;
struct dpaa2_faead *faead;
struct dpaa2_fas *fas;
struct timespec64 ts;
u16 offset1, offset2;
u32 ctrl, frc;
__le64 *ns;
u8 *data;
/* Mark the egress frame annotation area as valid */
frc = dpaa2_fd_get_frc(fd);
dpaa2_fd_set_frc(fd, frc | DPAA2_FD_FRC_FAEADV);
/* Set hardware annotation size */
ctrl = dpaa2_fd_get_ctrl(fd);
dpaa2_fd_set_ctrl(fd, ctrl | DPAA2_FD_CTRL_ASAL);
/* enable UPD (update prepanded data) bit in FAEAD field of
* hardware frame annotation area
*/
ctrl = DPAA2_FAEAD_A2V | DPAA2_FAEAD_UPDV | DPAA2_FAEAD_UPD;
faead = dpaa2_get_faead(buf_start, true);
faead->ctrl = cpu_to_le32(ctrl);
if (skb->cb[0] == TX_TSTAMP_ONESTEP_SYNC) {
if (dpaa2_eth_ptp_parse(skb, &msgtype, &twostep, &udp,
&offset1, &offset2) ||
msgtype != PTP_MSGTYPE_SYNC || twostep) {
WARN_ONCE(1, "Bad packet for one-step timestamping\n");
return;
}
/* Mark the frame annotation status as valid */
frc = dpaa2_fd_get_frc(fd);
dpaa2_fd_set_frc(fd, frc | DPAA2_FD_FRC_FASV);
/* Mark the PTP flag for one step timestamping */
fas = dpaa2_get_fas(buf_start, true);
fas->status = cpu_to_le32(DPAA2_FAS_PTP);
dpaa2_ptp->caps.gettime64(&dpaa2_ptp->caps, &ts);
ns = dpaa2_get_ts(buf_start, true);
*ns = cpu_to_le64(timespec64_to_ns(&ts) /
DPAA2_PTP_CLK_PERIOD_NS);
/* Update current time to PTP message originTimestamp field */
ns_to_ptp_tstamp(&origin_timestamp, le64_to_cpup(ns));
data = skb_mac_header(skb);
*(__be16 *)(data + offset2) = htons(origin_timestamp.sec_msb);
*(__be32 *)(data + offset2 + 2) =
htonl(origin_timestamp.sec_lsb);
*(__be32 *)(data + offset2 + 6) = htonl(origin_timestamp.nsec);
if (priv->ptp_correction_off == offset1)
return;
priv->dpaa2_set_onestep_params_cb(priv, offset1, udp);
priv->ptp_correction_off = offset1;
}
}
void *dpaa2_eth_sgt_get(struct dpaa2_eth_priv *priv)
{
struct dpaa2_eth_sgt_cache *sgt_cache;
void *sgt_buf = NULL;
int sgt_buf_size;
sgt_cache = this_cpu_ptr(priv->sgt_cache);
sgt_buf_size = priv->tx_data_offset +
DPAA2_ETH_SG_ENTRIES_MAX * sizeof(struct dpaa2_sg_entry);
if (sgt_cache->count == 0)
sgt_buf = napi_alloc_frag_align(sgt_buf_size, DPAA2_ETH_TX_BUF_ALIGN);
else
sgt_buf = sgt_cache->buf[--sgt_cache->count];
if (!sgt_buf)
return NULL;
memset(sgt_buf, 0, sgt_buf_size);
return sgt_buf;
}
void dpaa2_eth_sgt_recycle(struct dpaa2_eth_priv *priv, void *sgt_buf)
{
struct dpaa2_eth_sgt_cache *sgt_cache;
sgt_cache = this_cpu_ptr(priv->sgt_cache);
if (sgt_cache->count >= DPAA2_ETH_SGT_CACHE_SIZE)
skb_free_frag(sgt_buf);
else
sgt_cache->buf[sgt_cache->count++] = sgt_buf;
}
/* Create a frame descriptor based on a fragmented skb */
static int dpaa2_eth_build_sg_fd(struct dpaa2_eth_priv *priv,
struct sk_buff *skb,
struct dpaa2_fd *fd,
void **swa_addr)
{
struct device *dev = priv->net_dev->dev.parent;
void *sgt_buf = NULL;
dma_addr_t addr;
int nr_frags = skb_shinfo(skb)->nr_frags;
struct dpaa2_sg_entry *sgt;
int i, err;
int sgt_buf_size;
struct scatterlist *scl, *crt_scl;
int num_sg;
int num_dma_bufs;
struct dpaa2_eth_swa *swa;
/* Create and map scatterlist.
* We don't advertise NETIF_F_FRAGLIST, so skb_to_sgvec() will not have
* to go beyond nr_frags+1.
* Note: We don't support chained scatterlists
*/
if (unlikely(PAGE_SIZE / sizeof(struct scatterlist) < nr_frags + 1))
return -EINVAL;
scl = kmalloc_array(nr_frags + 1, sizeof(struct scatterlist), GFP_ATOMIC);
if (unlikely(!scl))
return -ENOMEM;
sg_init_table(scl, nr_frags + 1);
num_sg = skb_to_sgvec(skb, scl, 0, skb->len);
if (unlikely(num_sg < 0)) {
err = -ENOMEM;
goto dma_map_sg_failed;
}
num_dma_bufs = dma_map_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL);
if (unlikely(!num_dma_bufs)) {
err = -ENOMEM;
goto dma_map_sg_failed;
}
/* Prepare the HW SGT structure */
sgt_buf_size = priv->tx_data_offset +
sizeof(struct dpaa2_sg_entry) * num_dma_bufs;
sgt_buf = dpaa2_eth_sgt_get(priv);
if (unlikely(!sgt_buf)) {
err = -ENOMEM;
goto sgt_buf_alloc_failed;
}
sgt = (struct dpaa2_sg_entry *)(sgt_buf + priv->tx_data_offset);
/* Fill in the HW SGT structure.
*
* sgt_buf is zeroed out, so the following fields are implicit
* in all sgt entries:
* - offset is 0
* - format is 'dpaa2_sg_single'
*/
for_each_sg(scl, crt_scl, num_dma_bufs, i) {
dpaa2_sg_set_addr(&sgt[i], sg_dma_address(crt_scl));
dpaa2_sg_set_len(&sgt[i], sg_dma_len(crt_scl));
}
dpaa2_sg_set_final(&sgt[i - 1], true);
/* Store the skb backpointer in the SGT buffer.
* Fit the scatterlist and the number of buffers alongside the
* skb backpointer in the software annotation area. We'll need
* all of them on Tx Conf.
*/
*swa_addr = (void *)sgt_buf;
swa = (struct dpaa2_eth_swa *)sgt_buf;
swa->type = DPAA2_ETH_SWA_SG;
swa->sg.skb = skb;
swa->sg.scl = scl;
swa->sg.num_sg = num_sg;
swa->sg.sgt_size = sgt_buf_size;
/* Separately map the SGT buffer */
addr = dma_map_single(dev, sgt_buf, sgt_buf_size, DMA_BIDIRECTIONAL);
if (unlikely(dma_mapping_error(dev, addr))) {
err = -ENOMEM;
goto dma_map_single_failed;
}
memset(fd, 0, sizeof(struct dpaa2_fd));
dpaa2_fd_set_offset(fd, priv->tx_data_offset);
dpaa2_fd_set_format(fd, dpaa2_fd_sg);
dpaa2_fd_set_addr(fd, addr);
dpaa2_fd_set_len(fd, skb->len);
dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
return 0;
dma_map_single_failed:
dpaa2_eth_sgt_recycle(priv, sgt_buf);
sgt_buf_alloc_failed:
dma_unmap_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL);
dma_map_sg_failed:
kfree(scl);
return err;
}
/* Create a SG frame descriptor based on a linear skb.
*
* This function is used on the Tx path when the skb headroom is not large
* enough for the HW requirements, thus instead of realloc-ing the skb we
* create a SG frame descriptor with only one entry.