Question about L3 and L2 CAT and MBA

[PandaMengXu]

Hi,

I saw in README that both L2 and L3 CAT are supported in the software.
(1) Is L2 shared among all cores or only between the hardware threads?
(2) Is there any Intel CPU that supports both L2 and L3 CAT?

As to the Memory Bandwidth Allocation,
(3) Is there any Intel CPU that support Memory Bandwidth Allocation now? When should we expect to purchase it on the market?

Thank you very much for your help!

Meng

[ahetheri]

Hi Meng,

Thanks for getting in contact and showing an interest in RDT. We would love to hear how you are using these tools and would be happy to receive feedback on your experience.

To answer your questions:

1. It depends on the product type. L2 is designed a different way depending on the product you have. Have a look into Intel's SDM for more information: https://software.intel.com/en-us/articles/intel-sdm
2. This user space software enables L2 /L3 CAT and MBA based on the SDM linked above. I cannot advice on products implementing these technologies apart from the table in the README.
3. Same as above.

Best,
Aaron

[PandaMengXu]

Hi Aaron,

1. I read the Intel SDM for several times. I wrote the similar module in Linux and Xen before. So I got the background of CAT, L2 and L3. :-)
   The reason why I ask is because L2 is shared among cores when there is no L3. It is unclear what the README meant about L2. There is no definition about L2's relation with cores. If L2 is shared, the L2 CAT is similar to L3 CAT. Otherwise, it's a totally different story. That's why I asked.

2. My second question is a follow-up to my first question. If no CPU can support both L2 and L3 CAT, the README table will be confusing, because it gives people, at least me, the illusion that some Intel CPU with L3 cache can achieve both L2 and L3 CAT.

3. Hmm, if we don't know which hardware supports which software functionality, which hardware should we purchase for your software? ;-)

Thank you very much!

Meng

[tkanteck]

Hi Meng,

Apologies that we cannot be more helpful here.
For validating L2 CAT software implementation we used one of these parts:
http://ark.intel.com/products/codename/63508/Denverton?q=denverton
and this product family doesn't have L3 cache.

I hope it helps
Tomasz

[PandaMengXu]

Hi Tomasz,

Thank you very much for your information! :-)

Meng

[tkanteck]

Let me close this issue. Feel free to open a new one if you have further questions.
Tomasz