Will 1 L1 miss trigger both 1 L2 reference and 1 L3 reference at the same time?

[oleotiger]

Assuming there is a load instruction and the cache line is not stored in L1 and L2. But it can be found in L3.

Q1:

According to the document of Intel, L2 and L3 are non-inclusive. So, if there is a L1 miss, will the cache line be looking up both in L2 and L3 at the same time?

Or it just be looked up in L2, if missed , go to L3?

Q2:
If the cache line is looked up both in L2 and L3 and L2 missed but L3 hitted, will the cache line be transferred to L1 directly or through L2? Will L2 keep one copy of it in case of nect reference to avoding long latency for accessing L3?

[opcm]

I think this Intel forum is a better place for your question: https://community.intel.com/t5/Software-Tuning-Performance/bd-p/software-tuning-perf-optimization