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Many people coming to ROHD-VF will have some experience in SystemVerilog UVM. An example of how they differ would be valuable.
Add documentation and/or an example with the same thing implemented in SystemVerilog/UVM and ROHD-VF.
Leave documentation solely focused on ROHD-VF.
The text was updated successfully, but these errors were encountered:
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Motivation
Many people coming to ROHD-VF will have some experience in SystemVerilog UVM. An example of how they differ would be valuable.
Desired solution
Add documentation and/or an example with the same thing implemented in SystemVerilog/UVM and ROHD-VF.
Alternatives considered
Leave documentation solely focused on ROHD-VF.
The text was updated successfully, but these errors were encountered: