Check output changes based on the inputs changes, System Verilog assert property

[quekyj]

Normally we want to check if my input is something, x clock later, my outputs changed to something else. Is there anyways to monitor / listen to input changes and check for output changes at x clock later. In system Verilog, we can use assert property.

Something like this:
This means A must occur within 1 to 20 clk cycles after B occurred

p1: assert property(
@(posedge clk)
B |-> ##[1:20] A;)