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In clocks_us_serdes.vhd and clocks_usp_serdes.vhd, the reset signal for the aux clock domain depends directly on the pre-buffer aux clock signal clk_aux_i rather than the post-buffer aux clock signal clk_aux_b that is used for the output port. E.g:
process(clk_aux_i)
begin
if rising_edge(clk_aux_i) then
rst_aux <= rst;
end if;
end process;
These process statements should be updated to use the post-buffer signal
In
clocks_us_serdes.vhd
andclocks_usp_serdes.vhd
, the reset signal for the aux clock domain depends directly on the pre-buffer aux clock signalclk_aux_i
rather than the post-buffer aux clock signalclk_aux_b
that is used for the output port. E.g:These process statements should be updated to use the post-buffer signal
(Spotted by @dmnewbold )
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