Add a lower-speed, CPLL-based version of the XDMA interface #216
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These changes add a second version of the XDMA IP core. In addition to the 8 Gb/s version that requires a QPLL, there is now also a 5 Gb/s second version that is satisfied with a CPLL.
All examples have been verified to build, and both XDMA IP cores have been verified to work in third-party designs.
Since I have no access to PCIe setups corresponding to the example designs, these themselves have not explicitly been verified.
Note: two additional 'small fixes' for the PCIe example designs are included as well. Neither problem was big enough to be noticed until now, apparently.