/
6328_map_part.h
1418 lines (1259 loc) · 51.5 KB
/
6328_map_part.h
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/*
Copyright 2000-2010 Broadcom Corporation
<:label-BRCM:2011:DUAL/GPL:standard
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License, version 2, as published by
the Free Software Foundation (the "GPL").
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA.
:>
*/
#ifndef __BCM6328_MAP_PART_H
#define __BCM6328_MAP_PART_H
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __BCM6328_MAP_H
#define __BCM6328_MAP_H
#include "bcmtypes.h"
#define PERF_BASE 0xb0000000 /* chip control registers */
#define TIMR_BASE 0xb0000040 /* timer registers */
#define GPIO_BASE 0xb0000080 /* gpio registers */
#define UART_BASE 0xb0000100 /* uart registers */
#define UART1_BASE 0xb0000120 /* uart registers */
#define NAND_REG_BASE 0xb0000200 /* NAND registers */
#define NAND_CACHE_BASE 0xb0000400
#define LED_BASE 0xb0000800 /* LED control registers */
#define HSSPIM_BASE 0xb0001000 /* High-Speed SPI registers */
#define MISC_BASE 0xb0001800 /* Miscellaneous Registers */
#define USB_CTL_BASE 0xb0002400 /* USB 2.0 device control registers */
#define USB_EHCI_BASE 0x10002500 /* USB host registers */
#define USB_OHCI_BASE 0x10002600 /* USB host registers */
#define USBH_CFG_BASE 0xb0002700
#define DDR_BASE 0xb0003000 /* Memory control registers */
#define SAR_DMA_BASE 0xb000b800 /* ATM SAR DMA control registers */
#define SWITCH_DMA_BASE 0xb000d800
#define SWITCH_BASE 0xb0e00000
#define PCIE_BASE 0xb0e40000
/*
** NAND Controller Registers
*/
typedef struct NandCtrlRegs {
uint32 NandRevision; /* NAND Revision */
uint32 NandCmdStart; /* Nand Flash Command Start */
uint32 NandCmdExtAddr; /* Nand Flash Command Extended Address */
uint32 NandCmdAddr; /* Nand Flash Command Address */
uint32 NandCmdEndAddr; /* Nand Flash Command End Address */
uint32 NandNandBootConfig; /* Nand Flash Boot Config */
#define NBC_AUTO_DEV_ID_CFG 0x40000000
uint32 NandCsNandXor; /* Nand Flash EBI CS Address XOR with */
} NandCtrlRegs;
#define NAND ((volatile NandCtrlRegs * const) NAND_REG_BASE)
#endif
typedef struct DDRPhyControl {
uint32 REVISION; /* 0x00 */
uint32 CLK_PM_CTRL; /* 0x04 */
uint32 unused0[2]; /* 0x08-0x10 */
uint32 PLL_STATUS; /* 0x10 */
uint32 PLL_CONFIG; /* 0x14 */
uint32 PLL_PRE_DIVIDER; /* 0x18 */
uint32 PLL_DIVIDER; /* 0x1c */
uint32 PLL_CONTROL1; /* 0x20 */
uint32 PLL_CONTROL2; /* 0x24 */
uint32 PLL_SS_EN; /* 0x28 */
uint32 PLL_SS_CFG; /* 0x2c */
uint32 STATIC_VDL_OVERRIDE; /* 0x30 */
uint32 DYNAMIC_VDL_OVERRIDE; /* 0x34 */
uint32 IDLE_PAD_CONTROL; /* 0x38 */
uint32 ZQ_PVT_COMP_CTL; /* 0x3c */
uint32 DRIVE_PAD_CTL; /* 0x40 */
uint32 CLOCK_REG_CONTROL; /* 0x44 */
uint32 unused1[46];
} DDRPhyControl;
typedef struct DDRPhyByteLaneControl {
uint32 REVISION; /* 0x00 */
uint32 VDL_CALIBRATE; /* 0x04 */
uint32 VDL_STATUS; /* 0x08 */
uint32 unused; /* 0x0c */
uint32 VDL_OVERRIDE_0; /* 0x10 */
uint32 VDL_OVERRIDE_1; /* 0x14 */
uint32 VDL_OVERRIDE_2; /* 0x18 */
uint32 VDL_OVERRIDE_3; /* 0x1c */
uint32 VDL_OVERRIDE_4; /* 0x20 */
uint32 VDL_OVERRIDE_5; /* 0x24 */
uint32 VDL_OVERRIDE_6; /* 0x28 */
uint32 VDL_OVERRIDE_7; /* 0x2c */
uint32 READ_CONTROL; /* 0x30 */
uint32 READ_FIFO_STATUS; /* 0x34 */
uint32 READ_FIFO_CLEAR; /* 0x38 */
uint32 IDLE_PAD_CONTROL; /* 0x3c */
uint32 DRIVE_PAD_CTL; /* 0x40 */
uint32 CLOCK_PAD_DISABLE; /* 0x44 */
uint32 WR_PREAMBLE_MODE; /* 0x48 */
uint32 CLOCK_REG_CONTROL; /* 0x4C */
uint32 unused0[44];
} DDRPhyByteLaneControl;
typedef struct DDRControl {
uint32 CNFG; /* 0x000 */
uint32 CSST; /* 0x004 */
uint32 CSEND; /* 0x008 */
uint32 unused; /* 0x00c */
uint32 ROW00_0; /* 0x010 */
uint32 ROW00_1; /* 0x014 */
uint32 ROW01_0; /* 0x018 */
uint32 ROW01_1; /* 0x01c */
uint32 unused0[4];
uint32 ROW20_0; /* 0x030 */
uint32 ROW20_1; /* 0x034 */
uint32 ROW21_0; /* 0x038 */
uint32 ROW21_1; /* 0x03c */
uint32 unused1[4];
uint32 COL00_0; /* 0x050 */
uint32 COL00_1; /* 0x054 */
uint32 COL01_0; /* 0x058 */
uint32 COL01_1; /* 0x05c */
uint32 unused2[4];
uint32 COL20_0; /* 0x070 */
uint32 COL20_1; /* 0x074 */
uint32 COL21_0; /* 0x078 */
uint32 COL21_1; /* 0x07c */
uint32 unused3[4];
uint32 BNK10; /* 0x090 */
uint32 BNK32; /* 0x094 */
uint32 unused4[26];
uint32 DCMD; /* 0x100 */
#define DCMD_CS1 (1 << 5)
#define DCMD_CS0 (1 << 4)
#define DCMD_SET_SREF 4
uint32 DMODE_0; /* 0x104 */
uint32 DMODE_1; /* 0x108 */
#define DMODE_1_DRAMSLEEP (1 << 11)
uint32 CLKS; /* 0x10c */
uint32 ODT; /* 0x110 */
uint32 TIM1_0; /* 0x114 */
uint32 TIM1_1; /* 0x118 */
uint32 TIM2; /* 0x11c */
uint32 CTL_CRC; /* 0x120 */
uint32 DOUT_CRC; /* 0x124 */
uint32 DIN_CRC; /* 0x128 */
uint32 unused5[53];
DDRPhyControl PhyControl; /* 0x200 */
DDRPhyByteLaneControl PhyByteLane0Control; /* 0x300 */
DDRPhyByteLaneControl PhyByteLane1Control; /* 0x400 */
DDRPhyByteLaneControl PhyByteLane2Control; /* 0x500 */
DDRPhyByteLaneControl PhyByteLane3Control; /* 0x600 */
uint32 unused6[64];
uint32 GCFG; /* 0x800 */
uint32 LBIST_CFG; /* 0x804 */
uint32 LBIST_SEED; /* 0x808 */
uint32 ARB; /* 0x80c */
uint32 PI_GCF; /* 0x810 */
uint32 PI_UBUS_CTL; /* 0x814 */
uint32 PI_MIPS_CTL; /* 0x818 */
uint32 PI_DSL_MIPS_CTL; /* 0x81c */
uint32 PI_DSL_PHY_CTL; /* 0x820 */
uint32 PI_UBUS_ST; /* 0x824 */
uint32 PI_MIPS_ST; /* 0x828 */
uint32 PI_DSL_MIPS_ST; /* 0x82c */
uint32 PI_DSL_PHY_ST; /* 0x830 */
uint32 PI_UBUS_SMPL; /* 0x834 */
uint32 TESTMODE; /* 0x838 */
uint32 TEST_CFG1; /* 0x83c */
uint32 TEST_PAT; /* 0x840 */
uint32 TEST_COUNT; /* 0x844 */
uint32 TEST_CURR_COUNT; /* 0x848 */
uint32 TEST_ADDR_UPDT; /* 0x84c */
uint32 TEST_ADDR; /* 0x850 */
uint32 TEST_DATA0; /* 0x854 */
uint32 TEST_DATA1; /* 0x858 */
uint32 TEST_DATA2; /* 0x85c */
uint32 TEST_DATA3; /* 0x860 */
} DDRControl;
#define DDR ((volatile DDRControl * const) DDR_BASE)
/*
** Peripheral Controller
*/
#define IRQ_BITS 64
typedef struct {
uint64 IrqMask;
uint64 IrqStatus;
} IrqControl_t;
typedef struct PerfControl {
uint32 RevID; /* (00) word 0 */
#define CHIP_ID_SHIFT 16
#define CHIP_ID_MASK (0xffff << CHIP_ID_SHIFT)
#define REV_ID_MASK 0xff
uint32 blkEnables; /* (04) word 1 */
#define ROBOSW_CLK_EN (1 << 11)
#define PCIE_CLK_EN (1 << 10)
#define HS_SPI_CLK_EN (1 << 9)
#define USBH_CLK_EN (1 << 8)
#define USBD_CLK_EN (1 << 7)
#define PCM_CLK_EN (1 << 6)
#define SAR_CLK_EN (1 << 5)
#define MIPS_CLK_EN (1 << 4)
#define ADSL_CLK_EN (1 << 3)
#define ADSL_AFE_EN (1 << 2)
#define ADSL_QPROC_EN (1 << 1)
#define PHYMIPS_CLK_EN (1 << 0)
uint32 unused0; /* (08) word 2 */
uint32 deviceTimeoutEn; /* (0c) word 3 */
uint32 softResetB; /* (10) word 4 */
#define SOFT_RST_PCIE_HARD (1 << 10)
#define SOFT_RST_PCIE_EXT (1 << 9)
#define SOFT_RST_PCIE (1 << 8)
#define SOFT_RST_PCIE_CORE (1 << 7)
#define SOFT_RST_PCM (1 << 6)
#define SOFT_RST_USBH (1 << 5)
#define SOFT_RST_USBD (1 << 4)
#define SOFT_RST_SWITCH (1 << 3)
#define SOFT_RST_SAR (1 << 2)
#define SOFT_RST_EPHY (1 << 1)
#define SOFT_RST_SPI (1 << 0)
uint32 diagControl; /* (14) word 5 */
uint32 ExtIrqCfg; /* (18) word 6*/
uint32 unused1; /* (1c) word 7 */
#define EI_SENSE_SHFT 0
#define EI_STATUS_SHFT 4
#define EI_CLEAR_SHFT 8
#define EI_MASK_SHFT 12
#define EI_INSENS_SHFT 16
#define EI_LEVEL_SHFT 20
IrqControl_t IrqControl[2];
} PerfControl;
#define PERF ((volatile PerfControl * const) PERF_BASE)
/*
** Timer
*/
typedef struct Timer {
uint16 unused0;
byte TimerMask;
#define TIMER0EN 0x01
#define TIMER1EN 0x02
#define TIMER2EN 0x04
byte TimerInts;
#define TIMER0 0x01
#define TIMER1 0x02
#define TIMER2 0x04
#define WATCHDOG 0x08
uint32 TimerCtl0;
uint32 TimerCtl1;
uint32 TimerCtl2;
#define TIMERENABLE 0x80000000
#define RSTCNTCLR 0x40000000
uint32 TimerCnt0;
uint32 TimerCnt1;
uint32 TimerCnt2;
uint32 WatchDogDefCount;
/* Write 0xff00 0x00ff to Start timer
* Write 0xee00 0x00ee to Stop and re-load default count
* Read from this register returns current watch dog count
*/
uint32 WatchDogCtl;
/* Number of 50-MHz ticks for WD Reset pulse to last */
uint32 WDResetCount;
uint32 SoftRst;
#define SOFT_RESET 0x00000001 // 0
} Timer;
#define TIMER ((volatile Timer * const) TIMR_BASE)
/*
** UART
*/
typedef struct UartChannel {
byte unused0;
byte control;
#define BRGEN 0x80 /* Control register bit defs */
#define TXEN 0x40
#define RXEN 0x20
#define LOOPBK 0x10
#define TXPARITYEN 0x08
#define TXPARITYEVEN 0x04
#define RXPARITYEN 0x02
#define RXPARITYEVEN 0x01
byte config;
#define XMITBREAK 0x40
#define BITS5SYM 0x00
#define BITS6SYM 0x10
#define BITS7SYM 0x20
#define BITS8SYM 0x30
#define ONESTOP 0x07
#define TWOSTOP 0x0f
/* 4-LSBS represent STOP bits/char
* in 1/8 bit-time intervals. Zero
* represents 1/8 stop bit interval.
* Fifteen represents 2 stop bits.
*/
byte fifoctl;
#define RSTTXFIFOS 0x80
#define RSTRXFIFOS 0x40
/* 5-bit TimeoutCnt is in low bits of this register.
* This count represents the number of characters
* idle times before setting receive Irq when below threshold
*/
uint32 baudword;
/* When divide SysClk/2/(1+baudword) we should get 32*bit-rate
*/
byte txf_levl; /* Read-only fifo depth */
byte rxf_levl; /* Read-only fifo depth */
byte fifocfg; /* Upper 4-bits are TxThresh, Lower are
* RxThreshold. Irq can be asserted
* when rx fifo> thresh, txfifo<thresh
*/
byte prog_out; /* Set value of DTR (Bit0), RTS (Bit1)
* if these bits are also enabled to GPIO_o
*/
#define DTREN 0x01
#define RTSEN 0x02
byte unused1;
byte DeltaIPEdgeNoSense; /* Low 4-bits, set corr bit to 1 to
* detect irq on rising AND falling
* edges for corresponding GPIO_i
* if enabled (edge insensitive)
*/
byte DeltaIPConfig_Mask; /* Upper 4 bits: 1 for posedge sense
* 0 for negedge sense if
* not configured for edge
* insensitive (see above)
* Lower 4 bits: Mask to enable change
* detection IRQ for corresponding
* GPIO_i
*/
byte DeltaIP_SyncIP; /* Upper 4 bits show which bits
* have changed (may set IRQ).
* read automatically clears bit
* Lower 4 bits are actual status
*/
uint16 intMask; /* Same Bit defs for Mask and status */
uint16 intStatus;
#define DELTAIP 0x0001
#define TXUNDERR 0x0002
#define TXOVFERR 0x0004
#define TXFIFOTHOLD 0x0008
#define TXREADLATCH 0x0010
#define TXFIFOEMT 0x0020
#define RXUNDERR 0x0040
#define RXOVFERR 0x0080
#define RXTIMEOUT 0x0100
#define RXFIFOFULL 0x0200
#define RXFIFOTHOLD 0x0400
#define RXFIFONE 0x0800
#define RXFRAMERR 0x1000
#define RXPARERR 0x2000
#define RXBRK 0x4000
uint16 unused2;
uint16 Data; /* Write to TX, Read from RX */
/* bits 11:8 are BRK,PAR,FRM errors */
uint32 unused3;
uint32 unused4;
} Uart;
#define UART ((volatile Uart * const) UART_BASE)
/*
** Gpio Controller
*/
#pragma pack(push, 4)
typedef struct GpioControl {
uint32 GPIODirHi; /* 0 */
uint32 GPIODir; /* 4 */
uint32 GPIOioHi; /* 8 */
uint32 GPIOio; /* C */
uint32 unused0; /* 10 */
uint32 SpiSlaveCfg; /* 14 */
uint32 GPIOMode; /* 18 */
uint64 PinMuxSel; /* 1C */
#define SERIAL_LED_DATA 6
#define SERIAL_LED_CLK 7
#define INET_ACT_LED 11
#define PCIE_CLKREQ 16
#define EPHY0_SPD_LED 17
#define EPHY1_SPD_LED 18
#define EPHY2_SPD_LED 19
#define EPHY3_SPD_LED 20
#define EPHY0_ACT_LED 25
#define EPHY1_ACT_LED 26
#define EPHY2_ACT_LED 27
#define EPHY3_ACT_LED 28
#define PINMUX_SERIAL_LED_DATA ((uint64)2 << (SERIAL_LED_DATA << 1))
#define PINMUX_SERIAL_LED_CLK ((uint64)2 << (SERIAL_LED_CLK << 1))
#define PINMUX_INET_ACT_LED ((uint64)1 << (INET_ACT_LED << 1))
#define PINMUX_PCIE_CLKREQ ((uint64)2 << (PCIE_CLKREQ << 1))
#define PINMUX_EPHY0_ACT_LED ((uint64)1 << (EPHY0_ACT_LED << 1))
#define PINMUX_EPHY1_ACT_LED ((uint64)1 << (EPHY1_ACT_LED << 1))
#define PINMUX_EPHY2_ACT_LED ((uint64)1 << (EPHY2_ACT_LED << 1))
#define PINMUX_EPHY3_ACT_LED ((uint64)1 << (EPHY3_ACT_LED << 1))
uint32 PinMuxSelOther; /* 24 */
#define SEL_SPI2 8
#define PINMUX_SEL_SPI2_MASK (3 << SEL_SPI2)
#define PINMUX_SEL_SPI2 (2 << SEL_SPI2)
#define SEL_USB 12
#define PINMUX_SEL_USB_MASK (3 << SEL_USB)
#define PINMUX_SEL_USB_HOST (1 << SEL_USB)
#define PINMUX_SEL_USB_DEV (2 << SEL_USB)
uint32 TestControl; /* 28 */
uint32 unused2; /* 2C */
uint32 RoboSWLEDControl; /* 30 */
uint32 RoboSWLEDLSR; /* 34 */
uint32 unused3; /* 38 */
uint32 RoboswEphyCtrl; /* 3C */
#define EPHY_AUTO_PWR_DOWN_EN (1<<29)
#define EPHY_IDDQ_FROM_PHY (1<<28)
#define EPHY_PLL_LOCK (1<<27)
#define EPHY_ATEST_25MHZ_EN (1<<26)
#define EPHY_PWR_DOWN_DLL (1<<25)
#define EPHY_PWR_DOWN_BIAS (1<<24)
#define EPHY_PWR_DOWN_TX_4 (1<<23)
#define EPHY_PWR_DOWN_TX_3 (1<<22)
#define EPHY_PWR_DOWN_TX_2 (1<<21)
#define EPHY_PWR_DOWN_TX_1 (1<<20)
#define EPHY_PWR_DOWN_RX_4 (1<<19)
#define EPHY_PWR_DOWN_RX_3 (1<<18)
#define EPHY_PWR_DOWN_RX_2 (1<<17)
#define EPHY_PWR_DOWN_RX_1 (1<<16)
#define EPHY_PWR_DOWN_SD_4 (1<<15)
#define EPHY_PWR_DOWN_SD_3 (1<<14)
#define EPHY_PWR_DOWN_SD_2 (1<<13)
#define EPHY_PWR_DOWN_SD_1 (1<<12)
#define EPHY_PWR_DOWN_RD_4 (1<<11)
#define EPHY_PWR_DOWN_RD_3 (1<<10)
#define EPHY_PWR_DOWN_RD_2 (1<<9)
#define EPHY_PWR_DOWN_RD_1 (1<<8)
#define EPHY_PWR_DOWN_4 (1<<7)
#define EPHY_PWR_DOWN_3 (1<<6)
#define EPHY_PWR_DOWN_2 (1<<5)
#define EPHY_PWR_DOWN_1 (1<<4)
#define EPHY_RST_4 (1<<3)
#define EPHY_RST_3 (1<<2)
#define EPHY_RST_2 (1<<1)
#define EPHY_RST_1 (1<<0)
#define EPHY_RST_SHIFT 0x0
#define EPHY_RST_MASK (0xf<<EPHY_RST_SHIFT)
uint32 RoboswSwitchCtrl; /* 40 */
#define RSW_SPI_MODE (1<<11)
#define RSW_BC_SUPP_EN (1<<10)
#define RSW_CLK_FREQ_MASK (3<<8)
#define RSW_ENF_DFX_FLOW (1<<7)
#define RSW_ENH_DFX_FLOW (1<<6)
#define RSW_GRX_0_SETUP (1<<5)
#define RSW_GTX_0_SETUP (1<<4)
#define RSW_HW_FWDG_EN (1<<3)
#define RSW_QOS_EN (1<<2)
#define RSW_WD_CLR_EN (1<<1)
#define RSW_MII_DUMB_FWDG_EN (1<<0)
uint32 RegFileTmCtl; /* 44 */
uint32 RingOscCtrl0; /* 48 */
#define RING_OSC_256_CYCLES 8
#define RING_OSC_512_CYCLES 9
#define RING_OSC_1024_CYCLES 10
uint32 RingOscCtrl1; /* 4C */
#define RING_OSC_ENABLE_MASK (0x0f<<24)
#define RING_OSC_ENABLE_SHIFT 24
#define RING_OSC_MAX 4
#define RING_OSC_COUNT_RESET (0x1<<23)
#define RING_OSC_SELECT_MASK (0x7<<20)
#define RING_OSC_SELECT_SHIFT 20
#define RING_OSC_IRQ (0x1<<18)
#define RING_OSC_COUNTER_OVERFLOW (0x1<<17)
#define RING_OSC_COUNTER_BUSY (0x1<<16)
#define RING_OSC_COUNT_MASK 0x0000ffff
uint32 unused4[6]; /* 50 - 64 */
uint32 DieRevID; /* 68 */
uint32 unused5; /* 6c */
uint32 DiagSelControl; /* 70 */
uint32 DiagReadBack; /* 74 */
uint32 DiagReadBackHi; /* 78 */
uint32 DiagMiscControl; /* 7c */
} GpioControl;
#pragma pack(pop)
#define GPIO ((volatile GpioControl * const) GPIO_BASE)
/* Number to mask conversion macro used for GPIODir and GPIOio */
#define GPIO_NUM_MAX 32
#define GPIO_NUM_TO_MASK(X) ( (((X) & BP_GPIO_NUM_MASK) < GPIO_NUM_MAX) ? (1 << ((X) & BP_GPIO_NUM_MASK)) : (0) )
/*
** High-Speed SPI Controller
*/
#define __mask(end, start) (((1 << ((end - start) + 1)) - 1) << start)
typedef struct HsSpiControl {
uint32 hs_spiGlobalCtrl; // 0x0000
#define HS_SPI_MOSI_IDLE (1 << 18)
#define HS_SPI_CLK_POLARITY (1 << 17)
#define HS_SPI_CLK_GATE_SSOFF (1 << 16)
#define HS_SPI_PLL_CLK_CTRL (8)
#define HS_SPI_PLL_CLK_CTRL_MASK __mask(15, HS_SPI_PLL_CLK_CTRL)
#define HS_SPI_SS_POLARITY (0)
#define HS_SPI_SS_POLARITY_MASK __mask(7, HS_SPI_SS_POLARITY)
uint32 hs_spiExtTrigCtrl; // 0x0004
#define HS_SPI_TRIG_RAW_STATE (24)
#define HS_SPI_TRIG_RAW_STATE_MASK __mask(31, HS_SPI_TRIG_RAW_STATE)
#define HS_SPI_TRIG_LATCHED (16)
#define HS_SPI_TRIG_LATCHED_MASK __mask(23, HS_SPI_TRIG_LATCHED)
#define HS_SPI_TRIG_SENSE (8)
#define HS_SPI_TRIG_SENSE_MASK __mask(15, HS_SPI_TRIG_SENSE)
#define HS_SPI_TRIG_TYPE (0)
#define HS_SPI_TRIG_TYPE_MASK __mask(7, HS_SPI_TRIG_TYPE)
#define HS_SPI_TRIG_TYPE_EDGE (0)
#define HS_SPI_TRIG_TYPE_LEVEL (1)
uint32 hs_spiIntStatus; // 0x0008
#define HS_SPI_IRQ_PING1_USER (28)
#define HS_SPI_IRQ_PING1_USER_MASK __mask(31, HS_SPI_IRQ_PING1_USER)
#define HS_SPI_IRQ_PING0_USER (24)
#define HS_SPI_IRQ_PING0_USER_MASK __mask(27, HS_SPI_IRQ_PING0_USER)
#define HS_SPI_IRQ_PING1_CTRL_INV (1 << 12)
#define HS_SPI_IRQ_PING1_POLL_TOUT (1 << 11)
#define HS_SPI_IRQ_PING1_TX_UNDER (1 << 10)
#define HS_SPI_IRQ_PING1_RX_OVER (1 << 9)
#define HS_SPI_IRQ_PING1_CMD_DONE (1 << 8)
#define HS_SPI_IRQ_PING0_CTRL_INV (1 << 4)
#define HS_SPI_IRQ_PING0_POLL_TOUT (1 << 3)
#define HS_SPI_IRQ_PING0_TX_UNDER (1 << 2)
#define HS_SPI_IRQ_PING0_RX_OVER (1 << 1)
#define HS_SPI_IRQ_PING0_CMD_DONE (1 << 0)
uint32 hs_spiIntStatusMasked; // 0x000C
#define HS_SPI_IRQSM__PING1_USER (28)
#define HS_SPI_IRQSM__PING1_USER_MASK __mask(31, HS_SPI_IRQSM__PING1_USER)
#define HS_SPI_IRQSM__PING0_USER (24)
#define HS_SPI_IRQSM__PING0_USER_MASK __mask(27, HS_SPI_IRQSM__PING0_USER)
#define HS_SPI_IRQSM__PING1_CTRL_INV (1 << 12)
#define HS_SPI_IRQSM__PING1_POLL_TOUT (1 << 11)
#define HS_SPI_IRQSM__PING1_TX_UNDER (1 << 10)
#define HS_SPI_IRQSM__PING1_RX_OVER (1 << 9)
#define HS_SPI_IRQSM__PING1_CMD_DONE (1 << 8)
#define HS_SPI_IRQSM__PING0_CTRL_INV (1 << 4)
#define HS_SPI_IRQSM__PING0_POLL_TOUT (1 << 3)
#define HS_SPI_IRQSM__PING0_TX_UNDER (1 << 2)
#define HS_SPI_IRQSM__PING0_RX_OVER (1 << 1)
#define HS_SPI_IRQSM__PING0_CMD_DONE (1 << 0)
uint32 hs_spiIntMask; // 0x0010
#define HS_SPI_IRQM_PING1_USER (28)
#define HS_SPI_IRQM_PING1_USER_MASK __mask(31, HS_SPI_IRQM_PING1_USER)
#define HS_SPI_IRQM_PING0_USER (24)
#define HS_SPI_IRQM_PING0_USER_MASK __mask(27, HS_SPI_IRQM_PING0_USER)
#define HS_SPI_IRQM_PING1_CTRL_INV (1 << 12)
#define HS_SPI_IRQM_PING1_POLL_TOUT (1 << 11)
#define HS_SPI_IRQM_PING1_TX_UNDER (1 << 10)
#define HS_SPI_IRQM_PING1_RX_OVER (1 << 9)
#define HS_SPI_IRQM_PING1_CMD_DONE (1 << 8)
#define HS_SPI_IRQM_PING0_CTRL_INV (1 << 4)
#define HS_SPI_IRQM_PING0_POLL_TOUT (1 << 3)
#define HS_SPI_IRQM_PING0_TX_UNDER (1 << 2)
#define HS_SPI_IRQM_PING0_RX_OVER (1 << 1)
#define HS_SPI_IRQM_PING0_CMD_DONE (1 << 0)
#define HS_SPI_INTR_CLEAR_ALL (0xFF001F1F)
uint32 hs_spiFlashCtrl; // 0x0014
#define HS_SPI_FCTRL_MB_ENABLE (23)
#define HS_SPI_FCTRL_SS_NUM (20)
#define HS_SPI_FCTRL_SS_NUM_MASK __mask(22, HS_SPI_FCTRL_SS_NUM)
#define HS_SPI_FCTRL_PROFILE_NUM (16)
#define HS_SPI_FCTRL_PROFILE_NUM_MASK __mask(18, HS_SPI_FCTRL_PROFILE_NUM)
#define HS_SPI_FCTRL_DUMMY_BYTES (10)
#define HS_SPI_FCTRL_DUMMY_BYTES_MASK __mask(11, HS_SPI_FCTRL_DUMMY_BYTES)
#define HS_SPI_FCTRL_ADDR_BYTES (8)
#define HS_SPI_FCTRL_ADDR_BYTES_MASK __mask(9, HS_SPI_FCTRL_ADDR_BYTES)
#define HS_SPI_FCTRL_ADDR_BYTES_2 (0)
#define HS_SPI_FCTRL_ADDR_BYTES_3 (1)
#define HS_SPI_FCTRL_ADDR_BYTES_4 (2)
#define HS_SPI_FCTRL_READ_OPCODE (0)
#define HS_SPI_FCTRL_READ_OPCODE_MASK __mask(7, HS_SPI_FCTRL_READ_OPCODE)
uint32 hs_spiFlashAddrBase; // 0x0018
char fill0[0x80 - 0x18];
uint32 hs_spiPP_0_Cmd; // 0x0080
#define HS_SPI_PP_SS_NUM (12)
#define HS_SPI_PP_SS_NUM_MASK __mask(14, HS_SPI_PP_SS_NUM)
#define HS_SPI_PP_PROFILE_NUM (8)
#define HS_SPI_PP_PROFILE_NUM_MASK __mask(10, HS_SPI_PP_PROFILE_NUM)
} HsSpiControl;
typedef struct HsSpiPingPong {
uint32 command;
#define HS_SPI_SS_NUM (12)
#define HS_SPI_PROFILE_NUM (8)
#define HS_SPI_TRIGGER_NUM (4)
#define HS_SPI_COMMAND_VALUE (0)
#define HS_SPI_COMMAND_NOOP (0)
#define HS_SPI_COMMAND_START_NOW (1)
#define HS_SPI_COMMAND_START_TRIGGER (2)
#define HS_SPI_COMMAND_HALT (3)
#define HS_SPI_COMMAND_FLUSH (4)
uint32 status;
#define HS_SPI_ERROR_BYTE_OFFSET (16)
#define HS_SPI_WAIT_FOR_TRIGGER (2)
#define HS_SPI_SOURCE_BUSY (1)
#define HS_SPI_SOURCE_GNT (0)
uint32 fifo_status;
uint32 control;
} HsSpiPingPong;
typedef struct HsSpiProfile {
uint32 clk_ctrl;
#define HS_SPI_ACCUM_RST_ON_LOOP (15)
#define HS_SPI_SPI_CLK_2X_SEL (14)
#define HS_SPI_FREQ_CTRL_WORD (0)
uint32 signal_ctrl;
#define HS_SPI_ASYNC_INPUT_PATH (1 << 16)
#define HS_SPI_LAUNCH_RISING (1 << 13)
#define HS_SPI_LATCH_RISING (1 << 12)
uint32 mode_ctrl;
#define HS_SPI_PREPENDBYTE_CNT (24)
#define HS_SPI_MODE_ONE_WIRE (20)
#define HS_SPI_MULTIDATA_WR_SIZE (18)
#define HS_SPI_MULTIDATA_RD_SIZE (16)
#define HS_SPI_MULTIDATA_WR_STRT (12)
#define HS_SPI_MULTIDATA_RD_STRT (8)
#define HS_SPI_FILLBYTE (0)
uint32 polling_config;
uint32 polling_and_mask;
uint32 polling_compare;
uint32 polling_timeout;
uint32 reserved;
} HsSpiProfile;
#define HS_SPI_OP_CODE 13
#define HS_SPI_OP_SLEEP (0)
#define HS_SPI_OP_READ_WRITE (1)
#define HS_SPI_OP_WRITE (2)
#define HS_SPI_OP_READ (3)
#define HS_SPI_OP_SETIRQ (4)
#define HS_SPI ((volatile HsSpiControl * const) HSSPIM_BASE)
#define HS_SPI_PINGPONG0 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0x80))
#define HS_SPI_PINGPONG1 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0xc0))
#define HS_SPI_PROFILES ((volatile HsSpiProfile * const) (HSSPIM_BASE+0x100))
#define HS_SPI_FIFO0 ((volatile uint8 * const) (HSSPIM_BASE+0x200))
#define HS_SPI_FIFO1 ((volatile uint8 * const) (HSSPIM_BASE+0x400))
/*
** Misc Register Set Definitions.
*/
typedef struct Misc {
uint32 miscSerdesCtrl; /* 0x0000 */
#define SERDES_PCIE_ENABLE 0x00000001
#define SERDES_PCIE_EXD_ENABLE (1<<15)
uint32 miscSerdesSts; /* 0x0004 */
uint32 miscIrqOutMask; /* 0x0008 */
#define MISC_PCIE_EP_IRQ_MASK0 (1<<0)
#define MISC_PCIE_EP_IRQ_MASK1 (1<<1)
uint32 miscMemcControl; /* 0x000c */
#define MISC_MEMC_CONTROL_MC_UBUS_ASYNC_MODE (1<<3)
#define MISC_MEMC_CONTROL_MC_LMB_ASYNC_MODE (1<<2)
#define MISC_MEMC_CONTROL_DDR_TEST_DONE (1<<1)
#define MISC_MEMC_CONTROL_DDR_TEST_DISABLE (1<<0)
uint32 unused0[2]; /* 0x0010 */
uint32 miscVregCtrl0; /* 0x0018 */
#define VREG_VSEL1P2_SHIFT 0
#define VREG_VSEL1P2_MASK 0x1f
#define VREG_VSEL1P2_MIDDLE 0x0f
uint32 miscVregCtrl1; /* 0x001c */
uint32 miscVregCtrl2; /* 0x0020 */
uint32 miscLedXorReg; /* 0x0024 */
uint32 miscExtra2ChipIrqMask; /* 0x0028 */
uint32 miscExtra2ChipIrqStatus; /* 0x002c */
uint32 miscExtra2ChipIrqMask1; /* 0x0030 */
uint32 miscExtra2ChipIrqStatus1; /* 0x0034 */
uint32 miscDdrPllTestCtrl; /* 0x0038 */
uint32 miscPadCtrlLow; /* 0x003c */
uint32 miscPadCtrlHigh; /* 0x0040 */
#define MISC_MII_SEL_SHIFT 30
#define MISC_MII_SEL_3P3V 0
#define MISC_MII_SEL_2P5V 1
#define MISC_MII_SEL_1P5V 2
uint32 miscPeriphEcoReg; /* 0x0044 */
uint32 miscIddqCtrl; /* 0x0048 */
#define MISC_IDDQ_CTRL_EPHY (1<<9)
#define MISC_IDDQ_CTRL_ROBOSW (1<<8)
#define MISC_IDDQ_CTRL_PCIE (1<<7)
#define MISC_IDDQ_CTRL_USBH (1<<6)
#define MISC_IDDQ_CTRL_USBD (1<<5)
#define MISC_IDDQ_CTRL_PCM (1<<4)
#define MISC_IDDQ_CTRL_SAR (1<<3)
#define MISC_IDDQ_CTRL_ADSL2_AFE (1<<2)
#define MISC_IDDQ_CTRL_ADSL2_PHY (1<<1)
#define MISC_IDDQ_CTRL_ADSL2_MIPS (1<<0)
uint32 miscAdslClkSample; /* 0x004c */
uint32 unused3[(0x0100 - 0x0050) / 4]; /* 0x0050 */
uint32 miscAdslCtrl; /* 0x0100 */
uint32 unused4[(0x0180 - 0x0104) / 4]; /* 0x0104 */
uint32 miscMipsTestCtrl; /* 0x0180 */
uint32 miscMipsTestStatus; /* 0x0184 */
uint32 unused5[(0x0200 - 0x0188) / 4]; /* 0x0188 */
uint32 miscPllCtrlSysPll0; /* 0x0200 */
uint32 miscPllCtrlSysPll1; /* 0x0204 */
uint32 miscPllCtrlSysPll2; /* 0x0208 */
uint32 miscPllCtrlSysPll3; /* 0x020c */
uint32 miscPllCtrlDdrPll; /* 0x0210 */
uint32 miscPllCtrlXtalEcoReg; /* 0x0214 */
uint32 unused6[(0x0240 - 0x0218) / 4]; /* 0x0218 */
uint32 miscStrapBus; /* 0x0240 */
#define MISC_STRAP_BUS_BOOT_SEL_SHIFT 18
#define MISC_STRAP_BUS_BOOT_SEL_MASK (0x1<<MISC_STRAP_BUS_BOOT_SEL_SHIFT)
#define MISC_STRAP_BUS_BOOT_SERIAL 0x01
#define MISC_STRAP_BUS_BOOT_NAND 0x00
#define MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT 7
#define MISC_STRAP_BUS_MIPS_PLL_FVCO_MASK (0x1F<<MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT)
#define MISC_STRAP_BUS_HS_SPIM_FAST_B_MASK (1<<4)
uint32 miscStrapOverride; /* 0x0244 */
uint32 unused7[(0x0280 - 0x0248) / 4]; /* 0x0248 */
uint32 miscRtcSleepModeEn; /* 0x0280 */
uint32 miscRtcSleepRtcEn; /* 0x0284 */
uint32 miscRtcSleepRtcCountLow; /* 0x0288 */
uint32 miscRtcSleepRtcCountHigh; /* 0x028c */
uint32 miscRtcSleepRtcEvent; /* 0x0290 */
uint32 miscRtcSleepWakeupMask; /* 0x0294 */
uint32 miscRtcSleepWakeupStatus; /* 0x0298 */
uint32 miscRtcSleepDebounceCtrl; /* 0x029c */
uint32 miscRtcSleepCpuScratchPad; /* 0x02a0 */
} Misc;
#define MISC ((volatile Misc * const) MISC_BASE)
/*
** LedControl Register Set Definitions.
*/
#pragma pack(push, 4)
typedef struct LedControl {
uint32 ledInit;
#define LED_LED_TEST (1 << 31)
#define LED_SHIFT_TEST (1 << 30)
#define LED_SERIAL_LED_SHIFT_DIR (1 << 16)
#define LED_SERIAL_LED_DATA_PPOL (1 << 15)
#define LEDSERIAL_LED_CLK_NPOL (1 << 14)
#define LED_SERIAL_LED_MUX_SEL (1 << 13)
#define LED_SERIAL_LED_EN (1 << 12)
#define LED_FAST_INTV_SHIFT 6
#define LED_FAST_INTV_MASK (0x3F<<LED_FAST_INTV_SHIFT)
#define LED_SLOW_INTV_SHIFT 0
#define LED_SLOW_INTV_MASK (0x3F<<LED_SLOW_INTV_SHIFT)
#define LED_INTERVAL_20MS 1
uint64 ledMode;
#define LED_MODE_MASK (uint64)0x3
#define LED_MODE_OFF (uint64)0x0
#define LED_MODE_FLASH (uint64)0x1
#define LED_MODE_BLINK (uint64)0x2
#define LED_MODE_ON (uint64)0x3
uint32 ledHWDis;
#define LED_INET_ACT 0
uint32 ledStrobe;
uint32 ledLinkActSelHigh;
#define LED_4_ACT_SHIFT 0
#define LED_5_ACT_SHIFT 4
#define LED_6_ACT_SHIFT 8
#define LED_7_ACT_SHIFT 12
#define LED_4_LINK_SHIFT 16
#define LED_5_LINK_SHIFT 20
#define LED_6_LINK_SHIFT 24
#define LED_7_LINK_SHIFT 28
uint32 ledLinkActSelLow;
#define LED_0_ACT_SHIFT 0
#define LED_1_ACT_SHIFT 4
#define LED_2_ACT_SHIFT 8
#define LED_3_ACT_SHIFT 12
#define LED_0_LINK_SHIFT 16
#define LED_1_LINK_SHIFT 20
#define LED_2_LINK_SHIFT 24
#define LED_3_LINK_SHIFT 28
uint32 ledReadback;
uint32 ledSerialMuxSelect;
} LedControl;
#pragma pack(pop)
#define LED ((volatile LedControl * const) LED_BASE)
#define GPIO_NUM_TO_LED_MODE_SHIFT(X) \
((((X) & BP_GPIO_NUM_MASK) < 8) ? (32 + (((X) & BP_GPIO_NUM_MASK) << 1)) : \
((((X) & BP_GPIO_NUM_MASK) - 8) << 1))
#define IUDMA_MAX_CHANNELS 32
/*
** DMA Channel Configuration (1 .. 32)
*/
typedef struct DmaChannelCfg {
uint32 cfg; /* (00) assorted configuration */
#define DMA_ENABLE 0x00000001 /* set to enable channel */
#define DMA_PKT_HALT 0x00000002 /* idle after an EOP flag is detected */
#define DMA_BURST_HALT 0x00000004 /* idle after finish current memory burst */
uint32 intStat; /* (04) interrupts control and status */
uint32 intMask; /* (08) interrupts mask */
#define DMA_BUFF_DONE 0x00000001 /* buffer done */
#define DMA_DONE 0x00000002 /* packet xfer complete */
#define DMA_NO_DESC 0x00000004 /* no valid descriptors */
uint32 maxBurst; /* (0C) max burst length permitted */
#define DMA_DESCSIZE_SEL 0x00040000 /* DMA Descriptor Size Selection */
} DmaChannelCfg;
/*
** DMA State RAM (1 .. 16)
*/
typedef struct DmaStateRam {
uint32 baseDescPtr; /* (00) descriptor ring start address */
uint32 state_data; /* (04) state/bytes done/ring offset */
uint32 desc_len_status; /* (08) buffer descriptor status and len */
uint32 desc_base_bufptr; /* (0C) buffer descrpitor current processing */
} DmaStateRam;
/*
** DMA Registers
*/
typedef struct DmaRegs {
uint32 controller_cfg; /* (00) controller configuration */
#define DMA_MASTER_EN 0x00000001
#define DMA_FLOWC_CH1_EN 0x00000002
#define DMA_FLOWC_CH3_EN 0x00000004
// Flow control Ch1
uint32 flowctl_ch1_thresh_lo; /* 004 */
uint32 flowctl_ch1_thresh_hi; /* 008 */
uint32 flowctl_ch1_alloc; /* 00c */
#define DMA_BUF_ALLOC_FORCE 0x80000000
// Flow control Ch3
uint32 flowctl_ch3_thresh_lo; /* 010 */
uint32 flowctl_ch3_thresh_hi; /* 014 */
uint32 flowctl_ch3_alloc; /* 018 */
// Flow control Ch5
uint32 flowctl_ch5_thresh_lo; /* 01C */
uint32 flowctl_ch5_thresh_hi; /* 020 */
uint32 flowctl_ch5_alloc; /* 024 */
// Flow control Ch7
uint32 flowctl_ch7_thresh_lo; /* 028 */
uint32 flowctl_ch7_thresh_hi; /* 02C */
uint32 flowctl_ch7_alloc; /* 030 */
uint32 ctrl_channel_reset; /* 034 */
uint32 ctrl_channel_debug; /* 038 */
uint32 reserved1; /* 03C */
uint32 ctrl_global_interrupt_status; /* 040 */
uint32 ctrl_global_interrupt_mask; /* 044 */
// Unused words
uint8 reserved2[0x200-0x48];
// Per channel registers/state ram
DmaChannelCfg chcfg[IUDMA_MAX_CHANNELS];/* (200-3FF) Channel configuration */
union {
DmaStateRam s[IUDMA_MAX_CHANNELS];
uint32 u32[4 * IUDMA_MAX_CHANNELS];
} stram; /* (400-5FF) state ram */
} DmaRegs;
#define SW_DMA ((volatile DmaRegs * const) SWITCH_DMA_BASE)
/*
** DMA Buffer
*/
typedef struct DmaDesc {
union {
struct {
uint16 length; /* in bytes of data in buffer */
#define DMA_DESC_USEFPM 0x8000
#define DMA_DESC_MULTICAST 0x4000
#define DMA_DESC_BUFLENGTH 0x0fff
uint16 status; /* buffer status */
#define DMA_OWN 0x8000 /* cleared by DMA, set by SW */
#define DMA_EOP 0x4000 /* last buffer in packet */
#define DMA_SOP 0x2000 /* first buffer in packet */
#define DMA_WRAP 0x1000 /* */
#define DMA_PRIO 0x0C00 /* Prio for Tx */
#define DMA_APPEND_BRCM_TAG 0x0200
#define DMA_APPEND_CRC 0x0100
#define USB_ZERO_PKT (1<< 0) // Set to send zero length packet
};
uint32 word0;
};
uint32 address; /* address of data */
} DmaDesc;
/*
** 16 Byte DMA Buffer
*/
typedef struct {
union {
struct {
uint16 length; /* in bytes of data in buffer */
#define DMA_DESC_USEFPM 0x8000
#define DMA_DESC_MULTICAST 0x4000
#define DMA_DESC_BUFLENGTH 0x0fff
uint16 status; /* buffer status */
#define DMA_OWN 0x8000 /* cleared by DMA, set by SW */
#define DMA_EOP 0x4000 /* last buffer in packet */
#define DMA_SOP 0x2000 /* first buffer in packet */
#define DMA_WRAP 0x1000 /* */
#define DMA_PRIO 0x0C00 /* Prio for Tx */
#define DMA_APPEND_BRCM_TAG 0x0200
#define DMA_APPEND_CRC 0x0100
#define USB_ZERO_PKT (1<< 0) // Set to send zero length packet
};
uint32 word0;
};
uint32 address; /* address of data */
uint32 control;
#define GEM_ID_MASK 0x001F
uint32 reserved;
} DmaDesc16;
typedef struct USBControl {
uint32 BrtControl1;