There are several rules that enforce alignment for a group of lines based on the keywords such as 'after', '<=' etc. Some of the configurations are available in all keyword alignment rules, while others are rule specific.
There are several options to these rules:
Note
Some options are rule dependent.
Option | Values | Default | Description |
---|---|---|---|
compact_alignment |
yes , no |
yes |
|
blank_line_ends_group |
yes , no |
yes |
|
comment_line_ends_group |
yes , no |
yes |
|
separate_generic_port_alignment |
yes , no |
yes |
|
if_control_statements_ends_group |
yes , no |
yes |
|
case_control_statements_ends_group |
yes , no , break_on_case_or_end_case |
yes |
|
generate_statements_ends_group |
yes , no |
yes |
|
loop_control_generic_port_alignment |
yes , no |
yes |
|
include_type_is_keyword |
yes , no |
no |
|
This is an example of how to configure these options.
rule :
process_031:
compact_alignment: 'yes'
blank_line_ends_group: 'yes'
comment_line_ends_group : 'yes'
separate_generic_port_alignment: 'yes'
if_control_statements_ends_group: 'yes'
case_control_statements_ends_group: 'yes'
generate_statements_ends_group: 'yes'
loop_control_statements_ends_group: 'yes'
include_type_is_keyword: 'no'
Enforces single space before alignment keyword in the line with the longest part before the keyword.
Violation
signal sig_short : std_logic; signal sig_very_long : std_logic;Fix
signal sig_short : std_logic; signal sig_very_long : std_logic;
Aligns to right most instance of keyword.
Violation
signal sig_short : std_logic; signal sig_very_long : std_logic;Fix
signal sig_short : std_logic; signal sig_very_long : std_logic;
Any blank line encountered in the VHDL file ends the group of lines that should be aligned and starts new group.
Violation
signal wr_en : std_logic; signal rd_en : std_logic; constant c_short_period : time; constant c_long_period : time;Fix
signal wr_en : std_logic; signal rd_en : std_logic; constant c_short_period : time; constant c_long_period : time;
Any blank line encountered in the VHDL file will not end the group of lines that should be aligned.
Violation
signal wr_en : std_logic; signal rd_en : std_logic; constant c_short_period : time; constant c_long_period : time;Fix
signal wr_en : std_logic; signal rd_en : std_logic; constant c_short_period : time; constant c_long_period : time;
Any comment line in the VHDL file ends the group of lines that should be aligned and starts new group.
Violation
port ( sclk_i : in std_logic; pclk_i : in std_logic; rst_i : in std_logic; ---- serial interface ---- spi_ssel_o : out std_logic; spi_sck_o : out std_logic; spi_mosi_o : out std_logic; spi_miso_i : in std_logic );Fix
port ( sclk_i : in std_logic; pclk_i : in std_logic; rst_i : in std_logic; ---- serial interface ---- spi_ssel_o : out std_logic; spi_sck_o : out std_logic; spi_mosi_o : out std_logic; spi_miso_i : in std_logic );
Any comment line in the VHDL file will not end the group of lines that should be aligned and starts new group.
Violation
port ( sclk_i : in std_logic; pclk_i : in std_logic; rst_i : in std_logic; ---- serial interface ---- spi_ssel_o : out std_logic; spi_sck_o : out std_logic; spi_mosi_o : out std_logic; spi_miso_i : in std_logic );Fix
port ( sclk_i : in std_logic; pclk_i : in std_logic; rst_i : in std_logic; ---- serial interface ---- spi_ssel_o : out std_logic; spi_sck_o : out std_logic; spi_mosi_o : out std_logic; spi_miso_i : in std_logic );
Alignment within the generic declarative/mapping part is separated from alignment within the port declarative/mapping part.
Violation
generic ( g_width : positive; g_output_delay : positive ); port ( clk_i : in std_logic; data_i : in std_logic; data_o : in std_logic );Fix
generic ( g_width : positive; g_output_delay : positive ); port ( clk_i : in std_logic; data_i : in std_logic; data_o : in std_logic );
Alignment within the generic declarative/mapping part is the same as the alignment within the port declarative/mapping part.
Violation
generic ( g_width : positive; g_output_delay : positive ); port ( clk_i : in std_logic; data_i : in std_logic; data_o : in std_logic );Fix
generic ( g_width : positive; g_output_delay : positive ); port ( clk_i : in std_logic; data_i : in std_logic; data_o : in std_logic );
Any line with if control statement ends the group of lines that should be aligned and starts new group.
Violation
if condition = '1' then data_valid <= '1'; data <= '1'; else data_valid <= '0'; hold_transmission <= '1'; end if;Fix
if condition = '1' then data_valid <= '1'; data <= '1'; else data_valid <= '0'; hold_transmission <= '1'; end if;
Any line with if control statement does not end the group of lines that should be aligned and starts new group.
Violation
if condition = '1' then data_valid <= '1'; data <= '1'; else data_valid <= '0'; hold_transmission <= '1'; end if;Fix
if condition = '1' then data_valid <= '1'; data <= '1'; else data_valid <= '0'; hold_transmission <= '1'; end if;
Any line with case control statements (case
, when
or end case
) ends the group of lines that should be aligned and starts new group.
Violation
data_valid_before <= '1'; case A is when A => X <= F; XY <= G; XYZ <= H; when B => a <= I; ab <= h; c <= a; when others => null; end case; data_valid_after <= '1';Fix
data_valid_before <= '1'; case A is when A => X <= F; XY <= G; XYZ <= H; when B => a <= I; ab <= h; c <= a; when others => null; end case; data_valid_after <= '1';
No line with case control statements ends the group of lines that should be aligned and starts a group.
Violation
data_valid_before <= '1'; case A is when A => X <= F; XY <= G; XYZ <= H; when B => a <= I; ab <= h; c <= a; when others => null; end case; data_valid_after <= '1';Fix
data_valid_before <= '1'; case A is when A => X <= F; XY <= G; XYZ <= H; when B => a <= I; ab <= h; c <= a; when others => null; end case; data_valid_after <= '1';
Any line with case
or end case
ends the group of lines that should be aligned and starts new group.
Violation
data_valid_before <= '1'; case A is when A => X <= F; XY <= G; XYZ <= H; when B => a <= I; ab <= h; c <= a; when others => null; end case; data_valid_after <= '1';Fix
data_valid_before <= '1'; case A is when A => X <= F; XY <= G; XYZ <= H; when B => a <= I; ab <= h; c <= a; when others => null; end case; data_valid_after <= '1';
Any line with generate statement keywords ends the group of lines that should be aligned and starts new group.
Violation
data_valid_before <= '1'; generate_label : if G_ENABLE = '1' generate data_valid <= '0'; hold_transmission <= '1'; end generate; data_valid_after <= '1';Fix
data_valid_before <= '1'; generate_label : if G_ENABLE = '1' generate data_valid <= '0'; hold_transmission <= '1'; end generate; data_valid_after <= '1';
No line with generate statement keywords ends the group of lines that should be aligned and starts new group.
Violation
data_valid_before <= '1'; generate_label : if G_ENABLE = '1' generate data_valid <= '0'; hold_transmission <= '1'; end generate; data_valid_after <= '1';Fix
data_valid_before <= '1'; generate_label : if G_ENABLE = '1' generate data_valid <= '0'; hold_transmission <= '1'; end generate; data_valid_after <= '1';
Any line with loop control statement (including for and while loops) ends the group of lines that should be aligned and starts new group.
Violation
data_valid_before <= '1'; for index in 4 to 23 loop data_valid <= '0'; hold_transmission <= '1'; end loop; data_valid_after <= '1';Fix
data_valid_before <= '1'; for index in 4 to 23 loop data_valid <= '0'; hold_transmission <= '1'; end loop; data_valid_after <= '1';
No line with loop control statement (including for and while loops) ends the group of lines that should be aligned and starts new group.
Violation
data_valid_before <= '1'; for index in 4 to 23 loop data_valid <= '0'; hold_transmission <= '1'; end loop; data_valid_after <= '1';Fix
data_valid_before <= '1'; for index in 4 to 23 loop data_valid <= '0'; hold_transmission <= '1'; end loop; data_valid_after <= '1';
Any blank line encountered in the VHDL file ends the group of lines that should be aligned and starts new group.
Violation
signal wr_en : std_logic; signal rd_en : std_logic; type sm is (idle, read, write); constant c_short_period : time; constant c_long_period : time;Fix
signal wr_en : std_logic; signal rd_en : std_logic; type sm is (idle, read, write); constant c_short_period : time; constant c_long_period : time;
Any blank line encountered in the VHDL file will not end the group of lines that should be aligned.
Violation
signal wr_en : std_logic; signal rd_en : std_logic; type sm is (idle, read, write); constant c_short_period : time; constant c_long_period : time;Fix
signal wr_en : std_logic; signal rd_en : std_logic; type sm is (idle, read, write); constant c_short_period : time; constant c_long_period : time;
- after_002
- architecture_026
- architecture_027
- architecture_400
- block_401
- block_402
- case_generate_statement_400
- component_017
- component_020
- concurrent_006
- concurrent_008
- concurrent_400
- constant_400
- declarative_part_400
- entity_017
- entity_018
- entity_020
- function_012
- generate_401
- generate_403
- generate_405
- instantiation_010
- instantiation_029
- package_400
- package_401
- package_402
- package_body_401
- package_body_402
- procedure_401
- procedure_410
- procedure_411
- procedure_call_401
- process_031
- process_033
- process_034
- process_035
- process_400
- process_401
- sequential_400
- subprogram_body_400
- subprogram_body_401
- type_400