/
.travis.yml
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/
.travis.yml
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git:
submodules: true
language: scala
sudo: required
cache:
timeout: 3000
apt: true
directories:
$HOME/.ivy2
regression/install
ivlsim/iverilog
verisim/verilator
# packages needed to build riscv-tools
addons:
apt:
sources:
- ubuntu-toolchain-r-test
packages:
- gcc-4.8
- g++-4.8
- gperf
- autoconf
- automake
- autotools-dev
- libmpc-dev
- libmpfr-dev
- libgmp-dev
- gawk
- build-essential
- bison
- flex
- texinfo
- device-tree-compiler
- libusb-1.0-0-dev
- python-pexpect
# These branches are the only ones that
# will build when "build branch updates"
# is set in settings (branches which PR against
# them are still built). With this set,
# the above blacklist is not useful.
# Adding this allows us to keep "Build Branch Updates"
# set to 'ON'.
branches:
only:
- master
- rocketchip-bump
- travis
jobs:
include:
# - stage: prepare cache-riscv-tools
# before_install:
# - export CXX=g++-4.8 CC=gcc-4.8
# - export MAKEFLAGS='-j2'
# install:
# - travis_wait
# script:
# - travis_wait 120 make tools -C regression SUITE=none
# before_cache:
# - ls -t regression/install | tail -n+2 | sed s@^@regression/install/@ | xargs rm -rf
# - stage: prepare cache-toolchain
# before_install:
# - export CXX=g++-4.8 CC=gcc-4.8
# - export MAKEFLAGS='-j3'
# script:
# - travis_wait 100 make toolchain -C regression SUITE=none
- stage: prepare cache-misc-tools
before_install:
- export CXX=g++-4.8 CC=gcc-4.8
script:
- travis_wait 50 make openocd -C regression SUITE=none
- travis_wait 50 make spike -C regression SUITE=none
#FIXME: - travis_wait 50 make pk -C regression SUITE=none
#FIXME: - travis_wait 50 make tests -C regression SUITE=none
- travis_wait 10 date > regression/install/install.stamp
before_cache:
- ls -t regression/install | tail -n+2 | sed s@^@regression/install/@ | xargs rm -rf
- stage: prepare cache-verilator
script:
- travis_wait 50 make verilator -C verisim
before_install:
- export CXX=g++-4.8 CC=gcc-4.8
- stage: prepare cache-ivlsim
script:
- travis_wait 50 make iverilog -C ivlsim
before_install:
- export CXX=g++-4.8 CC=gcc-4.8
- &test
stage: Test
script:
# Emulation / Synthesis
- travis_wait 20 make -f Makefile.examplefpga verilog
- travis_wait 20 make -f Makefile.asic verilog
- <<: *test
script:
# Check RTL generation only
- travis_wait 20 make -C regression SUITE=examplefpgaA verisim-verilog
- travis_wait 20 make -C regression SUITE=examplefpgaA ivlsim-verilog
- travis_wait 20 make -C regression SUITE=examplefpgaB verisim-verilog
- travis_wait 20 make -C regression SUITE=examplefpgaB ivlsim-verilog