/
common.mk
138 lines (114 loc) · 3.78 KB
/
common.mk
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# See LICENSE for license details.
# Required variables:
# - MODEL
# - PROJECT
# - CONFIG_PROJECT
# - CONFIG
# - BUILD_DIR
# - FPGA_DIR
# - FLOW_TYPE
#
# Optional variables:
# - EXTRA_FPGA_VSRCS
# export to bootloader
export ROMCONF=$(BUILD_DIR)/$(PROJECT).$(MODEL).$(CONFIG).rom.conf
# export to fpga-shells
export FPGA_TOP_SYSTEM=$(MODEL)
export FPGA_BUILD_DIR=$(BUILD_DIR)/$(FPGA_TOP_SYSTEM)
export fpga_common_script_dir=$(FPGA_DIR)/common/tcl
export fpga_board_script_dir=$(FPGA_DIR)/$(BOARD)/tcl
export BUILD_DIR
EXTRA_FPGA_VSRCS ?=
PATCHVERILOG ?= ""
BOOTROM_DIR ?= ""
FLOW_TYPE ?= "FPGA"
base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
export rocketchip_dir := $(base_dir)/rocket-chip
SBT ?= java -jar $(rocketchip_dir)/sbt-launch.jar ++2.12.4
# Build firrtl.jar and put it where chisel3 can find it.
ROCKET_CLASSES ?= "$(rocketchip_dir)/target/scala-2.12/classes:$(rocketchip_dir)/chisel3/target/scala-2.12/*"
FIRRTL_JAR ?= $(rocketchip_dir)/firrtl/utils/bin/firrtl.jar
FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp "$(FIRRTL_JAR)":"$(ROCKET_CLASSES)" firrtl.Driver
$(FIRRTL_JAR): $(shell find $(rocketchip_dir)/firrtl/src/main/scala -iname "*.scala")
$(MAKE) -C $(rocketchip_dir)/firrtl SBT="$(SBT)" root_dir=$(rocketchip_dir)/firrtl build-scala
touch $(FIRRTL_JAR)
mkdir -p $(rocketchip_dir)/lib
cp -p $(FIRRTL_JAR) $(rocketchip_dir)/lib
mkdir -p $(rocketchip_dir)/chisel3/lib
cp -p $(FIRRTL_JAR) $(rocketchip_dir)/chisel3/lib
# Build .fir
firrtl := $(BUILD_DIR)/$(PROJECT).$(MODEL).$(CONFIG).fir
$(firrtl): $(shell find $(base_dir)/src/main/scala -name '*.scala') $(FIRRTL_JAR)
mkdir -p $(dir $@)
ifeq ($(FLOW_TYPE), ASIC)
$(SBT) "runMain $(PROJECT).ASICGenerator $(BUILD_DIR) $(PROJECT) $(MODEL) $(CONFIG_PROJECT) $(CONFIG)"
else
$(SBT) "runMain $(PROJECT).FPGAGenerator $(BUILD_DIR) $(PROJECT) $(MODEL) $(CONFIG_PROJECT) $(CONFIG)"
endif
.PHONY: firrtl
firrtl: $(firrtl)
# Build verilog
verilog := $(BUILD_DIR)/$(PROJECT).$(MODEL).$(CONFIG).v
MEM_GEN ?= $(rocketchip_dir)/scripts/vlsi_mem_gen
$(verilog): $(firrtl) $(FIRRTL_JAR)
$(verilog):
ifeq ($(FLOW_TYPE), ASIC)
$(FIRRTL) -i $(firrtl) -o $@ -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$(verilog:.v=.conf) -faf $(verilog:.v=.anno.json) -td $(BUILD_DIR)/
cd $(BUILD_DIR) && \
rm -f $*.behav_srams.v && \
$(MEM_GEN) $(verilog:.v=.conf) >> $(verilog:.v=.tmp) && \
mv $(verilog:.v=.tmp) $(verilog:.v=.behav_srams.v)
else
$(FIRRTL) -i $(firrtl) -o $@ -X verilog
endif
ifneq ($(PATCHVERILOG),"")
$(PATCHVERILOG)
endif
.PHONY: verilog
verilog: $(verilog)
# Generate bootrom
romgen := $(BUILD_DIR)/$(PROJECT).$(MODEL).$(CONFIG).rom.v
$(romgen): $(verilog)
ifneq ($(BOOTROM_DIR),"")
$(MAKE) -C $(BOOTROM_DIR) romgen
mv $(BUILD_DIR)/rom.v $@
endif
.PHONY: romgen
romgen: $(romgen)
f := $(BUILD_DIR)/$(PROJECT).$(MODEL).$(CONFIG).vsrcs.F
$(f):
echo $(VSRCS) > $@
.PHONY: f
f:$(f)
bit := $(BUILD_DIR)/obj/$(MODEL).bit
$(bit): $(romgen) $(f)
cd $(BUILD_DIR); vivado \
-nojournal -mode batch \
-source $(fpga_common_script_dir)/vivado.tcl \
-tclargs \
-top-module "$(MODEL)" \
-F "$(f)" \
-ip-vivado-tcls "$(shell find '$(BUILD_DIR)' -name '*.vivado.tcl')" \
-board "$(BOARD)"
.PHONY: bit
bit: $(bit)
# Build .mcs
mcs := $(BUILD_DIR)/obj/$(MODEL).mcs
$(mcs): $(bit)
cd $(BUILD_DIR); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $<
.PHONY: mcs
mcs: $(mcs)
# Build Libero project
prjx := $(BUILD_DIR)/libero/$(MODEL).prjx
$(prjx): $(verilog)
cd $(BUILD_DIR); libero SCRIPT:$(fpga_common_script_dir)/libero.tcl SCRIPT_ARGS:"$(BUILD_DIR) $(MODEL) $(PROJECT) $(CONFIG) $(BOARD)"
.PHONY: prjx
prjx: $(prjx)
# Clean
.PHONY: clean
clean:
ifneq ($(BOOTROM_DIR),"")
$(MAKE) -C $(BOOTROM_DIR) clean
endif
$(MAKE) -C $(FPGA_DIR) clean
rm -rf $(BUILD_DIR)