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vunit_run_motor_control_simulator.py
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vunit_run_motor_control_simulator.py
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#!/usr/bin/env python3
from pathlib import Path
from vunit import VUnit
# ROOT
ROOT = Path(__file__).resolve().parent
VU = VUnit.from_argv()
mathlib = VU.add_library("math_library")
mathlib.add_source_files(ROOT / "source/system_clocks_pkg.vhd")
# mathlib.add_source_files(ROOT / "source/hVHDL_math_library/multiplier/multiplier_base_types_22bit_pkg.vhd")
mathlib.add_source_files(ROOT / "testbenches/multiplier_configuration_pkg.vhd")
mathlib.add_source_files(ROOT / "source/hVHDL_math_library/multiplier/multiplier_pkg.vhd")
mathlib.add_source_files(ROOT / "source/hVHDL_math_library/pi_controller/pi_controller_pkg.vhd")
mathlib.add_source_files(ROOT / "source/hVHDL_math_library/sincos/sincos_pkg.vhd")
mathlib.add_source_files(ROOT / "source/hVHDL_fpga_interconnect/interconnect_configuration/data_15_address_15_bit_pkg.vhd")
mathlib.add_source_files(ROOT / "source/hVHDL_fpga_interconnect/fpga_interconnect_pkg.vhd")
mathlib.add_source_files(ROOT / "source/hVHDL_math_library/coordinate_transforms/abc_to_ab_transform/abc_to_ab_transform_pkg.vhd")
mathlib.add_source_files(ROOT / "source/hVHDL_math_library/coordinate_transforms/abc_to_ab_transform/ab_to_abc_transform_pkg.vhd")
mathlib.add_source_files(ROOT / "source/hVHDL_math_library/coordinate_transforms/ab_to_dq_transform/dq_to_ab_transform_pkg.vhd")
mathlib.add_source_files(ROOT / "source/hVHDL_math_library/coordinate_transforms/ab_to_dq_transform/ab_to_dq_transform_pkg.vhd")
mathlib.add_source_files(ROOT / "source/hVHDL_dynamic_model_verification_library/state_variable/state_variable_pkg.vhd")
mathlib.add_source_files(ROOT / "source/hVHDL_dynamic_model_verification_library/ac_motor_models/pmsm_electrical_model_pkg.vhd")
mathlib.add_source_files(ROOT / "source/hVHDL_dynamic_model_verification_library/ac_motor_models/pmsm_mechanical_model_pkg.vhd")
mathlib.add_source_files(ROOT / "source/hVHDL_dynamic_model_verification_library/ac_motor_models/permanent_magnet_motor_model_pkg.vhd")
mathlib.add_source_files(ROOT / "source/hVHDL_dynamic_model_verification_library/ac_motor_models/field_oriented_motor_control/field_oriented_motor_control_pkg.vhd")
mathlib.add_source_files(ROOT / "source/system_control/motor_control_hardware/motor_control_data_processing/motor_control_data_processing_pkg.vhd")
mathlib.add_source_files(ROOT / "source/system_control/motor_control_hardware/motor_control_hardware_pkg.vhd")
mathlib.add_source_files(ROOT / "source/vhdl_motor_control_addresses_pkg.vhd")
mathlib.add_source_files(ROOT / "testbenches/motor_control_harware_tb.vhd")
mathlib.add_source_files(ROOT / "testbenches/test_sincos_tb.vhd")
lib = VU.add_library("memory")
lib.add_source_files(ROOT / "source/hVHDL_fpga_interconnect/interconnect_configuration/data_15_address_15_bit_pkg.vhd")
lib.add_source_files(ROOT / "source/hVHDL_fpga_interconnect/fpga_interconnect_pkg.vhd")
lib.add_source_files(ROOT / "source/hVHDL_memory_library/fpga_ram/ram_configuration/ram_configuration_16x1024_pkg.vhd")
lib.add_source_files(ROOT / "source/hVHDL_memory_library/fpga_ram" / "*.vhd")
lib.add_source_files(ROOT / "testbenches/fpga_ram/tb_map_ram_to_bus.vhd")
VU.main()