CHROMIUM: ASoC: Intel: Fix skylake backports

Fixup backports to maintain closed source audio BUG=b:110025789 TEST=Test Audio use cases after full SOF series patches are applied. Change-Id: If13d41954e1f581e673ac25a5225aa8eb19e70d7 Signed-off-by: Curtis Malainey <cujomalainey@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1329931 Reviewed-by: Dylan Reid <dgreid@chromium.org>
jsarha · Nov 15, 2018 · 823458d · 823458d
1 parent b94cd49
commit 823458d
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Showing 3 changed files with 6 additions and 2 deletions.
diff --git a/sound/soc/intel/skylake/skl-topology.h b/sound/soc/intel/skylake/skl-topology.h
@@ -505,9 +505,10 @@ int skl_set_module_params(struct skl_sst *ctx, u32 *params, int size,
 			u32 param_id, struct skl_module_cfg *mcfg);
 int skl_get_module_params(struct skl_sst *ctx, u32 *params, int size,
 			  u32 param_id, struct skl_module_cfg *mcfg);
-
 struct skl_module_cfg *skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai,
 								int stream);
+void skl_tplg_add_moduleid_in_bind_params(struct skl *skl,
+				struct snd_soc_dapm_widget *w);
 enum skl_bitdepth skl_get_bit_depth(int params);
 int skl_pcm_host_dma_prepare(struct device *dev,
 			struct skl_pipe_params *params);

diff --git a/sound/soc/intel/skylake/skl.c b/sound/soc/intel/skylake/skl.c
@@ -101,7 +101,7 @@ static void skl_enable_miscbdcge(struct device *dev, bool enable)
  * @dev: Device pointer
  * @enable: Enable/Disable flag
  */
-static void skl_clock_power_gating(struct device *dev, bool enable)
+void skl_clock_power_gating(struct device *dev, bool enable)
 {
 	struct pci_dev *pci = to_pci_dev(dev);
 	struct hdac_bus *bus = pci_get_drvdata(pci);

diff --git a/sound/soc/intel/skylake/skl.h b/sound/soc/intel/skylake/skl.h
@@ -41,6 +41,9 @@
 /* D0I3C Register fields */
 #define AZX_REG_VS_D0I3C_CIP      0x1 /* Command in progress */
 #define AZX_REG_VS_D0I3C_I3       0x4 /* D0i3 enable */
+#define AZX_PGCTL_ADSPPGD              BIT(2)
+#define AZX_CGCTL_ADSPDCGE             BIT(1)
+#define AZX_REG_VS_EM2_L1SEN           BIT(13)
 
 #define AZX_REG_VS_EM2_L1SEN		BIT(13)