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avxintrin-emu.h
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avxintrin-emu.h
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/*
Copyright (c) 2010, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
*/
/***
Provide feedback to: maxim.locktyukhin intel com, phil.j.kerly intel com
Version 1.0 - Initial release.
This AVX intrinsics emulation header file designed to work with Intel C/C++
as well as GCC compilers.
Known Issues and limitations:
- does not support immediate values higher than 0x7 for _mm[256]_cmp_[ps|pd]
intrinsics, UD2 instruction will be generated instead
- -O0 optimization level may _sometimes_ result with compile time errors due
to failed forced inline and compiler not being able to generate instruction
with constant immediate operand becasue of it, compiling with -O1 and/or
-finline-functions should help.
***/
#ifndef __EMU_M256_AVXIMMINTRIN_EMU_H__
#define __EMU_M256_AVXIMMINTRIN_EMU_H__
// for memset
#include <string.h>
#ifdef __GNUC__
#ifdef __SSE__
#include <xmmintrin.h>
#endif
#ifdef __SSE2__
#include <emmintrin.h>
#endif
#ifdef __SSE3__
#include <pmmintrin.h>
#endif
#ifdef __SSSE3__
#include <tmmintrin.h>
#endif
#if defined (__SSE4_2__) || defined (__SSE4_1__)
#include <smmintrin.h>
#endif
#if defined (__AES__) || defined (__PCLMUL__)
#include <wmmintrin.h>
#endif
#else
#include <wmmintrin.h>
#endif
#if !defined (__SSE3__)
#define _mm_lddqu_si128 _mm_loadu_si128
#define _mm_addsub_pd _mm_addsub_pd_SSE2
#define _mm_addsub_ps _mm_addsub_ps_SSE2
#define _mm_hadd_pd _mm_hadd_pd_SSE2
#define _mm_hadd_ps _mm_hadd_ps_SSE2
#define _mm_hsub_pd _mm_hsub_pd_SSE2
#define _mm_hsub_ps _mm_hsub_ps_SSE2
#define _mm_maddubs_epi16 _mm_maddubs_epi16_SSE2
#define _mm_movedup_pd _mm_movedup_pd_SSE2
#define _mm_movehdup_ps _mm_movehdup_ps_SSE2
#define _mm_moveldup_ps _mm_moveldup_ps_SSE2
#endif
#if !defined (__SSSE3__)
#define _mm_maddubs_epi16 _mm_maddubs_epi16_SSE2
#define _mm_shuffle_epi8 _mm_shuffle_epi8_REF
#endif
#if !(defined (__SSE4_2__) || defined (__SSE4_1__))
#define _mm_blend_pd _mm_blend_pd_REF
#define _mm_blend_ps _mm_blend_ps_SSE2
#define _mm_blendv_pd _mm_blendv_pd_SSE2
#define _mm_blendv_ps _mm_blendv_ps_SSE2
#define _mm_cmpeq_epi64 _mm_cmpeq_epi64_REF
#define _mm_cmpgt_epi64 _mm_cmpgt_epi64_REF
#define _mm_cvtepu8_epi64 _mm_cvtepu8_epi64_SSE2
#define _mm_extract_epi64 _mm_extract_epi64_REF
#define _mm_insert_epi32 _mm_insert_epi32_REF
#define _mm_insert_epi64 _mm_insert_epi64_REF
#define _mm_insert_epi8 _mm_insert_epi8_REF
#define _mm_max_epu32 _mm_max_epu32_REF
#define _mm_testc_si128 _mm_testc_si128_REF
#define _mm_testnzc_si128 _mm_testnzc_si128_REF
#define _mm_testz_si128 _mm_testz_si128_REF
#endif
// #pragma message ("Warning: AVX intrinsics are emulated with SSE")
/*
* Intel(R) AVX compiler intrinsics.
*/
#ifdef __cplusplus
extern "C" {
#endif
/*
* This is an emulation of Intel AVX
*/
#if defined( _MSC_VER ) || defined( __INTEL_COMPILER )
#define __EMU_M256_ALIGN( a ) __declspec(align(a))
#define __emu_inline __forceinline
#define __emu_int64_t __int64
#define __emu_uint64_t unsigned __int64
#elif defined( __GNUC__ )
#define __EMU_M256_ALIGN( a ) __attribute__((__aligned__(a)))
#define __emu_inline __inline __attribute__((__always_inline__))
#define __emu_int64_t long long
#define __emu_uint64_t unsigned long long
#else
#error "unsupported platform"
#endif
typedef union __EMU_M256_ALIGN(32) __emu__m256
{
float __emu_arr[8];
__m128 __emu_m128[2];
} __emu__m256;
typedef union __EMU_M256_ALIGN(32) __emu__m256d
{
double __emu_arr[4];
__m128d __emu_m128[2];
} __emu__m256d;
typedef union __EMU_M256_ALIGN(32) __emu__m256i
{
int __emu_arr[8];
__m128i __emu_m128[2];
} __emu__m256i;
#define __m256_get_ps(vec, index) vec.__emu_m128[index >> 2][index & 3]
static __emu_inline __emu__m256 __emu_set_m128( const __m128 arr[] ) { __emu__m256 ret; ret.__emu_m128[0] = arr[0]; ret.__emu_m128[1] = arr[1]; return (ret); }
static __emu_inline __emu__m256d __emu_set_m128d( const __m128d arr[] ) { __emu__m256d ret; ret.__emu_m128[0] = arr[0]; ret.__emu_m128[1] = arr[1]; return (ret); }
static __emu_inline __emu__m256i __emu_set_m128i( const __m128i arr[] ) { __emu__m256i ret; ret.__emu_m128[0] = arr[0]; ret.__emu_m128[1] = arr[1]; return (ret); }
#define __EMU_M256_IMPL_M1( type, func ) \
static __emu_inline __emu##type __emu_mm256_##func( __emu##type m256_param1 ) \
{ __emu##type res; \
res.__emu_m128[0] = _mm_##func( m256_param1.__emu_m128[0] ); \
res.__emu_m128[1] = _mm_##func( m256_param1.__emu_m128[1] ); \
return ( res ); \
}
#define __EMU_M256_IMPL_M1_RET( ret_type, type, func ) \
static __emu_inline __emu##ret_type __emu_mm256_##func( __emu##type m256_param1 ) \
{ __emu##ret_type res; \
res.__emu_m128[0] = _mm_##func( m256_param1.__emu_m128[0] ); \
res.__emu_m128[1] = _mm_##func( m256_param1.__emu_m128[1] ); \
return ( res ); \
}
#define __EMU_M256_IMPL_M1_RET_NAME( ret_type, type, func, name ) \
static __emu_inline __emu##ret_type __emu_mm256_##name( __emu##type m256_param1 ) \
{ __emu##ret_type res; \
res.__emu_m128[0] = _mm_##func( m256_param1.__emu_m128[0] ); \
res.__emu_m128[1] = _mm_##func( m256_param1.__emu_m128[1] ); \
return ( res ); \
}
#define __EMU_M256_IMPL_M1_LH( type, type_128, func ) \
static __emu_inline __emu##type __emu_mm256_##func( type_128 m128_param ) \
{ __emu##type res; \
res.__emu_m128[0] = _mm_##func( m128_param ); \
__m128 m128_param_high = _mm_movehl_ps( *(__m128*)&m128_param, *(__m128*)&m128_param ); \
res.__emu_m128[1] = _mm_##func( *(type_128*)&m128_param_high ); \
return ( res ); \
}
#define __EMU_M256_IMPL_M1_HL( type_128, type, func ) \
static __emu_inline type_128 __emu_mm256_##func( __emu##type m256_param1 ) \
{ type_128 res, tmp; \
res = _mm_##func( m256_param1.__emu_m128[0] ); \
tmp = _mm_##func( m256_param1.__emu_m128[1] ); \
*(((__emu_int64_t*)&res)+1) = *(__emu_int64_t*)&tmp; \
return ( res ); \
}
#define __EMU_M256_IMPL_M1P_DUP( type, type_param, func ) \
static __emu_inline __emu##type __emu_mm256_##func( type_param param ) \
{ __emu##type res; \
res.__emu_m128[0] = _mm_##func( param ); \
res.__emu_m128[1] = _mm_##func( param ); \
return ( res ); \
}
#define __EMU_M256_IMPL_M1I_DUP( type, func ) \
static __emu_inline __emu##type __emu_mm256_##func( __emu##type m256_param1, const int param2 ) \
{ __emu##type res; \
res.__emu_m128[0] = _mm_##func( m256_param1.__emu_m128[0], param2 ); \
res.__emu_m128[1] = _mm_##func( m256_param1.__emu_m128[1], param2 ); \
return ( res ); \
}
#define __EMU_M256_IMPL2_M1I_DUP( type, func ) \
static __emu_inline __emu##type __emu_mm256_##func( __emu##type m256_param1, const int param2 ) \
{ __emu##type res; \
res.__emu_m128[0] = __emu_mm_##func( m256_param1.__emu_m128[0], param2 ); \
res.__emu_m128[1] = __emu_mm_##func( m256_param1.__emu_m128[1], param2 ); \
return ( res ); \
}
#define __EMU_M256_IMPL2_M1I_SHIFT( type, func, shift_for_hi ) \
static __emu_inline __emu##type __emu_mm256_##func( __emu##type m256_param1, const int param2 ) \
{ __emu##type res; \
res.__emu_m128[0] = __emu_mm_##func( m256_param1.__emu_m128[0], param2 & ((1<<shift_for_hi)-1) ); \
res.__emu_m128[1] = __emu_mm_##func( m256_param1.__emu_m128[1], param2 >> shift_for_hi); \
return ( res ); \
}
#define __EMU_M256_IMPL_M2( type, func ) \
static __emu_inline __emu##type __emu_mm256_##func( __emu##type m256_param1, __emu##type m256_param2 ) \
{ __emu##type res; \
res.__emu_m128[0] = _mm_##func( m256_param1.__emu_m128[0], m256_param2.__emu_m128[0] ); \
res.__emu_m128[1] = _mm_##func( m256_param1.__emu_m128[1], m256_param2.__emu_m128[1] ); \
return ( res ); \
}
#define __EMU_M256_IMPL2_M2T( type, type_2, func ) \
static __emu_inline __emu##type __emu_mm256_##func( __emu##type m256_param1, __emu##type_2 m256_param2 ) \
{ __emu##type res; \
res.__emu_m128[0] = __emu_mm_##func( m256_param1.__emu_m128[0], m256_param2.__emu_m128[0] ); \
res.__emu_m128[1] = __emu_mm_##func( m256_param1.__emu_m128[1], m256_param2.__emu_m128[1] ); \
return ( res ); \
}
#define __EMU_M256_IMPL_M2I_DUP( type, func ) \
static __emu_inline __emu##type __emu_mm256_##func( __emu##type m256_param1, __emu##type m256_param2, const int param3 ) \
{ __emu##type res; \
res.__emu_m128[0] = _mm_##func( m256_param1.__emu_m128[0], m256_param2.__emu_m128[0], param3 ); \
res.__emu_m128[1] = _mm_##func( m256_param1.__emu_m128[1], m256_param2.__emu_m128[1], param3 ); \
return ( res ); \
}
#define __EMU_M256_IMPL2_M2I_DUP( type, func ) \
static __emu_inline __emu##type __emu_mm256_##func( __emu##type m256_param1, __emu##type m256_param2, const int param3 ) \
{ __emu##type res; \
res.__emu_m128[0] = __emu_mm_##func( m256_param1.__emu_m128[0], m256_param2.__emu_m128[0], param3 ); \
res.__emu_m128[1] = __emu_mm_##func( m256_param1.__emu_m128[1], m256_param2.__emu_m128[1], param3 ); \
return ( res ); \
}
#define __EMU_M256_IMPL_M2I_SHIFT( type, func, shift_for_hi ) \
static __emu_inline __emu##type __emu_mm256_##func( __emu##type m256_param1, __emu##type m256_param2, const int param3 ) \
{ __emu##type res; \
res.__emu_m128[0] = _mm_##func( m256_param1.__emu_m128[0], m256_param2.__emu_m128[0], param3 & ((1<<shift_for_hi)-1) ); \
res.__emu_m128[1] = _mm_##func( m256_param1.__emu_m128[1], m256_param2.__emu_m128[1], param3 >> shift_for_hi ); \
return ( res ); \
}
#define __EMU_M256_IMPL_M3( type, func ) \
static __emu_inline __emu##type __emu_mm256_##func( __emu##type m256_param1, __emu##type m256_param2, __emu##type m256_param3 ) \
{ __emu##type res; \
res.__emu_m128[0] = _mm_##func( m256_param1.__emu_m128[0], m256_param2.__emu_m128[0], m256_param3.__emu_m128[0] ); \
res.__emu_m128[1] = _mm_##func( m256_param1.__emu_m128[1], m256_param2.__emu_m128[1], m256_param3.__emu_m128[1] ); \
return ( res ); \
}
// sse2
/** */
static __emu_inline void ssp_convert_odd_even_ps_SSE2( __m128 *a, __m128 *b )
{
// IN
// a = a3,a2,a1,a0
// b = b3,b2,b1,b0
// OUT
// a = b2,b0,a2,a0 // even
// b = b3,b1,a3,a1 // odd
__m128 c, d;
c = _mm_shuffle_ps( *a, *b, _MM_SHUFFLE(3,1,3,1) );
d = _mm_shuffle_ps( *a, *b, _MM_SHUFFLE(2,0,2,0) );
*a = c;
*b = d;
}
static __emu_inline __m128i ssp_movmask_imm8_to_epi32_SSE2( int mask )
{
__m128i screen;
const __m128i mulShiftImm = _mm_set_epi16( 0x1000, 0x0000, 0x2000, 0x0000, 0x4000, 0x0000, 0x8000, 0x0000 ); // Shift mask multiply moves all bits to left, becomes MSB
screen = _mm_set1_epi16 ( mask ); // Load the mask into register
screen = _mm_mullo_epi16( screen, mulShiftImm ); // Shift bits to MSB
screen = _mm_srai_epi32 ( screen, 31 ); // Shift bits to obtain all F's or all 0's
return screen;
}
static __emu_inline __m128i ssp_logical_bitwise_select_SSE2( __m128i a, __m128i b, __m128i mask ) // Bitwise (mask ? a : b)
{
a = _mm_and_si128 ( a, mask ); // clear a where mask = 0
b = _mm_andnot_si128( mask, b ); // clear b where mask = 1
a = _mm_or_si128 ( a, b ); // a = a OR b
return a;
}
// avx2 __EMU_M256_128_IMPL_M2
#define __EMU_M256_128_IMPL_M2( type, func ) \
static __emu_inline __emu##type __emu_mm256_##func##256( __emu##type m256_param1, __emu##type m256_param2 ) \
{ __emu##type res; \
res.__emu_m128[0] = _mm_##func##128( m256_param1.__emu_m128[0], m256_param2.__emu_m128[0] ); \
res.__emu_m128[1] = _mm_##func##128( m256_param1.__emu_m128[1], m256_param2.__emu_m128[1] ); \
return ( res ); \
}
/** \SSE4_1{Reference,_mm_blend_pd} */
static __emu_inline __m128d _mm_blend_pd_REF ( __m128d a, __m128d b, const int mask )
{
__m128d A, B;
A = a;
B = b;
A[0] = (mask & 0x1) ? B[0] : A[0];
A[1] = (mask & 0x2) ? B[1] : A[1];
return A;
}
/** \SSE4_1{SSE2,_mm_blendv_pd} */
static __emu_inline __m128d _mm_blendv_pd_SSE2( __m128d a, __m128d b, __m128d mask )
{
__m128i A, B, Mask;
A = _mm_castpd_si128(a);
B = _mm_castpd_si128(b);
Mask = _mm_castpd_si128(mask);
Mask = _mm_shuffle_epi32( Mask, _MM_SHUFFLE(3, 3, 1, 1) );
Mask = _mm_srai_epi32 ( Mask, 31 );
B = _mm_and_si128( B, Mask );
A = _mm_andnot_si128( Mask, A );
A = _mm_or_si128( A, B );
return _mm_castsi128_pd(A);
}
/** \SSE4_1{SSE2,_mm_blend_ps} */
static __emu_inline __m128 _mm_blend_ps_SSE2( __m128 a, __m128 b, const int mask )
{
__m128i screen, A, B;
A = _mm_castps_si128(a);
B = _mm_castps_si128(b);
screen = ssp_movmask_imm8_to_epi32_SSE2( mask );
screen = ssp_logical_bitwise_select_SSE2( B, A, screen );
return _mm_castsi128_ps(screen);
}
/** \SSE4_1{SSE2,_mm_blendv_epi8} */
static __emu_inline __m128 _mm_blendv_ps_SSE2( __m128 a, __m128 b, __m128 mask )
{
__m128i A, B, Mask;
A = _mm_castps_si128(a);
B = _mm_castps_si128(b);
Mask = _mm_castps_si128(mask);
Mask = _mm_srai_epi32( Mask, 31 );
B = _mm_and_si128( B, Mask );
A = _mm_andnot_si128( Mask, A );
A = _mm_or_si128( A, B );
return _mm_castsi128_ps(A);
}
/** \SSE45{Reference,_mm_testc_si128,ptest} */
static __emu_inline int _mm_testc_si128_REF( __m128i a, __m128i b)
{
__m128i A,B;
A = a;
B = b;
return (((~A[0]) & B[0]) | ((~A[1]) & B[1])) == 0;
}
/** \SSE45{Reference,_mm_testz_si128,ptest} */
static __emu_inline int _mm_testz_si128_REF( __m128i a, __m128i b)
{
__m128i A,B;
A = a;
B = b;
return ( (A[0] & B[0]) | (A[1] & B[1])) == 0;
}
/** \SSE45{Reference,_mm_testnzc_si128,ptest} */
static __emu_inline int _mm_testnzc_si128_REF( __m128i a, __m128i b)
{
int zf, cf;
__m128i A,B;
A = a;
B = b;
zf = _mm_testz_si128_REF(A, B);
cf = _mm_testc_si128_REF(A, B);
return ((int)!zf & (int)!cf);
}
/** \SSE3{SSE2,_mm_addsub_ps} */
static __emu_inline __m128 _mm_addsub_ps_SSE2(__m128 a, __m128 b)
{
static __m128 const const_addSub_ps_neg = { -1, 1, -1, 1 };
b = _mm_mul_ps( b, const_addSub_ps_neg );
a = _mm_add_ps( a, b );
return a;
}
/** \SSE3{SSE2,_mm_addsub_pd} */
static __emu_inline __m128d _mm_addsub_pd_SSE2(__m128d a, __m128d b)
{
static __m128d const const_addSub_pd_neg = { -1, 1 };
b = _mm_mul_pd( b, const_addSub_pd_neg );
a = _mm_add_pd( a, b );
return a;
}
/** \SSE5{Reference,_mm_comgt_epi64, pcomq } */
static __emu_inline __m128i _mm_cmpgt_epi64_REF(__m128i a, __m128i b)
{
__m128i A,B;
A = a;
B = b;
A[0] = (A[0]>B[0]) ? 0xFFFFFFFFFFFFFFFF : 0;
A[1] = (A[1]>B[1]) ? 0xFFFFFFFFFFFFFFFF : 0;
return A;
}
//---------------------------------------
/** \SSE4_1{Reference,_mm_cmpeq_epi64} */
static __emu_inline __m128i _mm_cmpeq_epi64_REF( __m128i a, __m128i b )
{
__m128i A, B;
A = a;
B = b;
if( A[0] == B[0] )
A[0] = 0xFFFFFFFFFFFFFFFFll;
else
A[0] = 0x0ll;
if( A[1] == B[1] )
A[1] = 0xFFFFFFFFFFFFFFFFll;
else
A[1] = 0x0ll;
return A;
}
#define SSP_SET_MIN( sd, s) sd=((sd)<(s))?(sd):(s);
#define SSP_SET_MAX( sd, s) sd=((sd)>(s))?(sd):(s);
/** \SSE4_1{Reference,_mm_max_epu32} */
static __emu_inline __m128i _mm_max_epu32_REF ( __m128i a, __m128i b )
{
__m128i A,B;
A = a;
B = b;
SSP_SET_MAX( ((unsigned int*)(&A))[0] , ((unsigned int*)(&B))[0] );
SSP_SET_MAX( ((unsigned int*)(&A))[1] , ((unsigned int*)(&B))[1] );
SSP_SET_MAX( ((unsigned int*)(&A))[2] , ((unsigned int*)(&B))[2] );
SSP_SET_MAX( ((unsigned int*)(&A))[3] , ((unsigned int*)(&B))[3] );
return A;
}
/** \SSE3{SSE2,_mm_movehdup_ps} */
static __emu_inline __m128 _mm_movehdup_ps_SSE2(__m128 a)
{
__m128 A;
A = _mm_castsi128_ps(_mm_shuffle_epi32( _mm_castps_si128(a), _MM_SHUFFLE( 3, 3, 1, 1) ));
return A;
}
/** \SSE3{SSE2,_mm_moveldup_ps} */
static __emu_inline __m128 _mm_moveldup_ps_SSE2(__m128 a)
{
__m128 A;
A = _mm_castsi128_ps(_mm_shuffle_epi32( _mm_castps_si128(a), _MM_SHUFFLE( 2, 2, 0, 0) ));
return A;
}
/** \SSE3{SSE2,_mm_movedup_pd} */
static __emu_inline __m128d _mm_movedup_pd_SSE2(__m128d a)
{
__m128d A;
A = a;
return _mm_set_pd( A[0], A[0] );
}
/** \SSE3{SSE2,_mm_hadd_ps} */
static __emu_inline __m128 _mm_hadd_ps_SSE2(__m128 a, __m128 b)
{
ssp_convert_odd_even_ps_SSE2( &a, &b );
a = _mm_add_ps( a, b );
return a;
}
/** \SSE3{SSE2,_mm_hadd_pd} */
static __emu_inline __m128d _mm_hadd_pd_SSE2(__m128d a, __m128d b)
{
__m128d A,B,C;
A = a;
C = a;
B = b;
A = _mm_castps_pd( _mm_movelh_ps( _mm_castpd_ps(A), _mm_castpd_ps(B) ) );
B = _mm_castps_pd( _mm_movehl_ps( _mm_castpd_ps(B), _mm_castpd_ps(C) ) );
A = _mm_add_pd ( A, B );
return A;
}
/** \SSE3{SSE2,_mm_hsub_ps} */
static __emu_inline __m128 _mm_hsub_ps_SSE2(__m128 a, __m128 b)
{
ssp_convert_odd_even_ps_SSE2( &a, &b );
a = _mm_sub_ps( b, a );
return a;
}
/** \SSE3{SSE2,_mm_hsub_pd} */
static __emu_inline __m128d _mm_hsub_pd_SSE2(__m128d a, __m128d b)
{
__m128d A,B,C;
A = a;
C = a;
B = b;
A = _mm_castps_pd( _mm_movelh_ps( _mm_castpd_ps(A), _mm_castpd_ps(B) ) );
B = _mm_castps_pd( _mm_movehl_ps( _mm_castpd_ps(B), _mm_castpd_ps(C) ) );
A = _mm_sub_pd ( A, B );
return A;
}
/** \SSE4_1{Reference,_mm_insert_epi8} */
static __emu_inline __m128i _mm_insert_epi8_REF( __m128i a, int b, const int ndx )
{
__m128i A;
A = a;
((int8_t*)(&A))[ndx & 0xF] = b;
return A;
}
/** \SSE4_1{Reference,_mm_insert_epi32} */
static __emu_inline __m128i _mm_insert_epi32_REF( __m128i a, int b, const int ndx )
{
__m128i A;
A = a;
((int*)(&A))[ndx & 0x3] = b;
return A;
}
/** \SSE4_1{Reference,_mm_insert_epi64} */
static __emu_inline __m128i _mm_insert_epi64_REF( __m128i a, long long b, const int ndx )
{
__m128i A;
A = a;
A[ndx & 0x1] = b;
return A;
}
/** \SSE4_1{Reference,_mm_extract_epi64} */
static __emu_inline __emu_int64_t _mm_extract_epi64_REF( __m128i a, const int ndx )
{
__m128i A;
A = a;
return A[ndx & 0x1];
}
//__m128i _mm_shuffle_epi8( __m128i a, __m128i mask);
/** \SSSE3{Reference,_mm_shuffle_epi8} */
static __emu_inline __m128i _mm_shuffle_epi8_REF (__m128i a, __m128i mask)
{
__m128i ret;
int8_t A[16], MSK[16], B[16];
memcpy(A,&a,16);
memcpy(MSK,&mask,16);
// full unroll is faster
B[0] = (MSK[0] & 0x80) ? 0 : A[(MSK[0] & 0xf)];
B[1] = (MSK[1] & 0x80) ? 0 : A[(MSK[1] & 0xf)];
B[2] = (MSK[2] & 0x80) ? 0 : A[(MSK[2] & 0xf)];
B[3] = (MSK[3] & 0x80) ? 0 : A[(MSK[3] & 0xf)];
B[4] = (MSK[4] & 0x80) ? 0 : A[(MSK[4] & 0xf)];
B[5] = (MSK[5] & 0x80) ? 0 : A[(MSK[5] & 0xf)];
B[6] = (MSK[6] & 0x80) ? 0 : A[(MSK[6] & 0xf)];
B[7] = (MSK[7] & 0x80) ? 0 : A[(MSK[7] & 0xf)];
B[8] = (MSK[8] & 0x80) ? 0 : A[(MSK[8] & 0xf)];
B[9] = (MSK[9] & 0x80) ? 0 : A[(MSK[9] & 0xf)];
B[10] = (MSK[10] & 0x80) ? 0 : A[(MSK[10] & 0xf)];
B[11] = (MSK[11] & 0x80) ? 0 : A[(MSK[11] & 0xf)];
B[12] = (MSK[12] & 0x80) ? 0 : A[(MSK[12] & 0xf)];
B[13] = (MSK[13] & 0x80) ? 0 : A[(MSK[13] & 0xf)];
B[14] = (MSK[14] & 0x80) ? 0 : A[(MSK[14] & 0xf)];
B[15] = (MSK[15] & 0x80) ? 0 : A[(MSK[15] & 0xf)];
memcpy(&ret,B,16);
return ret;
}
/** \SSSE3{SSE2,_mm_maddubs_epi16}
in: 2 registers x 16 x 8 bit values (a is unsigned, b is signed)
out: 1 register x 8 x 16 bit values
r0 := SATURATE_16((a0 * b0) + (a1 * b1))
*/
static __emu_inline __m128i _mm_maddubs_epi16_SSE2( __m128i a, __m128i b)
{
const __m128i EVEN_8 = _mm_set_epi8( 0,0xFF,0,0xFF,0,0xFF,0,0xFF,0,0xFF,0,0xFF,0,0xFF,0,0xFF);
__m128i Aodd, Aeven, Beven, Bodd;
// Convert the 8 bit inputs into 16 bits by dropping every other value
Aodd = _mm_srli_epi16( a, 8 ); // A is unsigned
Bodd = _mm_srai_epi16( b, 8 ); // B is signed
Aeven = _mm_and_si128 ( a, EVEN_8 ); // A is unsigned
Beven = _mm_slli_si128( b, 1 ); // B is signed
Beven = _mm_srai_epi16( Beven, 8 );
a = _mm_mullo_epi16( Aodd , Bodd ); // Will always fit in lower 16
b = _mm_mullo_epi16( Aeven, Beven );
a = _mm_adds_epi16 ( a, b );
return a;
}
/** \{Reference,_mm256_blend_epi32} */
static __emu_inline __emu__m256i __emu_mm256_blend_epi32_REF ( __emu__m256i a, __emu__m256i b, const int mask )
{
__emu__m256i ret;
ret.__emu_arr[0] = (mask & 0x1) ? b.__emu_arr[0] : a.__emu_arr[0];
ret.__emu_arr[1] = (mask & 0x2) ? b.__emu_arr[1] : a.__emu_arr[1];
ret.__emu_arr[2] = (mask & 0x4) ? b.__emu_arr[2] : a.__emu_arr[2];
ret.__emu_arr[3] = (mask & 0x8) ? b.__emu_arr[3] : a.__emu_arr[3];
ret.__emu_arr[4] = (mask & 0x10) ? b.__emu_arr[4] : a.__emu_arr[4];
ret.__emu_arr[5] = (mask & 0x20) ? b.__emu_arr[5] : a.__emu_arr[5];
ret.__emu_arr[6] = (mask & 0x40) ? b.__emu_arr[6] : a.__emu_arr[6];
ret.__emu_arr[7] = (mask & 0x80) ? b.__emu_arr[7] : a.__emu_arr[7];
return ret;
}
/** \AVX{Reference,_mm256_extract_epi64} */
static __emu_inline __emu_int64_t __emu_mm256_extract_epi64( __emu__m256i a, const int ndx )
{
__emu__m256i A;
A = a;
return ((__emu_int64_t*)(&A))[ndx & 0x3];
}
/*
* Compare predicates for scalar and packed compare intrinsics
*/
#define _CMP_EQ_OQ 0x00 /* Equal (ordered, nonsignaling) */
#define _CMP_LT_OS 0x01 /* Less-than (ordered, signaling) */
#define _CMP_LE_OS 0x02 /* Less-than-or-equal (ordered, signaling) */
#define _CMP_UNORD_Q 0x03 /* Unordered (nonsignaling) */
#define _CMP_NEQ_UQ 0x04 /* Not-equal (unordered, nonsignaling) */
#define _CMP_NLT_US 0x05 /* Not-less-than (unordered, signaling) */
#define _CMP_NLE_US 0x06 /* Not-less-than-or-equal (unordered, signaling) */
#define _CMP_ORD_Q 0x07 /* Ordered (nonsignaling) */
#define _CMP_EQ_UQ 0x08 /* Equal (unordered, non-signaling) */
#define _CMP_NGE_US 0x09 /* Not-greater-than-or-equal (unordered, signaling) */
#define _CMP_NGT_US 0x0A /* Not-greater-than (unordered, signaling) */
#define _CMP_FALSE_OQ 0x0B /* False (ordered, nonsignaling) */
#define _CMP_NEQ_OQ 0x0C /* Not-equal (ordered, non-signaling) */
#define _CMP_GE_OS 0x0D /* Greater-than-or-equal (ordered, signaling) */
#define _CMP_GT_OS 0x0E /* Greater-than (ordered, signaling) */
#define _CMP_TRUE_UQ 0x0F /* True (unordered, non-signaling) */
#define _CMP_EQ_OS 0x10 /* Equal (ordered, signaling) */
#define _CMP_LT_OQ 0x11 /* Less-than (ordered, nonsignaling) */
#define _CMP_LE_OQ 0x12 /* Less-than-or-equal (ordered, nonsignaling) */
#define _CMP_UNORD_S 0x13 /* Unordered (signaling) */
#define _CMP_NEQ_US 0x14 /* Not-equal (unordered, signaling) */
#define _CMP_NLT_UQ 0x15 /* Not-less-than (unordered, nonsignaling) */
#define _CMP_NLE_UQ 0x16 /* Not-less-than-or-equal (unordered, nonsignaling) */
#define _CMP_ORD_S 0x17 /* Ordered (signaling) */
#define _CMP_EQ_US 0x18 /* Equal (unordered, signaling) */
#define _CMP_NGE_UQ 0x19 /* Not-greater-than-or-equal (unordered, nonsignaling) */
#define _CMP_NGT_UQ 0x1A /* Not-greater-than (unordered, nonsignaling) */
#define _CMP_FALSE_OS 0x1B /* False (ordered, signaling) */
#define _CMP_NEQ_OS 0x1C /* Not-equal (ordered, signaling) */
#define _CMP_GE_OQ 0x1D /* Greater-than-or-equal (ordered, nonsignaling) */
#define _CMP_GT_OQ 0x1E /* Greater-than (ordered, nonsignaling) */
#define _CMP_TRUE_US 0x1F /* True (unordered, signaling) */
// avx2
static __emu_inline __emu__m256i __emu_mm256_broadcastb_epi8 ( __m128i a )
{
__emu__m256i A;
__m128i av = a;
memset(&A, *(int8_t*)&av, 32);
return A;
}
static __emu_inline __emu__m256i __emu_mm256_broadcastd_epi32 ( __m128i a )
{
__emu__m256i A;
int *m = (int*) &a;
int *p = (int*) &A;
for (int i=0; i<8; i++) p[i] = m[0];
return A;
}
static __emu_inline __emu__m256i __emu_mm256_broadcastq_epi64 ( __m128i a )
{
__emu__m256i A;
__emu_int64_t *m = (__emu_int64_t*) &a;
__emu_int64_t *p = (__emu_int64_t*) &A;
for (int i=0; i<4; i++) p[i] = m[0];
return A;
}
static __emu_inline __emu__m256i __emu_mm256_broadcastsi128_si256 ( __m128i a )
{
__emu__m256i A;
A.__emu_m128[0] = a;
A.__emu_m128[1] = a;
return A;
}
static __emu_inline __m128i __emu_mm_blendv_epi8(__m128i a, __m128i b, __m128i m)
{
m=_mm_cmpgt_epi8(_mm_setzero_si128(), m);
return ssp_logical_bitwise_select_SSE2(b, a, m);
}
static __emu_inline __emu__m256i __emu_mm256_blendv_epi8(__emu__m256i a, __emu__m256i b, __emu__m256i m)
{
__emu__m256i A;
A.__emu_m128[0] = __emu_mm_blendv_epi8(a.__emu_m128[0], b.__emu_m128[0], m.__emu_m128[0]);
A.__emu_m128[1] = __emu_mm_blendv_epi8(a.__emu_m128[1], b.__emu_m128[1], m.__emu_m128[1]);
return A;
}
static __emu_inline __emu__m256i __emu_mm256_slli_epi64 ( __emu__m256i a, int imm )
{
__emu__m256i A;
A.__emu_m128[0] = _mm_slli_epi64( a.__emu_m128[0], imm);
A.__emu_m128[1] = _mm_slli_epi64( a.__emu_m128[1], imm);
return A;
}
static __emu_inline __emu__m256i __emu_mm256_srli_epi16 ( __emu__m256i a, int imm )
{
__emu__m256i A;
A.__emu_m128[0] = _mm_srli_epi16( a.__emu_m128[0], imm);
A.__emu_m128[1] = _mm_srli_epi16( a.__emu_m128[1], imm);
return A;
}
static __emu_inline __emu__m256i __emu_mm256_srli_epi32 ( __emu__m256i a, int imm )
{
__emu__m256i A;
A.__emu_m128[0] = _mm_srli_epi32( a.__emu_m128[0], imm);
A.__emu_m128[1] = _mm_srli_epi32( a.__emu_m128[1], imm);
return A;
}
static __emu_inline __emu__m256i __emu_mm256_srli_epi64 ( __emu__m256i a, int imm )
{
__emu__m256i A;
A.__emu_m128[0] = _mm_srli_epi64( a.__emu_m128[0], imm);
A.__emu_m128[1] = _mm_srli_epi64( a.__emu_m128[1], imm);
return A;
}
#if defined(__clang__)
#define __emu_mm256_srli_si256( a, imm ) \
({ \
__emu__m256i A; \
A.__emu_m128[0] = _mm_srli_si128( a.__emu_m128[0], imm); \
A.__emu_m128[1] = _mm_srli_si128( a.__emu_m128[1], imm); \
A; \
})
#else
static __emu_inline __emu__m256i __emu_mm256_srli_si256 ( __emu__m256i a, int imm )
{
__emu__m256i A;
A.__emu_m128[0] = _mm_srli_si128( a.__emu_m128[0], imm);
A.__emu_m128[1] = _mm_srli_si128( a.__emu_m128[1], imm);
return A;
}
#endif
// avx2
__EMU_M256_IMPL_M2( __m256i, cmpgt_epi16 );
__EMU_M256_IMPL_M2( __m256i, cmpgt_epi32 );
__EMU_M256_IMPL_M2( __m256i, cmpgt_epi64 );
__EMU_M256_IMPL_M2( __m256i, cmpgt_epi8 );
__EMU_M256_IMPL_M2( __m256i, add_epi64 );
__EMU_M256_IMPL_M2( __m256i, sub_epi64 );
__EMU_M256_IMPL_M2( __m256d, add_pd );
__EMU_M256_IMPL_M2( __m256, add_ps );
__EMU_M256_IMPL_M2( __m256d, addsub_pd );
__EMU_M256_IMPL_M2( __m256, addsub_ps );
__EMU_M256_IMPL_M2( __m256d, and_pd );
__EMU_M256_IMPL_M2( __m256, and_ps );
__EMU_M256_IMPL_M2( __m256d, andnot_pd );
__EMU_M256_IMPL_M2( __m256, andnot_ps );
__EMU_M256_IMPL_M2( __m256d, div_pd );
__EMU_M256_IMPL_M2( __m256, div_ps );
__EMU_M256_IMPL_M2( __m256d, hadd_pd );
__EMU_M256_IMPL_M2( __m256, hadd_ps );
__EMU_M256_IMPL_M2( __m256d, hsub_pd );
__EMU_M256_IMPL_M2( __m256, hsub_ps );
__EMU_M256_IMPL_M2( __m256d, max_pd );
__EMU_M256_IMPL_M2( __m256, max_ps );
__EMU_M256_IMPL_M2( __m256d, min_pd );
__EMU_M256_IMPL_M2( __m256, min_ps );
__EMU_M256_IMPL_M2( __m256d, mul_pd );
__EMU_M256_IMPL_M2( __m256, mul_ps );
__EMU_M256_IMPL_M2( __m256d, or_pd );
__EMU_M256_IMPL_M2( __m256, or_ps );
#if defined(__clang__)
#define __emu_mm256_shuffle_pd( m256_param1, m256_param2, param3 ) \
({ __emu__m256d res; \
res.__emu_m128[0] = _mm_shuffle_pd( m256_param1.__emu_m128[0], m256_param2.__emu_m128[0], (param3) & ((1<<2)-1) ); \
res.__emu_m128[1] = _mm_shuffle_pd( m256_param1.__emu_m128[1], m256_param2.__emu_m128[1], (param3) >> 2 ); \
res; \
})
#define __emu_mm256_shuffle_ps( m256_param1, m256_param2, param3 ) \
({ __emu__m256 res; \
res.__emu_m128[0] = _mm_shuffle_ps( m256_param1.__emu_m128[0], m256_param2.__emu_m128[0], param3 ); \
res.__emu_m128[1] = _mm_shuffle_ps( m256_param1.__emu_m128[1], m256_param2.__emu_m128[1], param3 ); \
res; \
})
#else
__EMU_M256_IMPL_M2I_SHIFT( __m256d, shuffle_pd, 2 );
__EMU_M256_IMPL_M2I_DUP( __m256, shuffle_ps );
#endif
__EMU_M256_IMPL_M2( __m256d, sub_pd );
__EMU_M256_IMPL_M2( __m256, sub_ps );
__EMU_M256_IMPL_M2( __m256d, xor_pd );
__EMU_M256_IMPL_M2( __m256, xor_ps );
#if defined (__SSE4_2__) || defined (__SSE4_1__)
#if defined(__clang__)
#define __emu_mm256_blend_pd( m256_param1, m256_param2, param3 ) \
({ __emu__m256d res; \
res.__emu_m128[0] = _mm_blend_pd( m256_param1.__emu_m128[0], m256_param2.__emu_m128[0], (param3) & ((1<<2)-1) ); \
res.__emu_m128[1] = _mm_blend_pd( m256_param1.__emu_m128[1], m256_param2.__emu_m128[1], (param3) >> 2 ); \
res ; \
})
#define __emu_mm256_blend_ps( m256_param1, m256_param2, param3 ) \
({ __emu__m256 res; \
res.__emu_m128[0] = _mm_blend_ps( m256_param1.__emu_m128[0], m256_param2.__emu_m128[0], (param3) & ((1<<4)-1) ); \
res.__emu_m128[1] = _mm_blend_ps( m256_param1.__emu_m128[1], m256_param2.__emu_m128[1], (param3) >> 4 ); \
res ; \
})
#define __emu_mm256_blendv_pd( m256_param1, m256_param2, m256_param3 ) \
({ __emu__m256d res; \
res.__emu_m128[0] = _mm_blendv_pd( m256_param1.__emu_m128[0], m256_param2.__emu_m128[0], m256_param3.__emu_m128[0] ); \
res.__emu_m128[1] = _mm_blendv_pd( m256_param1.__emu_m128[1], m256_param2.__emu_m128[1], m256_param3.__emu_m128[1] ); \
res ; \
})
#define __emu_mm256_blendv_ps( m256_param1, m256_param2, m256_param3 ) \
({ __emu__m256 res; \
res.__emu_m128[0] = _mm_blendv_ps( m256_param1.__emu_m128[0], m256_param2.__emu_m128[0], m256_param3.__emu_m128[0] ); \
res.__emu_m128[1] = _mm_blendv_ps( m256_param1.__emu_m128[1], m256_param2.__emu_m128[1], m256_param3.__emu_m128[1] ); \
res ; \
})
#else
__EMU_M256_IMPL_M2I_SHIFT( __m256d, blend_pd, 2 );
__EMU_M256_IMPL_M2I_SHIFT( __m256, blend_ps, 4 );
__EMU_M256_IMPL_M3( __m256d, blendv_pd );
__EMU_M256_IMPL_M3( __m256, blendv_ps );
#endif
#else
__EMU_M256_IMPL_M2I_SHIFT( __m256d, blend_pd, 2 );
__EMU_M256_IMPL_M2I_SHIFT( __m256, blend_ps, 4 );
__EMU_M256_IMPL_M3( __m256d, blendv_pd );
__EMU_M256_IMPL_M3( __m256, blendv_ps );
#endif
#if defined (__SSE4_2__) || defined (__SSE4_1__)
#if defined(__clang__)
#define __emu_mm256_dp_ps( m256_param1, m256_param2, param3 ) \
({ __emu__m256 res; \
res.__emu_m128[0] = _mm_dp_ps( m256_param1.__emu_m128[0], m256_param2.__emu_m128[0], param3 ); \
res.__emu_m128[1] = _mm_dp_ps( m256_param1.__emu_m128[1], m256_param2.__emu_m128[1], param3 ); \
res ; \
})
#define __emu_mm256_round_pd( m256_param1, param2 ) \
({ __emu__m256d res; \
res.__emu_m128[0] = _mm_round_pd( m256_param1.__emu_m128[0], param2 ); \
res.__emu_m128[1] = _mm_round_pd( m256_param1.__emu_m128[1], param2 ); \
res ; \
})
#else
__EMU_M256_IMPL_M2I_DUP( __m256, dp_ps );
__EMU_M256_IMPL_M1I_DUP( __m256d, round_pd );
#endif
#define _mm256_ceil_pd(val) _mm256_round_pd((val), 0x0A);
#define _mm256_floor_pd(val) _mm256_round_pd((val), 0x09);
#if defined(__clang__)
#define __emu_mm256_round_ps( m256_param1, param2 ) \
({ __emu__m256d res; \
res.__emu_m128[0] = _mm_round_ps( m256_param1.__emu_m128[0], param2 ); \
res.__emu_m128[1] = _mm_round_ps( m256_param1.__emu_m128[1], param2 ); \
res ; \
})
#else
__EMU_M256_IMPL_M1I_DUP( __m256, round_ps );
#endif
#define _mm256_ceil_ps(val) _mm256_round_ps((val), 0x0A);
#define _mm256_floor_ps(val) _mm256_round_ps((val), 0x09);
#endif
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wunused-variable"
#if defined (__SSE4_2__) || defined (__SSE4_1__)
#define __emu_mm_test_impl( op, sfx, vec_type ) \
static __emu_inline int __emu_mm_test##op##_##sfx(vec_type s1, vec_type s2) { \
__m128d sign_bits_pd = _mm_castsi128_pd( _mm_set_epi32( 1 << 31, 0, 1 << 31, 0 ) ); \
__m128 sign_bits_ps = _mm_castsi128_ps( _mm_set1_epi32( 1 << 31 ) ); \
\
s1 = _mm_and_##sfx( s1, sign_bits_##sfx ); \
s2 = _mm_and_##sfx( s2, sign_bits_##sfx ); \
return _mm_test##op##_si128( _mm_cast##sfx##_si128( s1 ), _mm_cast##sfx##_si128( s2 ) ); \
}
__emu_mm_test_impl( z, pd, __m128d );
__emu_mm_test_impl( c, pd, __m128d );
__emu_mm_test_impl( nzc, pd, __m128d );
__emu_mm_test_impl( z, ps, __m128 );
__emu_mm_test_impl( c, ps, __m128 );
__emu_mm_test_impl( nzc, ps, __m128 );
#else
#define __emu_mm_test_impl( op, sfx, vec_type ) \
static __emu_inline int __emu_mm_test##op##_##sfx(vec_type s1, vec_type s2) { \
__m128d sign_bits_pd = _mm_castsi128_pd( _mm_set_epi32( 1 << 31, 0, 1 << 31, 0 ) ); \
__m128 sign_bits_ps = _mm_castsi128_ps( _mm_set1_epi32( 1 << 31 ) ); \
\
s1 = _mm_and_##sfx( s1, sign_bits_##sfx ); \
s2 = _mm_and_##sfx( s2, sign_bits_##sfx ); \