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Amend UC_X86_REG constants
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Julian Torreno committed Dec 18, 2021
1 parent 01ba6ce commit 43eec3a
Showing 1 changed file with 2 additions and 20 deletions.
22 changes: 2 additions & 20 deletions src/dumpulator/dumpulator.py
Original file line number Original file line Diff line number Diff line change
Expand Up @@ -94,7 +94,6 @@ def __init__(self, uc: Uc, x64):
"rdi": UC_X86_REG_RDI, "rdi": UC_X86_REG_RDI,
"rdx": UC_X86_REG_RDX, "rdx": UC_X86_REG_RDX,
"rip": UC_X86_REG_RIP, "rip": UC_X86_REG_RIP,
"riz": UC_X86_REG_RIZ,
"rsi": UC_X86_REG_RSI, "rsi": UC_X86_REG_RSI,
"rsp": UC_X86_REG_RSP, "rsp": UC_X86_REG_RSP,
"si": UC_X86_REG_SI, "si": UC_X86_REG_SI,
Expand All @@ -107,17 +106,7 @@ def __init__(self, uc: Uc, x64):
"cr2": UC_X86_REG_CR2, "cr2": UC_X86_REG_CR2,
"cr3": UC_X86_REG_CR3, "cr3": UC_X86_REG_CR3,
"cr4": UC_X86_REG_CR4, "cr4": UC_X86_REG_CR4,
"cr5": UC_X86_REG_CR5,
"cr6": UC_X86_REG_CR6,
"cr7": UC_X86_REG_CR7,
"cr8": UC_X86_REG_CR8, "cr8": UC_X86_REG_CR8,
"cr9": UC_X86_REG_CR9,
"cr10": UC_X86_REG_CR10,
"cr11": UC_X86_REG_CR11,
"cr12": UC_X86_REG_CR12,
"cr13": UC_X86_REG_CR13,
"cr14": UC_X86_REG_CR14,
"cr15": UC_X86_REG_CR15,
"dr0": UC_X86_REG_DR0, "dr0": UC_X86_REG_DR0,
"dr1": UC_X86_REG_DR1, "dr1": UC_X86_REG_DR1,
"dr2": UC_X86_REG_DR2, "dr2": UC_X86_REG_DR2,
Expand All @@ -126,14 +115,6 @@ def __init__(self, uc: Uc, x64):
"dr5": UC_X86_REG_DR5, "dr5": UC_X86_REG_DR5,
"dr6": UC_X86_REG_DR6, "dr6": UC_X86_REG_DR6,
"dr7": UC_X86_REG_DR7, "dr7": UC_X86_REG_DR7,
"dr8": UC_X86_REG_DR8,
"dr9": UC_X86_REG_DR9,
"dr10": UC_X86_REG_DR10,
"dr11": UC_X86_REG_DR11,
"dr12": UC_X86_REG_DR12,
"dr13": UC_X86_REG_DR13,
"dr14": UC_X86_REG_DR14,
"dr15": UC_X86_REG_DR15,
"fp0": UC_X86_REG_FP0, "fp0": UC_X86_REG_FP0,
"fp1": UC_X86_REG_FP1, "fp1": UC_X86_REG_FP1,
"fp2": UC_X86_REG_FP2, "fp2": UC_X86_REG_FP2,
Expand Down Expand Up @@ -304,7 +285,8 @@ def __init__(self, uc: Uc, x64):
"mxcsr": UC_X86_REG_MXCSR, "mxcsr": UC_X86_REG_MXCSR,
"fs_base": UC_X86_REG_FS_BASE, "fs_base": UC_X86_REG_FS_BASE,
"gs_base": UC_X86_REG_GS_BASE, "gs_base": UC_X86_REG_GS_BASE,
"rflags": UC_X86_REG_EFLAGS, "flags": UC_X86_REG_FLAGS,
"rflags": UC_X86_REG_RFLAGS,
} }
if self._x64: if self._x64:
self._regmap.update({ self._regmap.update({
Expand Down

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