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stm32:adc: Change bitwise AND to logical AND
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The original bitwise AND was _functionally_ correct because all operands
were booleans, but it was very poor at conveying the intent.

Fixes libopencm3#1230
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rma-x authored and karlp committed Jul 3, 2020
1 parent 9075395 commit 24bef9c
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Showing 2 changed files with 7 additions and 7 deletions.
8 changes: 4 additions & 4 deletions lib/stm32/common/adc_common_v1.c
Expand Up @@ -588,16 +588,16 @@ void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
if (i <= 6) {
first6 |= (channel[i - 1] << ((i - 1) * 5));
}
if ((i > 6) & (i <= 12)) {
if ((i > 6) && (i <= 12)) {
second6 |= (channel[i - 1] << ((i - 6 - 1) * 5));
}
if ((i > 12) & (i <= 18)) {
if ((i > 12) && (i <= 18)) {
third6 |= (channel[i - 1] << ((i - 12 - 1) * 5));
}
if ((i > 18) & (i <= 24)) {
if ((i > 18) && (i <= 24)) {
fourth6 |= (channel[i - 1] << ((i - 18 - 1) * 5));
}
if ((i > 24) & (i <= 28)) {
if ((i > 24) && (i <= 28)) {
fifth6 |= (channel[i - 1] << ((i - 24 - 1) * 5));
}
}
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6 changes: 3 additions & 3 deletions lib/stm32/common/adc_common_v2_multi.c
Expand Up @@ -111,13 +111,13 @@ void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
if (i <= 4) {
reg32_1 |= (channel[i - 1] << (i * 6));
}
if ((i > 4) & (i <= 9)) {
if ((i > 4) && (i <= 9)) {
reg32_2 |= (channel[i - 1] << ((i - 4 - 1) * 6));
}
if ((i > 9) & (i <= 14)) {
if ((i > 9) && (i <= 14)) {
reg32_3 |= (channel[i - 1] << ((i - 9 - 1) * 6));
}
if ((i > 14) & (i <= 16)) {
if ((i > 14) && (i <= 16)) {
reg32_4 |= (channel[i - 1] << ((i - 14 - 1) * 6));
}
}
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