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efx.h
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efx.h
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/* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2006-2018 Solarflare Communications Inc.
* All rights reserved.
*/
#ifndef _SYS_EFX_H
#define _SYS_EFX_H
#include "efx_annote.h"
#include "efsys.h"
#include "efx_check.h"
#include "efx_phy_ids.h"
#ifdef __cplusplus
extern "C" {
#endif
#define EFX_STATIC_ASSERT(_cond) \
((void)sizeof (char[(_cond) ? 1 : -1]))
#define EFX_ARRAY_SIZE(_array) \
(sizeof (_array) / sizeof ((_array)[0]))
#define EFX_FIELD_OFFSET(_type, _field) \
((size_t)&(((_type *)0)->_field))
/* The macro expands divider twice */
#define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
/* Round value up to the nearest power of two. */
#define EFX_P2ROUNDUP(_type, _value, _align) \
(-(-(_type)(_value) & -(_type)(_align)))
/* Return codes */
typedef __success(return == 0) int efx_rc_t;
/* Chip families */
typedef enum efx_family_e {
EFX_FAMILY_INVALID,
EFX_FAMILY_FALCON, /* Obsolete and not supported */
EFX_FAMILY_SIENA,
EFX_FAMILY_HUNTINGTON,
EFX_FAMILY_MEDFORD,
EFX_FAMILY_MEDFORD2,
EFX_FAMILY_NTYPES
} efx_family_t;
extern __checkReturn efx_rc_t
efx_family(
__in uint16_t venid,
__in uint16_t devid,
__out efx_family_t *efp,
__out unsigned int *membarp);
#define EFX_PCI_VENID_SFC 0x1924
#define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
#define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
#define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
#define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
#define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
#define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
#define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
#define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
#define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
#define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
#define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
#define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
#define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
#define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
#define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
#define EFX_MEM_BAR_SIENA 2
#define EFX_MEM_BAR_HUNTINGTON_PF 2
#define EFX_MEM_BAR_HUNTINGTON_VF 0
#define EFX_MEM_BAR_MEDFORD_PF 2
#define EFX_MEM_BAR_MEDFORD_VF 0
#define EFX_MEM_BAR_MEDFORD2 0
/* Error codes */
enum {
EFX_ERR_INVALID,
EFX_ERR_SRAM_OOB,
EFX_ERR_BUFID_DC_OOB,
EFX_ERR_MEM_PERR,
EFX_ERR_RBUF_OWN,
EFX_ERR_TBUF_OWN,
EFX_ERR_RDESQ_OWN,
EFX_ERR_TDESQ_OWN,
EFX_ERR_EVQ_OWN,
EFX_ERR_EVFF_OFLO,
EFX_ERR_ILL_ADDR,
EFX_ERR_SRAM_PERR,
EFX_ERR_NCODES
};
/* Calculate the IEEE 802.3 CRC32 of a MAC addr */
extern __checkReturn uint32_t
efx_crc32_calculate(
__in uint32_t crc_init,
__in_ecount(length) uint8_t const *input,
__in int length);
/* Type prototypes */
typedef struct efx_rxq_s efx_rxq_t;
/* NIC */
typedef struct efx_nic_s efx_nic_t;
extern __checkReturn efx_rc_t
efx_nic_create(
__in efx_family_t family,
__in efsys_identifier_t *esip,
__in efsys_bar_t *esbp,
__in efsys_lock_t *eslp,
__deref_out efx_nic_t **enpp);
/* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
typedef enum efx_fw_variant_e {
EFX_FW_VARIANT_FULL_FEATURED,
EFX_FW_VARIANT_LOW_LATENCY,
EFX_FW_VARIANT_PACKED_STREAM,
EFX_FW_VARIANT_HIGH_TX_RATE,
EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
EFX_FW_VARIANT_RULES_ENGINE,
EFX_FW_VARIANT_DPDK,
EFX_FW_VARIANT_DONT_CARE = 0xffffffff
} efx_fw_variant_t;
extern __checkReturn efx_rc_t
efx_nic_probe(
__in efx_nic_t *enp,
__in efx_fw_variant_t efv);
extern __checkReturn efx_rc_t
efx_nic_init(
__in efx_nic_t *enp);
extern __checkReturn efx_rc_t
efx_nic_reset(
__in efx_nic_t *enp);
extern __checkReturn boolean_t
efx_nic_hw_unavailable(
__in efx_nic_t *enp);
extern void
efx_nic_set_hw_unavailable(
__in efx_nic_t *enp);
#if EFSYS_OPT_DIAG
extern __checkReturn efx_rc_t
efx_nic_register_test(
__in efx_nic_t *enp);
#endif /* EFSYS_OPT_DIAG */
extern void
efx_nic_fini(
__in efx_nic_t *enp);
extern void
efx_nic_unprobe(
__in efx_nic_t *enp);
extern void
efx_nic_destroy(
__in efx_nic_t *enp);
#define EFX_PCIE_LINK_SPEED_GEN1 1
#define EFX_PCIE_LINK_SPEED_GEN2 2
#define EFX_PCIE_LINK_SPEED_GEN3 3
typedef enum efx_pcie_link_performance_e {
EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
} efx_pcie_link_performance_t;
extern __checkReturn efx_rc_t
efx_nic_calculate_pcie_link_bandwidth(
__in uint32_t pcie_link_width,
__in uint32_t pcie_link_gen,
__out uint32_t *bandwidth_mbpsp);
extern __checkReturn efx_rc_t
efx_nic_check_pcie_link_speed(
__in efx_nic_t *enp,
__in uint32_t pcie_link_width,
__in uint32_t pcie_link_gen,
__out efx_pcie_link_performance_t *resultp);
#if EFSYS_OPT_MCDI
#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
/* Huntington and Medford require MCDIv2 commands */
#define WITH_MCDI_V2 1
#endif
typedef struct efx_mcdi_req_s efx_mcdi_req_t;
typedef enum efx_mcdi_exception_e {
EFX_MCDI_EXCEPTION_MC_REBOOT,
EFX_MCDI_EXCEPTION_MC_BADASSERT,
} efx_mcdi_exception_t;
#if EFSYS_OPT_MCDI_LOGGING
typedef enum efx_log_msg_e {
EFX_LOG_INVALID,
EFX_LOG_MCDI_REQUEST,
EFX_LOG_MCDI_RESPONSE,
} efx_log_msg_t;
#endif /* EFSYS_OPT_MCDI_LOGGING */
typedef struct efx_mcdi_transport_s {
void *emt_context;
efsys_mem_t *emt_dma_mem;
void (*emt_execute)(void *, efx_mcdi_req_t *);
void (*emt_ev_cpl)(void *);
void (*emt_exception)(void *, efx_mcdi_exception_t);
#if EFSYS_OPT_MCDI_LOGGING
void (*emt_logger)(void *, efx_log_msg_t,
void *, size_t, void *, size_t);
#endif /* EFSYS_OPT_MCDI_LOGGING */
#if EFSYS_OPT_MCDI_PROXY_AUTH
void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
} efx_mcdi_transport_t;
extern __checkReturn efx_rc_t
efx_mcdi_init(
__in efx_nic_t *enp,
__in const efx_mcdi_transport_t *mtp);
extern __checkReturn efx_rc_t
efx_mcdi_reboot(
__in efx_nic_t *enp);
void
efx_mcdi_new_epoch(
__in efx_nic_t *enp);
extern void
efx_mcdi_get_timeout(
__in efx_nic_t *enp,
__in efx_mcdi_req_t *emrp,
__out uint32_t *usec_timeoutp);
extern void
efx_mcdi_request_start(
__in efx_nic_t *enp,
__in efx_mcdi_req_t *emrp,
__in boolean_t ev_cpl);
extern __checkReturn boolean_t
efx_mcdi_request_poll(
__in efx_nic_t *enp);
extern __checkReturn boolean_t
efx_mcdi_request_abort(
__in efx_nic_t *enp);
extern void
efx_mcdi_fini(
__in efx_nic_t *enp);
#endif /* EFSYS_OPT_MCDI */
/* INTR */
#define EFX_NINTR_SIENA 1024
typedef enum efx_intr_type_e {
EFX_INTR_INVALID = 0,
EFX_INTR_LINE,
EFX_INTR_MESSAGE,
EFX_INTR_NTYPES
} efx_intr_type_t;
#define EFX_INTR_SIZE (sizeof (efx_oword_t))
extern __checkReturn efx_rc_t
efx_intr_init(
__in efx_nic_t *enp,
__in efx_intr_type_t type,
__in efsys_mem_t *esmp);
extern void
efx_intr_enable(
__in efx_nic_t *enp);
extern void
efx_intr_disable(
__in efx_nic_t *enp);
extern void
efx_intr_disable_unlocked(
__in efx_nic_t *enp);
#define EFX_INTR_NEVQS 32
extern __checkReturn efx_rc_t
efx_intr_trigger(
__in efx_nic_t *enp,
__in unsigned int level);
extern void
efx_intr_status_line(
__in efx_nic_t *enp,
__out boolean_t *fatalp,
__out uint32_t *maskp);
extern void
efx_intr_status_message(
__in efx_nic_t *enp,
__in unsigned int message,
__out boolean_t *fatalp);
extern void
efx_intr_fatal(
__in efx_nic_t *enp);
extern void
efx_intr_fini(
__in efx_nic_t *enp);
/* MAC */
#if EFSYS_OPT_MAC_STATS
/* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
typedef enum efx_mac_stat_e {
EFX_MAC_RX_OCTETS,
EFX_MAC_RX_PKTS,
EFX_MAC_RX_UNICST_PKTS,
EFX_MAC_RX_MULTICST_PKTS,
EFX_MAC_RX_BRDCST_PKTS,
EFX_MAC_RX_PAUSE_PKTS,
EFX_MAC_RX_LE_64_PKTS,
EFX_MAC_RX_65_TO_127_PKTS,
EFX_MAC_RX_128_TO_255_PKTS,
EFX_MAC_RX_256_TO_511_PKTS,
EFX_MAC_RX_512_TO_1023_PKTS,
EFX_MAC_RX_1024_TO_15XX_PKTS,
EFX_MAC_RX_GE_15XX_PKTS,
EFX_MAC_RX_ERRORS,
EFX_MAC_RX_FCS_ERRORS,
EFX_MAC_RX_DROP_EVENTS,
EFX_MAC_RX_FALSE_CARRIER_ERRORS,
EFX_MAC_RX_SYMBOL_ERRORS,
EFX_MAC_RX_ALIGN_ERRORS,
EFX_MAC_RX_INTERNAL_ERRORS,
EFX_MAC_RX_JABBER_PKTS,
EFX_MAC_RX_LANE0_CHAR_ERR,
EFX_MAC_RX_LANE1_CHAR_ERR,
EFX_MAC_RX_LANE2_CHAR_ERR,
EFX_MAC_RX_LANE3_CHAR_ERR,
EFX_MAC_RX_LANE0_DISP_ERR,
EFX_MAC_RX_LANE1_DISP_ERR,
EFX_MAC_RX_LANE2_DISP_ERR,
EFX_MAC_RX_LANE3_DISP_ERR,
EFX_MAC_RX_MATCH_FAULT,
EFX_MAC_RX_NODESC_DROP_CNT,
EFX_MAC_TX_OCTETS,
EFX_MAC_TX_PKTS,
EFX_MAC_TX_UNICST_PKTS,
EFX_MAC_TX_MULTICST_PKTS,
EFX_MAC_TX_BRDCST_PKTS,
EFX_MAC_TX_PAUSE_PKTS,
EFX_MAC_TX_LE_64_PKTS,
EFX_MAC_TX_65_TO_127_PKTS,
EFX_MAC_TX_128_TO_255_PKTS,
EFX_MAC_TX_256_TO_511_PKTS,
EFX_MAC_TX_512_TO_1023_PKTS,
EFX_MAC_TX_1024_TO_15XX_PKTS,
EFX_MAC_TX_GE_15XX_PKTS,
EFX_MAC_TX_ERRORS,
EFX_MAC_TX_SGL_COL_PKTS,
EFX_MAC_TX_MULT_COL_PKTS,
EFX_MAC_TX_EX_COL_PKTS,
EFX_MAC_TX_LATE_COL_PKTS,
EFX_MAC_TX_DEF_PKTS,
EFX_MAC_TX_EX_DEF_PKTS,
EFX_MAC_PM_TRUNC_BB_OVERFLOW,
EFX_MAC_PM_DISCARD_BB_OVERFLOW,
EFX_MAC_PM_TRUNC_VFIFO_FULL,
EFX_MAC_PM_DISCARD_VFIFO_FULL,
EFX_MAC_PM_TRUNC_QBB,
EFX_MAC_PM_DISCARD_QBB,
EFX_MAC_PM_DISCARD_MAPPING,
EFX_MAC_RXDP_Q_DISABLED_PKTS,
EFX_MAC_RXDP_DI_DROPPED_PKTS,
EFX_MAC_RXDP_STREAMING_PKTS,
EFX_MAC_RXDP_HLB_FETCH,
EFX_MAC_RXDP_HLB_WAIT,
EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
EFX_MAC_VADAPTER_RX_BAD_PACKETS,
EFX_MAC_VADAPTER_RX_BAD_BYTES,
EFX_MAC_VADAPTER_RX_OVERFLOW,
EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
EFX_MAC_VADAPTER_TX_BAD_PACKETS,
EFX_MAC_VADAPTER_TX_BAD_BYTES,
EFX_MAC_VADAPTER_TX_OVERFLOW,
EFX_MAC_FEC_UNCORRECTED_ERRORS,
EFX_MAC_FEC_CORRECTED_ERRORS,
EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
EFX_MAC_CTPIO_OVERFLOW_FAIL,
EFX_MAC_CTPIO_UNDERFLOW_FAIL,
EFX_MAC_CTPIO_TIMEOUT_FAIL,
EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
EFX_MAC_CTPIO_INVALID_WR_FAIL,
EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
EFX_MAC_CTPIO_RUNT_FALLBACK,
EFX_MAC_CTPIO_SUCCESS,
EFX_MAC_CTPIO_FALLBACK,
EFX_MAC_CTPIO_POISON,
EFX_MAC_CTPIO_ERASE,
EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
EFX_MAC_RXDP_HLB_IDLE,
EFX_MAC_RXDP_HLB_TIMEOUT,
EFX_MAC_NSTATS
} efx_mac_stat_t;
/* END MKCONFIG GENERATED EfxHeaderMacBlock */
#endif /* EFSYS_OPT_MAC_STATS */
typedef enum efx_link_mode_e {
EFX_LINK_UNKNOWN = 0,
EFX_LINK_DOWN,
EFX_LINK_10HDX,
EFX_LINK_10FDX,
EFX_LINK_100HDX,
EFX_LINK_100FDX,
EFX_LINK_1000HDX,
EFX_LINK_1000FDX,
EFX_LINK_10000FDX,
EFX_LINK_40000FDX,
EFX_LINK_25000FDX,
EFX_LINK_50000FDX,
EFX_LINK_100000FDX,
EFX_LINK_NMODES
} efx_link_mode_t;
#define EFX_MAC_ADDR_LEN 6
#define EFX_VNI_OR_VSID_LEN 3
#define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
#define EFX_MAC_MULTICAST_LIST_MAX 256
#define EFX_MAC_SDU_MAX 9202
#define EFX_MAC_PDU_ADJUSTMENT \
(/* EtherII */ 14 \
+ /* VLAN */ 4 \
+ /* CRC */ 4 \
+ /* bug16011 */ 16) \
#define EFX_MAC_PDU(_sdu) \
EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
/*
* Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
* the SDU rounded up slightly.
*/
#define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
#define EFX_MAC_PDU_MIN 60
#define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
extern __checkReturn efx_rc_t
efx_mac_pdu_get(
__in efx_nic_t *enp,
__out size_t *pdu);
extern __checkReturn efx_rc_t
efx_mac_pdu_set(
__in efx_nic_t *enp,
__in size_t pdu);
extern __checkReturn efx_rc_t
efx_mac_addr_set(
__in efx_nic_t *enp,
__in uint8_t *addr);
extern __checkReturn efx_rc_t
efx_mac_filter_set(
__in efx_nic_t *enp,
__in boolean_t all_unicst,
__in boolean_t mulcst,
__in boolean_t all_mulcst,
__in boolean_t brdcst);
extern __checkReturn efx_rc_t
efx_mac_multicast_list_set(
__in efx_nic_t *enp,
__in_ecount(6*count) uint8_t const *addrs,
__in int count);
extern __checkReturn efx_rc_t
efx_mac_filter_default_rxq_set(
__in efx_nic_t *enp,
__in efx_rxq_t *erp,
__in boolean_t using_rss);
extern void
efx_mac_filter_default_rxq_clear(
__in efx_nic_t *enp);
extern __checkReturn efx_rc_t
efx_mac_drain(
__in efx_nic_t *enp,
__in boolean_t enabled);
extern __checkReturn efx_rc_t
efx_mac_up(
__in efx_nic_t *enp,
__out boolean_t *mac_upp);
#define EFX_FCNTL_RESPOND 0x00000001
#define EFX_FCNTL_GENERATE 0x00000002
extern __checkReturn efx_rc_t
efx_mac_fcntl_set(
__in efx_nic_t *enp,
__in unsigned int fcntl,
__in boolean_t autoneg);
extern void
efx_mac_fcntl_get(
__in efx_nic_t *enp,
__out unsigned int *fcntl_wantedp,
__out unsigned int *fcntl_linkp);
#if EFSYS_OPT_MAC_STATS
#if EFSYS_OPT_NAMES
extern __checkReturn const char *
efx_mac_stat_name(
__in efx_nic_t *enp,
__in unsigned int id);
#endif /* EFSYS_OPT_NAMES */
#define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
#define EFX_MAC_STATS_MASK_NPAGES \
(EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \
EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
EFX_MAC_STATS_MASK_BITS_PER_PAGE)
/*
* Get mask of MAC statistics supported by the hardware.
*
* If mask_size is insufficient to return the mask, EINVAL error is
* returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
* (which is sizeof (uint32_t)) is sufficient.
*/
extern __checkReturn efx_rc_t
efx_mac_stats_get_mask(
__in efx_nic_t *enp,
__out_bcount(mask_size) uint32_t *maskp,
__in size_t mask_size);
#define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
(1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
extern __checkReturn efx_rc_t
efx_mac_stats_clear(
__in efx_nic_t *enp);
/*
* Upload mac statistics supported by the hardware into the given buffer.
*
* The DMA buffer must be 4Kbyte aligned and sized to hold at least
* efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
*
* The hardware will only DMA statistics that it understands (of course).
* Drivers should not make any assumptions about which statistics are
* supported, especially when the statistics are generated by firmware.
*
* Thus, drivers should zero this buffer before use, so that not-understood
* statistics read back as zero.
*/
extern __checkReturn efx_rc_t
efx_mac_stats_upload(
__in efx_nic_t *enp,
__in efsys_mem_t *esmp);
extern __checkReturn efx_rc_t
efx_mac_stats_periodic(
__in efx_nic_t *enp,
__in efsys_mem_t *esmp,
__in uint16_t period_ms,
__in boolean_t events);
extern __checkReturn efx_rc_t
efx_mac_stats_update(
__in efx_nic_t *enp,
__in efsys_mem_t *esmp,
__inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
__inout_opt uint32_t *generationp);
#endif /* EFSYS_OPT_MAC_STATS */
/* MON */
typedef enum efx_mon_type_e {
EFX_MON_INVALID = 0,
EFX_MON_SFC90X0,
EFX_MON_SFC91X0,
EFX_MON_SFC92X0,
EFX_MON_NTYPES
} efx_mon_type_t;
#if EFSYS_OPT_NAMES
extern const char *
efx_mon_name(
__in efx_nic_t *enp);
#endif /* EFSYS_OPT_NAMES */
extern __checkReturn efx_rc_t
efx_mon_init(
__in efx_nic_t *enp);
#if EFSYS_OPT_MON_STATS
#define EFX_MON_STATS_PAGE_SIZE 0x100
#define EFX_MON_MASK_ELEMENT_SIZE 32
/* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
typedef enum efx_mon_stat_e {
EFX_MON_STAT_CONTROLLER_TEMP,
EFX_MON_STAT_PHY_COMMON_TEMP,
EFX_MON_STAT_CONTROLLER_COOLING,
EFX_MON_STAT_PHY0_TEMP,
EFX_MON_STAT_PHY0_COOLING,
EFX_MON_STAT_PHY1_TEMP,
EFX_MON_STAT_PHY1_COOLING,
EFX_MON_STAT_IN_1V0,
EFX_MON_STAT_IN_1V2,
EFX_MON_STAT_IN_1V8,
EFX_MON_STAT_IN_2V5,
EFX_MON_STAT_IN_3V3,
EFX_MON_STAT_IN_12V0,
EFX_MON_STAT_IN_1V2A,
EFX_MON_STAT_IN_VREF,
EFX_MON_STAT_OUT_VAOE,
EFX_MON_STAT_AOE_TEMP,
EFX_MON_STAT_PSU_AOE_TEMP,
EFX_MON_STAT_PSU_TEMP,
EFX_MON_STAT_FAN_0,
EFX_MON_STAT_FAN_1,
EFX_MON_STAT_FAN_2,
EFX_MON_STAT_FAN_3,
EFX_MON_STAT_FAN_4,
EFX_MON_STAT_IN_VAOE,
EFX_MON_STAT_OUT_IAOE,
EFX_MON_STAT_IN_IAOE,
EFX_MON_STAT_NIC_POWER,
EFX_MON_STAT_IN_0V9,
EFX_MON_STAT_IN_I0V9,
EFX_MON_STAT_IN_I1V2,
EFX_MON_STAT_IN_0V9_ADC,
EFX_MON_STAT_CONTROLLER_2_TEMP,
EFX_MON_STAT_VREG_INTERNAL_TEMP,
EFX_MON_STAT_VREG_0V9_TEMP,
EFX_MON_STAT_VREG_1V2_TEMP,
EFX_MON_STAT_CONTROLLER_VPTAT,
EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
EFX_MON_STAT_AMBIENT_TEMP,
EFX_MON_STAT_AIRFLOW,
EFX_MON_STAT_VDD08D_VSS08D_CSR,
EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
EFX_MON_STAT_HOTPOINT_TEMP,
EFX_MON_STAT_PHY_POWER_PORT0,
EFX_MON_STAT_PHY_POWER_PORT1,
EFX_MON_STAT_MUM_VCC,
EFX_MON_STAT_IN_0V9_A,
EFX_MON_STAT_IN_I0V9_A,
EFX_MON_STAT_VREG_0V9_A_TEMP,
EFX_MON_STAT_IN_0V9_B,
EFX_MON_STAT_IN_I0V9_B,
EFX_MON_STAT_VREG_0V9_B_TEMP,
EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
EFX_MON_STAT_SODIMM_VOUT,
EFX_MON_STAT_SODIMM_0_TEMP,
EFX_MON_STAT_SODIMM_1_TEMP,
EFX_MON_STAT_PHY0_VCC,
EFX_MON_STAT_PHY1_VCC,
EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
EFX_MON_STAT_BOARD_FRONT_TEMP,
EFX_MON_STAT_BOARD_BACK_TEMP,
EFX_MON_STAT_IN_I1V8,
EFX_MON_STAT_IN_I2V5,
EFX_MON_STAT_IN_I3V3,
EFX_MON_STAT_IN_I12V0,
EFX_MON_STAT_IN_1V3,
EFX_MON_STAT_IN_I1V3,
EFX_MON_NSTATS
} efx_mon_stat_t;
/* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
typedef enum efx_mon_stat_state_e {
EFX_MON_STAT_STATE_OK = 0,
EFX_MON_STAT_STATE_WARNING = 1,
EFX_MON_STAT_STATE_FATAL = 2,
EFX_MON_STAT_STATE_BROKEN = 3,
EFX_MON_STAT_STATE_NO_READING = 4,
} efx_mon_stat_state_t;
typedef enum efx_mon_stat_unit_e {
EFX_MON_STAT_UNIT_UNKNOWN = 0,
EFX_MON_STAT_UNIT_BOOL,
EFX_MON_STAT_UNIT_TEMP_C,
EFX_MON_STAT_UNIT_VOLTAGE_MV,
EFX_MON_STAT_UNIT_CURRENT_MA,
EFX_MON_STAT_UNIT_POWER_W,
EFX_MON_STAT_UNIT_RPM,
EFX_MON_NUNITS
} efx_mon_stat_unit_t;
typedef struct efx_mon_stat_value_s {
uint16_t emsv_value;
efx_mon_stat_state_t emsv_state;
efx_mon_stat_unit_t emsv_unit;
} efx_mon_stat_value_t;
typedef struct efx_mon_limit_value_s {
uint16_t emlv_warning_min;
uint16_t emlv_warning_max;
uint16_t emlv_fatal_min;
uint16_t emlv_fatal_max;
} efx_mon_stat_limits_t;
typedef enum efx_mon_stat_portmask_e {
EFX_MON_STAT_PORTMAP_NONE = 0,
EFX_MON_STAT_PORTMAP_PORT0 = 1,
EFX_MON_STAT_PORTMAP_PORT1 = 2,
EFX_MON_STAT_PORTMAP_PORT2 = 3,
EFX_MON_STAT_PORTMAP_PORT3 = 4,
EFX_MON_STAT_PORTMAP_ALL = (-1),
EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
} efx_mon_stat_portmask_t;
#if EFSYS_OPT_NAMES
extern const char *
efx_mon_stat_name(
__in efx_nic_t *enp,
__in efx_mon_stat_t id);
extern const char *
efx_mon_stat_description(
__in efx_nic_t *enp,
__in efx_mon_stat_t id);
#endif /* EFSYS_OPT_NAMES */
extern __checkReturn boolean_t
efx_mon_mcdi_to_efx_stat(
__in int mcdi_index,
__out efx_mon_stat_t *statp);
extern __checkReturn boolean_t
efx_mon_get_stat_unit(
__in efx_mon_stat_t stat,
__out efx_mon_stat_unit_t *unitp);
extern __checkReturn boolean_t
efx_mon_get_stat_portmap(
__in efx_mon_stat_t stat,
__out efx_mon_stat_portmask_t *maskp);
extern __checkReturn efx_rc_t
efx_mon_stats_update(
__in efx_nic_t *enp,
__in efsys_mem_t *esmp,
__inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
extern __checkReturn efx_rc_t
efx_mon_limits_update(
__in efx_nic_t *enp,
__inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values);
#endif /* EFSYS_OPT_MON_STATS */
extern void
efx_mon_fini(
__in efx_nic_t *enp);
/* PHY */
extern __checkReturn efx_rc_t
efx_phy_verify(
__in efx_nic_t *enp);
#if EFSYS_OPT_PHY_LED_CONTROL
typedef enum efx_phy_led_mode_e {
EFX_PHY_LED_DEFAULT = 0,
EFX_PHY_LED_OFF,
EFX_PHY_LED_ON,
EFX_PHY_LED_FLASH,
EFX_PHY_LED_NMODES
} efx_phy_led_mode_t;
extern __checkReturn efx_rc_t
efx_phy_led_set(
__in efx_nic_t *enp,
__in efx_phy_led_mode_t mode);
#endif /* EFSYS_OPT_PHY_LED_CONTROL */
extern __checkReturn efx_rc_t
efx_port_init(
__in efx_nic_t *enp);
#if EFSYS_OPT_LOOPBACK
typedef enum efx_loopback_type_e {
EFX_LOOPBACK_OFF = 0,
EFX_LOOPBACK_DATA = 1,
EFX_LOOPBACK_GMAC = 2,
EFX_LOOPBACK_XGMII = 3,
EFX_LOOPBACK_XGXS = 4,
EFX_LOOPBACK_XAUI = 5,
EFX_LOOPBACK_GMII = 6,
EFX_LOOPBACK_SGMII = 7,
EFX_LOOPBACK_XGBR = 8,
EFX_LOOPBACK_XFI = 9,
EFX_LOOPBACK_XAUI_FAR = 10,
EFX_LOOPBACK_GMII_FAR = 11,
EFX_LOOPBACK_SGMII_FAR = 12,
EFX_LOOPBACK_XFI_FAR = 13,
EFX_LOOPBACK_GPHY = 14,
EFX_LOOPBACK_PHY_XS = 15,
EFX_LOOPBACK_PCS = 16,
EFX_LOOPBACK_PMA_PMD = 17,
EFX_LOOPBACK_XPORT = 18,
EFX_LOOPBACK_XGMII_WS = 19,
EFX_LOOPBACK_XAUI_WS = 20,
EFX_LOOPBACK_XAUI_WS_FAR = 21,
EFX_LOOPBACK_XAUI_WS_NEAR = 22,
EFX_LOOPBACK_GMII_WS = 23,
EFX_LOOPBACK_XFI_WS = 24,
EFX_LOOPBACK_XFI_WS_FAR = 25,
EFX_LOOPBACK_PHYXS_WS = 26,
EFX_LOOPBACK_PMA_INT = 27,
EFX_LOOPBACK_SD_NEAR = 28,
EFX_LOOPBACK_SD_FAR = 29,
EFX_LOOPBACK_PMA_INT_WS = 30,
EFX_LOOPBACK_SD_FEP2_WS = 31,
EFX_LOOPBACK_SD_FEP1_5_WS = 32,
EFX_LOOPBACK_SD_FEP_WS = 33,
EFX_LOOPBACK_SD_FES_WS = 34,
EFX_LOOPBACK_AOE_INT_NEAR = 35,
EFX_LOOPBACK_DATA_WS = 36,
EFX_LOOPBACK_FORCE_EXT_LINK = 37,
EFX_LOOPBACK_NTYPES
} efx_loopback_type_t;
typedef enum efx_loopback_kind_e {
EFX_LOOPBACK_KIND_OFF = 0,
EFX_LOOPBACK_KIND_ALL,
EFX_LOOPBACK_KIND_MAC,
EFX_LOOPBACK_KIND_PHY,
EFX_LOOPBACK_NKINDS
} efx_loopback_kind_t;
extern void
efx_loopback_mask(
__in efx_loopback_kind_t loopback_kind,
__out efx_qword_t *maskp);
extern __checkReturn efx_rc_t
efx_port_loopback_set(
__in efx_nic_t *enp,
__in efx_link_mode_t link_mode,
__in efx_loopback_type_t type);
#if EFSYS_OPT_NAMES
extern __checkReturn const char *
efx_loopback_type_name(
__in efx_nic_t *enp,
__in efx_loopback_type_t type);
#endif /* EFSYS_OPT_NAMES */
#endif /* EFSYS_OPT_LOOPBACK */
extern __checkReturn efx_rc_t
efx_port_poll(
__in efx_nic_t *enp,
__out_opt efx_link_mode_t *link_modep);
extern void
efx_port_fini(
__in efx_nic_t *enp);
typedef enum efx_phy_cap_type_e {
EFX_PHY_CAP_INVALID = 0,
EFX_PHY_CAP_10HDX,
EFX_PHY_CAP_10FDX,
EFX_PHY_CAP_100HDX,
EFX_PHY_CAP_100FDX,
EFX_PHY_CAP_1000HDX,
EFX_PHY_CAP_1000FDX,
EFX_PHY_CAP_10000FDX,
EFX_PHY_CAP_PAUSE,
EFX_PHY_CAP_ASYM,
EFX_PHY_CAP_AN,
EFX_PHY_CAP_40000FDX,
EFX_PHY_CAP_DDM,
EFX_PHY_CAP_100000FDX,
EFX_PHY_CAP_25000FDX,
EFX_PHY_CAP_50000FDX,
EFX_PHY_CAP_BASER_FEC,
EFX_PHY_CAP_BASER_FEC_REQUESTED,
EFX_PHY_CAP_RS_FEC,
EFX_PHY_CAP_RS_FEC_REQUESTED,
EFX_PHY_CAP_25G_BASER_FEC,
EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
EFX_PHY_CAP_NTYPES
} efx_phy_cap_type_t;
#define EFX_PHY_CAP_CURRENT 0x00000000
#define EFX_PHY_CAP_DEFAULT 0x00000001
#define EFX_PHY_CAP_PERM 0x00000002
extern void
efx_phy_adv_cap_get(
__in efx_nic_t *enp,
__in uint32_t flag,
__out uint32_t *maskp);
extern __checkReturn efx_rc_t