-
Notifications
You must be signed in to change notification settings - Fork 2
/
dpaa2_eventdev.c
1101 lines (910 loc) · 26.8 KB
/
dpaa2_eventdev.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/* SPDX-License-Identifier: BSD-3-Clause
* Copyright 2017,2019 NXP
*/
#include <assert.h>
#include <stdio.h>
#include <stdbool.h>
#include <errno.h>
#include <stdint.h>
#include <string.h>
#include <sys/epoll.h>
#include <rte_atomic.h>
#include <rte_byteorder.h>
#include <rte_common.h>
#include <rte_debug.h>
#include <rte_dev.h>
#include <rte_eal.h>
#include <rte_fslmc.h>
#include <rte_lcore.h>
#include <rte_log.h>
#include <rte_malloc.h>
#include <rte_memcpy.h>
#include <rte_memory.h>
#include <rte_pci.h>
#include <rte_bus_vdev.h>
#include <rte_ethdev_driver.h>
#include <rte_cryptodev.h>
#include <rte_event_eth_rx_adapter.h>
#include <fslmc_vfio.h>
#include <dpaa2_hw_pvt.h>
#include <dpaa2_hw_mempool.h>
#include <dpaa2_hw_dpio.h>
#include <dpaa2_ethdev.h>
#ifdef RTE_LIBRTE_SECURITY
#include <dpaa2_sec_event.h>
#endif
#include "dpaa2_eventdev.h"
#include "dpaa2_eventdev_logs.h"
#include <portal/dpaa2_hw_pvt.h>
#include <mc/fsl_dpci.h>
/* Clarifications
* Evendev = SoC Instance
* Eventport = DPIO Instance
* Eventqueue = DPCON Instance
* 1 Eventdev can have N Eventqueue
* Soft Event Flow is DPCI Instance
*/
/* Dynamic logging identified for mempool */
int dpaa2_logtype_event;
static uint16_t
dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[],
uint16_t nb_events)
{
struct dpaa2_port *dpaa2_portal = port;
struct dpaa2_dpio_dev *dpio_dev;
uint32_t queue_id = ev[0].queue_id;
struct dpaa2_eventq *evq_info;
uint32_t fqid;
struct qbman_swp *swp;
struct qbman_fd fd_arr[MAX_TX_RING_SLOTS];
uint32_t loop, frames_to_send;
struct qbman_eq_desc eqdesc[MAX_TX_RING_SLOTS];
uint16_t num_tx = 0;
int i, n, ret;
uint8_t channel_index;
if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
/* Affine current thread context to a qman portal */
ret = dpaa2_affine_qbman_swp();
if (ret < 0) {
DPAA2_EVENTDEV_ERR("Failure in affining portal");
return 0;
}
}
/* todo - dpaa2_portal shall have dpio_dev - no per thread variable */
dpio_dev = DPAA2_PER_LCORE_DPIO;
swp = DPAA2_PER_LCORE_PORTAL;
if (likely(dpaa2_portal->is_port_linked))
goto skip_linking;
/* Create mapping between portal and channel to receive packets */
for (i = 0; i < DPAA2_EVENT_MAX_QUEUES; i++) {
evq_info = &dpaa2_portal->evq_info[i];
if (!evq_info->event_port)
continue;
ret = dpio_add_static_dequeue_channel(dpio_dev->dpio,
CMD_PRI_LOW,
dpio_dev->token,
evq_info->dpcon->dpcon_id,
&channel_index);
if (ret < 0) {
DPAA2_EVENTDEV_ERR(
"Static dequeue config failed: err(%d)", ret);
goto err;
}
qbman_swp_push_set(swp, channel_index, 1);
evq_info->dpcon->channel_index = channel_index;
}
dpaa2_portal->is_port_linked = true;
skip_linking:
evq_info = &dpaa2_portal->evq_info[queue_id];
while (nb_events) {
frames_to_send = (nb_events > dpaa2_eqcr_size) ?
dpaa2_eqcr_size : nb_events;
for (loop = 0; loop < frames_to_send; loop++) {
const struct rte_event *event = &ev[num_tx + loop];
if (event->sched_type != RTE_SCHED_TYPE_ATOMIC)
fqid = evq_info->dpci->rx_queue[
DPAA2_EVENT_DPCI_PARALLEL_QUEUE].fqid;
else
fqid = evq_info->dpci->rx_queue[
DPAA2_EVENT_DPCI_ATOMIC_QUEUE].fqid;
/* Prepare enqueue descriptor */
qbman_eq_desc_clear(&eqdesc[loop]);
qbman_eq_desc_set_fq(&eqdesc[loop], fqid);
qbman_eq_desc_set_no_orp(&eqdesc[loop], 0);
qbman_eq_desc_set_response(&eqdesc[loop], 0, 0);
if (event->sched_type == RTE_SCHED_TYPE_ATOMIC
&& event->mbuf->seqn) {
uint8_t dqrr_index = event->mbuf->seqn - 1;
qbman_eq_desc_set_dca(&eqdesc[loop], 1,
dqrr_index, 0);
DPAA2_PER_LCORE_DQRR_SIZE--;
DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dqrr_index);
}
memset(&fd_arr[loop], 0, sizeof(struct qbman_fd));
/*
* todo - need to align with hw context data
* to avoid copy
*/
struct rte_event *ev_temp = rte_malloc(NULL,
sizeof(struct rte_event), 0);
if (!ev_temp) {
if (!loop)
return num_tx;
frames_to_send = loop;
DPAA2_EVENTDEV_ERR(
"Unable to allocate event object");
goto send_partial;
}
rte_memcpy(ev_temp, event, sizeof(struct rte_event));
DPAA2_SET_FD_ADDR((&fd_arr[loop]), (size_t)ev_temp);
DPAA2_SET_FD_LEN((&fd_arr[loop]),
sizeof(struct rte_event));
}
send_partial:
loop = 0;
while (loop < frames_to_send) {
loop += qbman_swp_enqueue_multiple_desc(swp,
&eqdesc[loop], &fd_arr[loop],
frames_to_send - loop);
}
num_tx += frames_to_send;
nb_events -= frames_to_send;
}
return num_tx;
err:
for (n = 0; n < i; n++) {
evq_info = &dpaa2_portal->evq_info[n];
if (!evq_info->event_port)
continue;
qbman_swp_push_set(swp, evq_info->dpcon->channel_index, 0);
dpio_remove_static_dequeue_channel(dpio_dev->dpio, 0,
dpio_dev->token,
evq_info->dpcon->dpcon_id);
}
return 0;
}
static uint16_t
dpaa2_eventdev_enqueue(void *port, const struct rte_event *ev)
{
return dpaa2_eventdev_enqueue_burst(port, ev, 1);
}
static void dpaa2_eventdev_dequeue_wait(uint64_t timeout_ticks)
{
struct epoll_event epoll_ev;
qbman_swp_interrupt_clear_status(DPAA2_PER_LCORE_PORTAL,
QBMAN_SWP_INTERRUPT_DQRI);
epoll_wait(DPAA2_PER_LCORE_DPIO->epoll_fd,
&epoll_ev, 1, timeout_ticks);
}
static void dpaa2_eventdev_process_parallel(struct qbman_swp *swp,
const struct qbman_fd *fd,
const struct qbman_result *dq,
struct dpaa2_queue *rxq,
struct rte_event *ev)
{
struct rte_event *ev_temp =
(struct rte_event *)(size_t)DPAA2_GET_FD_ADDR(fd);
RTE_SET_USED(rxq);
rte_memcpy(ev, ev_temp, sizeof(struct rte_event));
rte_free(ev_temp);
qbman_swp_dqrr_consume(swp, dq);
}
static void dpaa2_eventdev_process_atomic(struct qbman_swp *swp,
const struct qbman_fd *fd,
const struct qbman_result *dq,
struct dpaa2_queue *rxq,
struct rte_event *ev)
{
struct rte_event *ev_temp =
(struct rte_event *)(size_t)DPAA2_GET_FD_ADDR(fd);
uint8_t dqrr_index = qbman_get_dqrr_idx(dq);
RTE_SET_USED(swp);
RTE_SET_USED(rxq);
rte_memcpy(ev, ev_temp, sizeof(struct rte_event));
rte_free(ev_temp);
ev->mbuf->seqn = dqrr_index + 1;
DPAA2_PER_LCORE_DQRR_SIZE++;
DPAA2_PER_LCORE_DQRR_HELD |= 1 << dqrr_index;
DPAA2_PER_LCORE_DQRR_MBUF(dqrr_index) = ev->mbuf;
}
static uint16_t
dpaa2_eventdev_dequeue_burst(void *port, struct rte_event ev[],
uint16_t nb_events, uint64_t timeout_ticks)
{
const struct qbman_result *dq;
struct dpaa2_dpio_dev *dpio_dev = NULL;
struct dpaa2_port *dpaa2_portal = port;
struct dpaa2_eventq *evq_info;
struct qbman_swp *swp;
const struct qbman_fd *fd;
struct dpaa2_queue *rxq;
int num_pkts = 0, ret, i = 0, n;
uint8_t channel_index;
if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
/* Affine current thread context to a qman portal */
ret = dpaa2_affine_qbman_swp();
if (ret < 0) {
DPAA2_EVENTDEV_ERR("Failure in affining portal");
return 0;
}
}
dpio_dev = DPAA2_PER_LCORE_DPIO;
swp = DPAA2_PER_LCORE_PORTAL;
if (likely(dpaa2_portal->is_port_linked))
goto skip_linking;
/* Create mapping between portal and channel to receive packets */
for (i = 0; i < DPAA2_EVENT_MAX_QUEUES; i++) {
evq_info = &dpaa2_portal->evq_info[i];
if (!evq_info->event_port)
continue;
ret = dpio_add_static_dequeue_channel(dpio_dev->dpio,
CMD_PRI_LOW,
dpio_dev->token,
evq_info->dpcon->dpcon_id,
&channel_index);
if (ret < 0) {
DPAA2_EVENTDEV_ERR(
"Static dequeue config failed: err(%d)", ret);
goto err;
}
qbman_swp_push_set(swp, channel_index, 1);
evq_info->dpcon->channel_index = channel_index;
}
dpaa2_portal->is_port_linked = true;
skip_linking:
/* Check if there are atomic contexts to be released */
while (DPAA2_PER_LCORE_DQRR_SIZE) {
if (DPAA2_PER_LCORE_DQRR_HELD & (1 << i)) {
qbman_swp_dqrr_idx_consume(swp, i);
DPAA2_PER_LCORE_DQRR_SIZE--;
DPAA2_PER_LCORE_DQRR_MBUF(i)->seqn =
DPAA2_INVALID_MBUF_SEQN;
}
i++;
}
DPAA2_PER_LCORE_DQRR_HELD = 0;
do {
dq = qbman_swp_dqrr_next(swp);
if (!dq) {
if (!num_pkts && timeout_ticks) {
dpaa2_eventdev_dequeue_wait(timeout_ticks);
timeout_ticks = 0;
continue;
}
return num_pkts;
}
qbman_swp_prefetch_dqrr_next(swp);
fd = qbman_result_DQ_fd(dq);
rxq = (struct dpaa2_queue *)(size_t)qbman_result_DQ_fqd_ctx(dq);
if (rxq) {
rxq->cb(swp, fd, dq, rxq, &ev[num_pkts]);
} else {
qbman_swp_dqrr_consume(swp, dq);
DPAA2_EVENTDEV_ERR("Null Return VQ received");
return 0;
}
num_pkts++;
} while (num_pkts < nb_events);
return num_pkts;
err:
for (n = 0; n < i; n++) {
evq_info = &dpaa2_portal->evq_info[n];
if (!evq_info->event_port)
continue;
qbman_swp_push_set(swp, evq_info->dpcon->channel_index, 0);
dpio_remove_static_dequeue_channel(dpio_dev->dpio, 0,
dpio_dev->token,
evq_info->dpcon->dpcon_id);
}
return 0;
}
static uint16_t
dpaa2_eventdev_dequeue(void *port, struct rte_event *ev,
uint64_t timeout_ticks)
{
return dpaa2_eventdev_dequeue_burst(port, ev, 1, timeout_ticks);
}
static void
dpaa2_eventdev_info_get(struct rte_eventdev *dev,
struct rte_event_dev_info *dev_info)
{
struct dpaa2_eventdev *priv = dev->data->dev_private;
EVENTDEV_INIT_FUNC_TRACE();
RTE_SET_USED(dev);
memset(dev_info, 0, sizeof(struct rte_event_dev_info));
dev_info->min_dequeue_timeout_ns =
DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT;
dev_info->max_dequeue_timeout_ns =
DPAA2_EVENT_MAX_DEQUEUE_TIMEOUT;
dev_info->dequeue_timeout_ns =
DPAA2_EVENT_PORT_DEQUEUE_TIMEOUT_NS;
dev_info->max_event_queues = priv->max_event_queues;
dev_info->max_event_queue_flows =
DPAA2_EVENT_MAX_QUEUE_FLOWS;
dev_info->max_event_queue_priority_levels =
DPAA2_EVENT_MAX_QUEUE_PRIORITY_LEVELS;
dev_info->max_event_priority_levels =
DPAA2_EVENT_MAX_EVENT_PRIORITY_LEVELS;
dev_info->max_event_ports = rte_fslmc_get_device_count(DPAA2_IO);
/* we only support dpio up to number of cores */
if (dev_info->max_event_ports > rte_lcore_count())
dev_info->max_event_ports = rte_lcore_count();
dev_info->max_event_port_dequeue_depth =
DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH;
dev_info->max_event_port_enqueue_depth =
DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH;
dev_info->max_num_events = DPAA2_EVENT_MAX_NUM_EVENTS;
dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
RTE_EVENT_DEV_CAP_BURST_MODE|
RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK |
RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT |
RTE_EVENT_DEV_CAP_NONSEQ_MODE;
}
static int
dpaa2_eventdev_configure(const struct rte_eventdev *dev)
{
struct dpaa2_eventdev *priv = dev->data->dev_private;
struct rte_event_dev_config *conf = &dev->data->dev_conf;
EVENTDEV_INIT_FUNC_TRACE();
priv->nb_event_queues = conf->nb_event_queues;
priv->nb_event_ports = conf->nb_event_ports;
priv->nb_event_queue_flows = conf->nb_event_queue_flows;
priv->nb_event_port_dequeue_depth = conf->nb_event_port_dequeue_depth;
priv->nb_event_port_enqueue_depth = conf->nb_event_port_enqueue_depth;
priv->event_dev_cfg = conf->event_dev_cfg;
/* Check dequeue timeout method is per dequeue or global */
if (priv->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT) {
/*
* Use timeout value as given in dequeue operation.
* So invalidating this timeout value.
*/
priv->dequeue_timeout_ns = 0;
} else if (conf->dequeue_timeout_ns == 0) {
priv->dequeue_timeout_ns = DPAA2_EVENT_PORT_DEQUEUE_TIMEOUT_NS;
} else {
priv->dequeue_timeout_ns = conf->dequeue_timeout_ns;
}
DPAA2_EVENTDEV_DEBUG("Configured eventdev devid=%d",
dev->data->dev_id);
return 0;
}
static int
dpaa2_eventdev_start(struct rte_eventdev *dev)
{
EVENTDEV_INIT_FUNC_TRACE();
RTE_SET_USED(dev);
return 0;
}
static void
dpaa2_eventdev_stop(struct rte_eventdev *dev)
{
EVENTDEV_INIT_FUNC_TRACE();
RTE_SET_USED(dev);
}
static int
dpaa2_eventdev_close(struct rte_eventdev *dev)
{
EVENTDEV_INIT_FUNC_TRACE();
RTE_SET_USED(dev);
return 0;
}
static void
dpaa2_eventdev_queue_def_conf(struct rte_eventdev *dev, uint8_t queue_id,
struct rte_event_queue_conf *queue_conf)
{
EVENTDEV_INIT_FUNC_TRACE();
RTE_SET_USED(dev);
RTE_SET_USED(queue_id);
RTE_SET_USED(queue_conf);
queue_conf->nb_atomic_flows = DPAA2_EVENT_QUEUE_ATOMIC_FLOWS;
queue_conf->schedule_type = RTE_SCHED_TYPE_PARALLEL;
queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
}
static int
dpaa2_eventdev_queue_setup(struct rte_eventdev *dev, uint8_t queue_id,
const struct rte_event_queue_conf *queue_conf)
{
struct dpaa2_eventdev *priv = dev->data->dev_private;
struct dpaa2_eventq *evq_info = &priv->evq_info[queue_id];
EVENTDEV_INIT_FUNC_TRACE();
switch (queue_conf->schedule_type) {
case RTE_SCHED_TYPE_PARALLEL:
case RTE_SCHED_TYPE_ATOMIC:
break;
case RTE_SCHED_TYPE_ORDERED:
DPAA2_EVENTDEV_ERR("Schedule type is not supported.");
return -1;
}
evq_info->event_queue_cfg = queue_conf->event_queue_cfg;
evq_info->event_queue_id = queue_id;
return 0;
}
static void
dpaa2_eventdev_queue_release(struct rte_eventdev *dev, uint8_t queue_id)
{
EVENTDEV_INIT_FUNC_TRACE();
RTE_SET_USED(dev);
RTE_SET_USED(queue_id);
}
static void
dpaa2_eventdev_port_def_conf(struct rte_eventdev *dev, uint8_t port_id,
struct rte_event_port_conf *port_conf)
{
EVENTDEV_INIT_FUNC_TRACE();
RTE_SET_USED(dev);
RTE_SET_USED(port_id);
port_conf->new_event_threshold =
DPAA2_EVENT_MAX_NUM_EVENTS;
port_conf->dequeue_depth =
DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH;
port_conf->enqueue_depth =
DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH;
port_conf->disable_implicit_release = 0;
}
static int
dpaa2_eventdev_port_setup(struct rte_eventdev *dev, uint8_t port_id,
const struct rte_event_port_conf *port_conf)
{
char event_port_name[32];
struct dpaa2_port *portal;
EVENTDEV_INIT_FUNC_TRACE();
RTE_SET_USED(port_conf);
sprintf(event_port_name, "event-port-%d", port_id);
portal = rte_malloc(event_port_name, sizeof(struct dpaa2_port), 0);
if (!portal) {
DPAA2_EVENTDEV_ERR("Memory allocation failure");
return -ENOMEM;
}
memset(portal, 0, sizeof(struct dpaa2_port));
dev->data->ports[port_id] = portal;
return 0;
}
static void
dpaa2_eventdev_port_release(void *port)
{
struct dpaa2_port *portal = port;
EVENTDEV_INIT_FUNC_TRACE();
/* TODO: Cleanup is required when ports are in linked state. */
if (portal->is_port_linked)
DPAA2_EVENTDEV_WARN("Event port must be unlinked before release");
if (portal)
rte_free(portal);
portal = NULL;
}
static int
dpaa2_eventdev_port_link(struct rte_eventdev *dev, void *port,
const uint8_t queues[], const uint8_t priorities[],
uint16_t nb_links)
{
struct dpaa2_eventdev *priv = dev->data->dev_private;
struct dpaa2_port *dpaa2_portal = port;
struct dpaa2_eventq *evq_info;
uint16_t i;
EVENTDEV_INIT_FUNC_TRACE();
RTE_SET_USED(priorities);
for (i = 0; i < nb_links; i++) {
evq_info = &priv->evq_info[queues[i]];
memcpy(&dpaa2_portal->evq_info[queues[i]], evq_info,
sizeof(struct dpaa2_eventq));
dpaa2_portal->evq_info[queues[i]].event_port = port;
dpaa2_portal->num_linked_evq++;
}
return (int)nb_links;
}
static int
dpaa2_eventdev_port_unlink(struct rte_eventdev *dev, void *port,
uint8_t queues[], uint16_t nb_unlinks)
{
struct dpaa2_port *dpaa2_portal = port;
int i;
struct dpaa2_dpio_dev *dpio_dev = NULL;
struct dpaa2_eventq *evq_info;
struct qbman_swp *swp;
EVENTDEV_INIT_FUNC_TRACE();
RTE_SET_USED(dev);
RTE_SET_USED(queues);
for (i = 0; i < nb_unlinks; i++) {
evq_info = &dpaa2_portal->evq_info[queues[i]];
if (DPAA2_PER_LCORE_DPIO && evq_info->dpcon) {
/* todo dpaa2_portal shall have dpio_dev-no per lcore*/
dpio_dev = DPAA2_PER_LCORE_DPIO;
swp = DPAA2_PER_LCORE_PORTAL;
qbman_swp_push_set(swp,
evq_info->dpcon->channel_index, 0);
dpio_remove_static_dequeue_channel(dpio_dev->dpio, 0,
dpio_dev->token,
evq_info->dpcon->dpcon_id);
}
memset(evq_info, 0, sizeof(struct dpaa2_eventq));
if (dpaa2_portal->num_linked_evq)
dpaa2_portal->num_linked_evq--;
}
if (!dpaa2_portal->num_linked_evq)
dpaa2_portal->is_port_linked = false;
return (int)nb_unlinks;
}
static int
dpaa2_eventdev_timeout_ticks(struct rte_eventdev *dev, uint64_t ns,
uint64_t *timeout_ticks)
{
uint32_t scale = 1000*1000;
EVENTDEV_INIT_FUNC_TRACE();
RTE_SET_USED(dev);
*timeout_ticks = ns / scale;
return 0;
}
static void
dpaa2_eventdev_dump(struct rte_eventdev *dev, FILE *f)
{
EVENTDEV_INIT_FUNC_TRACE();
RTE_SET_USED(dev);
RTE_SET_USED(f);
}
static int
dpaa2_eventdev_eth_caps_get(const struct rte_eventdev *dev,
const struct rte_eth_dev *eth_dev,
uint32_t *caps)
{
const char *ethdev_driver = eth_dev->device->driver->name;
EVENTDEV_INIT_FUNC_TRACE();
RTE_SET_USED(dev);
if (!strcmp(ethdev_driver, "net_dpaa2"))
*caps = RTE_EVENT_ETH_RX_ADAPTER_DPAA2_CAP;
else
*caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
return 0;
}
static int
dpaa2_eventdev_eth_queue_add_all(const struct rte_eventdev *dev,
const struct rte_eth_dev *eth_dev,
const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
{
struct dpaa2_eventdev *priv = dev->data->dev_private;
uint8_t ev_qid = queue_conf->ev.queue_id;
uint16_t dpcon_id = priv->evq_info[ev_qid].dpcon->dpcon_id;
int i, ret;
EVENTDEV_INIT_FUNC_TRACE();
for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
ret = dpaa2_eth_eventq_attach(eth_dev, i,
dpcon_id, queue_conf);
if (ret) {
DPAA2_EVENTDEV_ERR(
"Event queue attach failed: err(%d)", ret);
goto fail;
}
}
return 0;
fail:
for (i = (i - 1); i >= 0 ; i--)
dpaa2_eth_eventq_detach(eth_dev, i);
return ret;
}
static int
dpaa2_eventdev_eth_queue_add(const struct rte_eventdev *dev,
const struct rte_eth_dev *eth_dev,
int32_t rx_queue_id,
const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
{
struct dpaa2_eventdev *priv = dev->data->dev_private;
uint8_t ev_qid = queue_conf->ev.queue_id;
uint16_t dpcon_id = priv->evq_info[ev_qid].dpcon->dpcon_id;
int ret;
EVENTDEV_INIT_FUNC_TRACE();
if (rx_queue_id == -1)
return dpaa2_eventdev_eth_queue_add_all(dev,
eth_dev, queue_conf);
ret = dpaa2_eth_eventq_attach(eth_dev, rx_queue_id,
dpcon_id, queue_conf);
if (ret) {
DPAA2_EVENTDEV_ERR(
"Event queue attach failed: err(%d)", ret);
return ret;
}
return 0;
}
static int
dpaa2_eventdev_eth_queue_del_all(const struct rte_eventdev *dev,
const struct rte_eth_dev *eth_dev)
{
int i, ret;
EVENTDEV_INIT_FUNC_TRACE();
RTE_SET_USED(dev);
for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
ret = dpaa2_eth_eventq_detach(eth_dev, i);
if (ret) {
DPAA2_EVENTDEV_ERR(
"Event queue detach failed: err(%d)", ret);
return ret;
}
}
return 0;
}
static int
dpaa2_eventdev_eth_queue_del(const struct rte_eventdev *dev,
const struct rte_eth_dev *eth_dev,
int32_t rx_queue_id)
{
int ret;
EVENTDEV_INIT_FUNC_TRACE();
if (rx_queue_id == -1)
return dpaa2_eventdev_eth_queue_del_all(dev, eth_dev);
ret = dpaa2_eth_eventq_detach(eth_dev, rx_queue_id);
if (ret) {
DPAA2_EVENTDEV_ERR(
"Event queue detach failed: err(%d)", ret);
return ret;
}
return 0;
}
static int
dpaa2_eventdev_eth_start(const struct rte_eventdev *dev,
const struct rte_eth_dev *eth_dev)
{
EVENTDEV_INIT_FUNC_TRACE();
RTE_SET_USED(dev);
RTE_SET_USED(eth_dev);
return 0;
}
static int
dpaa2_eventdev_eth_stop(const struct rte_eventdev *dev,
const struct rte_eth_dev *eth_dev)
{
EVENTDEV_INIT_FUNC_TRACE();
RTE_SET_USED(dev);
RTE_SET_USED(eth_dev);
return 0;
}
#ifdef RTE_LIBRTE_SECURITY
static int
dpaa2_eventdev_crypto_caps_get(const struct rte_eventdev *dev,
const struct rte_cryptodev *cdev,
uint32_t *caps)
{
const char *name = cdev->data->name;
EVENTDEV_INIT_FUNC_TRACE();
RTE_SET_USED(dev);
if (!strncmp(name, "dpsec-", 6))
*caps = RTE_EVENT_CRYPTO_ADAPTER_DPAA2_CAP;
else
return -1;
return 0;
}
static int
dpaa2_eventdev_crypto_queue_add_all(const struct rte_eventdev *dev,
const struct rte_cryptodev *cryptodev,
const struct rte_event *ev)
{
struct dpaa2_eventdev *priv = dev->data->dev_private;
uint8_t ev_qid = ev->queue_id;
uint16_t dpcon_id = priv->evq_info[ev_qid].dpcon->dpcon_id;
int i, ret;
EVENTDEV_INIT_FUNC_TRACE();
for (i = 0; i < cryptodev->data->nb_queue_pairs; i++) {
ret = dpaa2_sec_eventq_attach(cryptodev, i,
dpcon_id, ev);
if (ret) {
DPAA2_EVENTDEV_ERR("dpaa2_sec_eventq_attach failed: ret %d\n",
ret);
goto fail;
}
}
return 0;
fail:
for (i = (i - 1); i >= 0 ; i--)
dpaa2_sec_eventq_detach(cryptodev, i);
return ret;
}
static int
dpaa2_eventdev_crypto_queue_add(const struct rte_eventdev *dev,
const struct rte_cryptodev *cryptodev,
int32_t rx_queue_id,
const struct rte_event *ev)
{
struct dpaa2_eventdev *priv = dev->data->dev_private;
uint8_t ev_qid = ev->queue_id;
uint16_t dpcon_id = priv->evq_info[ev_qid].dpcon->dpcon_id;
int ret;
EVENTDEV_INIT_FUNC_TRACE();
if (rx_queue_id == -1)
return dpaa2_eventdev_crypto_queue_add_all(dev,
cryptodev, ev);
ret = dpaa2_sec_eventq_attach(cryptodev, rx_queue_id,
dpcon_id, ev);
if (ret) {
DPAA2_EVENTDEV_ERR(
"dpaa2_sec_eventq_attach failed: ret: %d\n", ret);
return ret;
}
return 0;
}
static int
dpaa2_eventdev_crypto_queue_del_all(const struct rte_eventdev *dev,
const struct rte_cryptodev *cdev)
{
int i, ret;
EVENTDEV_INIT_FUNC_TRACE();
RTE_SET_USED(dev);
for (i = 0; i < cdev->data->nb_queue_pairs; i++) {
ret = dpaa2_sec_eventq_detach(cdev, i);
if (ret) {
DPAA2_EVENTDEV_ERR(
"dpaa2_sec_eventq_detach failed:ret %d\n", ret);
return ret;
}
}
return 0;
}
static int
dpaa2_eventdev_crypto_queue_del(const struct rte_eventdev *dev,
const struct rte_cryptodev *cryptodev,
int32_t rx_queue_id)
{
int ret;
EVENTDEV_INIT_FUNC_TRACE();
if (rx_queue_id == -1)
return dpaa2_eventdev_crypto_queue_del_all(dev, cryptodev);
ret = dpaa2_sec_eventq_detach(cryptodev, rx_queue_id);
if (ret) {
DPAA2_EVENTDEV_ERR(
"dpaa2_sec_eventq_detach failed: ret: %d\n", ret);
return ret;
}
return 0;
}
static int
dpaa2_eventdev_crypto_start(const struct rte_eventdev *dev,
const struct rte_cryptodev *cryptodev)
{
EVENTDEV_INIT_FUNC_TRACE();
RTE_SET_USED(dev);
RTE_SET_USED(cryptodev);
return 0;
}
static int
dpaa2_eventdev_crypto_stop(const struct rte_eventdev *dev,
const struct rte_cryptodev *cryptodev)
{
EVENTDEV_INIT_FUNC_TRACE();
RTE_SET_USED(dev);
RTE_SET_USED(cryptodev);
return 0;
}
#endif
static struct rte_eventdev_ops dpaa2_eventdev_ops = {
.dev_infos_get = dpaa2_eventdev_info_get,
.dev_configure = dpaa2_eventdev_configure,
.dev_start = dpaa2_eventdev_start,
.dev_stop = dpaa2_eventdev_stop,
.dev_close = dpaa2_eventdev_close,
.queue_def_conf = dpaa2_eventdev_queue_def_conf,
.queue_setup = dpaa2_eventdev_queue_setup,
.queue_release = dpaa2_eventdev_queue_release,
.port_def_conf = dpaa2_eventdev_port_def_conf,
.port_setup = dpaa2_eventdev_port_setup,
.port_release = dpaa2_eventdev_port_release,
.port_link = dpaa2_eventdev_port_link,
.port_unlink = dpaa2_eventdev_port_unlink,
.timeout_ticks = dpaa2_eventdev_timeout_ticks,
.dump = dpaa2_eventdev_dump,
.eth_rx_adapter_caps_get = dpaa2_eventdev_eth_caps_get,
.eth_rx_adapter_queue_add = dpaa2_eventdev_eth_queue_add,
.eth_rx_adapter_queue_del = dpaa2_eventdev_eth_queue_del,
.eth_rx_adapter_start = dpaa2_eventdev_eth_start,
.eth_rx_adapter_stop = dpaa2_eventdev_eth_stop,
#ifdef RTE_LIBRTE_SECURITY
.crypto_adapter_caps_get = dpaa2_eventdev_crypto_caps_get,
.crypto_adapter_queue_pair_add = dpaa2_eventdev_crypto_queue_add,
.crypto_adapter_queue_pair_del = dpaa2_eventdev_crypto_queue_del,
.crypto_adapter_start = dpaa2_eventdev_crypto_start,
.crypto_adapter_stop = dpaa2_eventdev_crypto_stop,
#endif
};
static int
dpaa2_eventdev_setup_dpci(struct dpaa2_dpci_dev *dpci_dev,
struct dpaa2_dpcon_dev *dpcon_dev)
{
struct dpci_rx_queue_cfg rx_queue_cfg;
int ret, i;
/*Do settings to get the frame on a DPCON object*/
rx_queue_cfg.options = DPCI_QUEUE_OPT_DEST |
DPCI_QUEUE_OPT_USER_CTX;
rx_queue_cfg.dest_cfg.dest_type = DPCI_DEST_DPCON;
rx_queue_cfg.dest_cfg.dest_id = dpcon_dev->dpcon_id;
rx_queue_cfg.dest_cfg.priority = DPAA2_EVENT_DEFAULT_DPCI_PRIO;
dpci_dev->rx_queue[DPAA2_EVENT_DPCI_PARALLEL_QUEUE].cb =
dpaa2_eventdev_process_parallel;
dpci_dev->rx_queue[DPAA2_EVENT_DPCI_ATOMIC_QUEUE].cb =
dpaa2_eventdev_process_atomic;
for (i = 0 ; i < DPAA2_EVENT_DPCI_MAX_QUEUES; i++) {
rx_queue_cfg.user_ctx = (size_t)(&dpci_dev->rx_queue[i]);
ret = dpci_set_rx_queue(&dpci_dev->dpci,
CMD_PRI_LOW,
dpci_dev->token, i,
&rx_queue_cfg);
if (ret) {
DPAA2_EVENTDEV_ERR(
"DPCI Rx queue setup failed: err(%d)",
ret);