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eal: fix comments spelling
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[ upstream commit a9aa14d ]

Fix spelling errors in comments (found with codespell).

Note that "inbetween" is not correct in English and should
either be two words or better yet, the in can be dropped.
https://www.grammarly.com/blog/in-between-or-inbetween/

Fixes: 12f45fa ("eal/arm: read timer from PMU if enabled")
Fixes: 096ffd8 ("eal/x86: use lock-prefixed instructions for SMP barrier")
Fixes: 1d40645 ("mem: make segment preallocation OS-specific")
Fixes: bb37206 ("malloc: make heap a doubly-linked list")
Fixes: 7353ee7 ("fbarray: add API to find biggest used or free chunks")

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
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shemminger authored and kevintraynor committed May 27, 2020
1 parent 3f9b2fc commit b1f89a7
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Showing 4 changed files with 4 additions and 4 deletions.
2 changes: 1 addition & 1 deletion lib/librte_eal/bsdapp/eal/eal_memory.c
Expand Up @@ -435,7 +435,7 @@ memseg_primary_init(void)
*
* we need (N*2)-1 segments because we cannot guarantee that
* each segment will be IOVA-contiguous with the previous one,
* so we will allocate more and put spaces inbetween segments
* so we will allocate more and put spaces between segments
* that are non-contiguous.
*/
avail_segs = (hpi->num_pages[0] * 2) - 1;
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2 changes: 1 addition & 1 deletion lib/librte_eal/common/include/arch/arm/rte_cycles_32.h
Expand Up @@ -57,7 +57,7 @@ __rte_rdtsc_syscall(void)
* asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(29));
* asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r"(0x8000000f));
*
* which is possible only from the priviledged mode (kernel space).
* which is possible only from the privileged mode (kernel space).
*/
static inline uint64_t
__rte_rdtsc_pmccntr(void)
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2 changes: 1 addition & 1 deletion lib/librte_eal/common/include/arch/x86/rte_atomic.h
Expand Up @@ -55,7 +55,7 @@ extern "C" {
*
* As pointed by Java guys, that makes possible to use lock-prefixed
* instructions to get the same effect as mfence and on most modern HW
* that gives a better perfomance then using mfence:
* that gives a better performance then using mfence:
* https://shipilev.net/blog/2014/on-the-fence-with-dependencies/
* Basic idea is to use lock prefixed add with some dummy memory location
* as the destination. From their experiments 128B(2 cache lines) below
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2 changes: 1 addition & 1 deletion lib/librte_eal/common/malloc_elem.c
Expand Up @@ -157,7 +157,7 @@ malloc_elem_insert(struct malloc_elem *elem)
next_elem = NULL;
heap->last = elem;
} else {
/* the new memory is somewhere inbetween start and end */
/* the new memory is somewhere between start and end */
uint64_t dist_from_start, dist_from_end;

dist_from_end = RTE_PTR_DIFF(heap->last, elem);
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